Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device

Abstract

In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.

Claims

1. A manufacturing method of a silicon carbide semiconductor device including a JFET, comprising: preparing a semiconductor substrate including a first conductivity-type substrate made of silicon carbide, a drift layer of a first conductivity-type formed on the first conductivity-type substrate by epitaxial growth, a first gate region of a second conductivity-type formed on the drift layer by epitaxial growth, and a source region of the first conductivity-type formed on the first gate region by epitaxial growth or ion implantation; forming a trench penetrating the source region and the first gate region and reaching the drift layer, the trench having a strip shape whose longitudinal direction is set in one direction; forming a channel layer of the first conductivity-type on an inner wall of the trench by epitaxial growth; forming a second gate region of the second conductivity-type on the channel layer; planarizing the channel layer and the second gate region until the source region is exposed; performing a selective etching after the planarizing so as to remove the source region, the channel layer and the second gate region from an end portion of the trench and to form a first depressed portion deeper than a thickness of the source region at the end portion of the trench; and performing an activation anneal process at a temperature equal to or higher than 1300 C. in a mixed gas in which gas including an element working as a second conductivity-type dopant is mixed to inert gas after forming the first depressed portion so as to form a second conductivity-type layer covering a corner portion located at a boundary between a bottom surface and a side surface of the first depressed portion.

2. The manufacturing method according to claim 1, wherein as the gas including the second conductivity-type dopant, TMA or B.sub.2H.sub.6, which is gas including a p type dopant, is used.

3. The manufacturing method according to claim 1, further comprising forming an interlayer insulating layer at a region including an inside of the first depressed portion after forming the second conductivity-type layer.

4. The manufacturing method according to claim 1, further comprising: forming a second depressed portion deeper than the first gate region and reaching the drift layer in a peripheral region that surrounds a cell region in which a cell of the JFET is formed; forming a RESURF layer of the second conductivity-type in the drift layer such that the RESURF layer extends from a side surface to a bottom surface of the second depressed portion; and performing the activation anneal process after forming the RESURF layer so as to form the second conductivity-type layer covering the corner portion of the first depressed portion and to form a second conductivity-type layer covering a corner portion at a boundary between the bottom surface and the side surface of the second depressed portion.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:

(2) FIG. 1A is a diagram showing a planar pattern of a SiC semiconductor device according to a first embodiment of the present disclosure, FIG. 1B is a cross-sectional view of the semiconductor device taken along line IB-IB in FIG. 1A, FIG. 1C is a cross-sectional view of the SiC semiconductor device taken along line IC-IC in FIG. 1A, and FIG. 1D is a cross-sectional view of the SiC semiconductor device taken along line ID-ID in FIG. 1A;

(3) FIG. 2A is a diagram showing a relationship between a gate voltage and a drain current in a conventional semiconductor device, FIG. 2B is a diagram showing a relationship between a gate voltage and a drain current in the SiC semiconductor device according to the first embodiment;

(4) FIG. 3A through FIG. 3F are cross-sectional views showing manufacturing processes of the SiC semiconductor device shown in FIG. 1;

(5) FIG. 4A through FIG. 4D are perspective cross-sectional views showing manufacturing processes of the SiC semiconductor device following FIG. 3;

(6) FIG. 5A is a diagram showing a planar pattern of a conventional SiC semiconductor device, FIG. 5B is a cross-sectional view of the conventional SiC semiconductor device taken along line VB-VB in FIG. 5A, and FIG. 5C is a cross-sectional view of the conventional SiC semiconductor device taken along line VC-VC in FIG. 5A;

(7) FIG. 6 is a diagram showing a relationship between a gate voltage and a drain current in the conventional SiC semiconductor device; and

(8) FIG. 7A through FIG. 7D are perspective cross-sectional views showing a manufacturing process of the conventional SiC semiconductor device.

EMBODIMENTS FOR CARRYING OUT INVENTION

(9) Embodiments of the present disclosure will be described with reference to drawings. In each of the following embodiments, the same reference number is given to the same or equivalent parts in the drawings.

First Embodiment

(10) A first embodiment of the present disclosure will be described with reference to the accompanying drawings.

(11) A SiC semiconductor device shown in FIG. 1A through FIG. 1D is formed using an n.sup.+ type SiC substrate 1. As the n.sup.+ type SiC substrate 1, for example, an offset substrate can be used. However, a layout of cells of JFET formed in the n.sup.+ type SiC substrate 1 is unrelated to an offset direction, and the layout of the cells of JFET does not need to correspond to the offset direction.

(12) First, a basic structure of the JFET will be described. The basic structure of the JFET is a structure shown in FIG. 1B. Specifically, a trench 6 is formed in a semiconductor substrate 5 in which an n.sup. type drift layer 2, a p.sup.+ type first gate region 3, and an n.sup.+ type source region 4 are formed in sequence above an n.sup.+ type SiC substrate 1, and an n.sup. type channel layer 7 is formed from on an inner wall of the trench 6 to on a surface of the semiconductor substrate 5. On a surface of the n.sup. type channel layer 7, a p.sup.+ type second gate region 8 is formed so as to fully fill the inside of the trench 6. On a surface of the second gate region 8, a gate electrode 9 is formed. Above the gate electrode 9, a source electrode 11 is formed through an interlayer insulating layer 10. The source electrode 11 is electrically connected to the n.sup.+ type source region 4 through a contact hole formed in the interlayer insulating layer 10. In addition, on a rear surface of the n.sup.+ type SiC substrate 1, a drain electrode 12 is formed and is electrically connected to the n.sup.+ type SiC substrate 1 which operates as a drain region. By the above-described configuration, the basic structure of the JFET is formed.

(13) As shown in FIG. 1A, an opening shape of the trench 6 has a strip shape. A plurality of trenches 6 having the above-described opening shape are arranged in parallel into a stripe pattern. As shown in FIG. 1C and FIG. 1D, a depressed portion (first depressed portion) 13 is formed at an outer edge portion of the n.sup.+ type SiC substrate 1 including a periphery of an end portion of the trench 6. Accordingly, a mesa structure, in which the n.sup.+ type source region 4 is removed, is formed, and the n.sup. type channel layer 7 and the second gate region 8 are removed from the end portion of the trench 6. Thus, the n.sup.+ type source region 4 remains only at a region adjacent to the long side of each of the trenches 6, and the JFET structure is formed only at the region.

(14) In the SiC semiconductor device including the JFET having the above-described configuration, even when the n.sup. type channel layer 7 formed at the end portion of the trench 6 is thicker than a portion located at the long side of the trench 6, the JFET structure is not formed at the end portion of the trench 6. Thus, the SiC semiconductor device is not influenced by the difference between the threshold value of the JFET structure at the end portion and the threshold value of the JFET structure at the portion located at the long side of the trench J5 as the conventional configuration in which the JFET structure is formed at the end portion of the trench 6. Thus, the SiC semiconductor device has a structure that can restrict excess drain current generated when the gate voltage approaches the vicinity of the threshold value.

(15) Especially, it is preferable that, at the end portion of the trench 6, the depressed portion 13 has such a shape that a region of the n.sup. type channel layer 7 thicker than the portion formed at the long side of the trench 6 and a region within a distance longer than the thickness of the first gate region 3 from the region are removed. Accordingly, a distance between a channel portion having an increased thickness and the n.sup.+ type source region 4 becomes longer than a channel length, a drain current is fully cut also at off in the vicinity of the threshold voltage, and generation of excess drain current can be prevented.

(16) In the SiC semiconductor device according to the present embodiment, a depressed portion (second depressed portion) 14 is formed in a peripheral region that surrounds a cell region in which the cells of the JFET is formed. The depressed portion 14 is deeper than the first gate region 3 and reaches the n.sup. type drift layer 2. The depressed portion 14 is formed so as to surround the cell region. From a side surface to a bottom surface of the depressed portion 14, a p type RESURF layer 15 is formed. Because of the p type RESURF layer 15, equipotential lines can be expanded uniformly over a large area at a periphery of the cell region, and electric field concentration can be relaxed. Thus, a breakdown voltage can be improved. Although it is not shown, a p type guard ring layer may be formed at a periphery of the p type RESURF layer 15. A peripheral high breakdown-voltage structure can be formed by the p type RESURF layer 15 and the p type guard ring layer, and the breakdown voltage of the SiC semiconductor device can be improved.

(17) At the corner portion of the depressed portion 13, specifically, at the boundary portion between the bottom surface and the side surface of the depressed portion 13, a p type layer 16 is formed. The p type layer 16 is intentionally formed in an activation anneal process described later. A thickness of the p type layer 16 is not limited. The p type layer 16 is formed at least so as not to be n type. For example, the p type layer 16 has an impurity concentration equal to or higher than 110.sup.18 cm.sup.3.

(18) Similarly, at the corner portion of the depressed portion 14, specifically, at the boundary portion between the bottom surface and the side surface of the depressed portion 14, a p type layer 17 is formed on a surface of the p type RESURF layer 15. The p type layer 17 is also intentionally formed in the activation anneal process described later. A thickness of the p type layer 17 is not limited. The p type layer 17 is formed at least so as not to be n type. For example, the p type layer 17 has an impurity concentration equal to or higher than 110.sup.18 cm.sup.3.

(19) FIG. 2A is a diagram showing a relationship between a gate voltage and a drain current in the conventional semiconductor device in which the n.sup.+ type source region 4 remains at the end portion of the trench 6. FIG. 2B is a diagram showing a relationship between a gate voltage and a drain current in the SiC semiconductor device according to the present embodiment. As shown in FIG. 2A and FIG. 2B, in the structure according to the present embodiment, a drain current does not flow when the gate voltage approaches the vicinity of the threshold value as a case of the conventional structure, and the gate voltage flows for the first time when the gate voltage becomes the threshold value. Also from this experimental result, it can be confirmed that the SiC semiconductor device has a structure that can restrict excess drain current generated when the gate voltage approaches the vicinity of the threshold value.

(20) In addition, the p type layer 16 is formed at the corner portion of the depressed portion 13. Thus, the p type layer 16 and the first gate region 3 or the second gate region 8 have the same conductivity-type and a high concentration junction (PN junction of high concentration regions) is not formed therebetween. Thus, the SiC semiconductor device can prevent that the drain potential is revealed above the first gate region 3 and thereby dropping the breakdown voltage between the gate and the drain and can prevent generation of a high concentration junction leakage (gate leakage or drain leakage). In addition, the corner portion of the depressed portion 13 is filled with the p type layer 16 and has a rounded smooth shape. Thus, at the corner portion of the depressed portion 13, a generation of a crack in the interlayer insulating layer 10 formed on the depressed portion 13 can be prevented, and a leakage between the gate and the source due to a crack can be prevented.

(21) Furthermore, also at the corner portion of the depressed portion 14, the p type layer 17 is formed. Thus, the p type layer 17 and the p type RESURF layer 15 have the same conductivity-type and a PN junction is not formed therebetween. Therefore, a drop in drain breakdown voltage can be prevented. In addition, the corner portion of the depressed portion 14 is filled with the p type layer 17 and has a rounded smooth shape. Thus, at the corner portion of the depressed portion 14, a generation of a crack in the interlayer insulating layer 10 formed on the depressed portion 14 can be prevented, and when the p type RESURF layer 15 is regarded as an anode and an n.sup.+ type SiC substrate 1 and the n.sup. type drift layer 2 are regarded as a cathode, a leakage between the anode and the cathode due to a crack can be prevented.

(22) A manufacturing method of the SiC semiconductor device according to the present embodiment will be described with reference to FIG. 3A through FIG. 3F and FIG. 4A through FIG. 4D. FIG. 3A, FIG. 3C, FIG. 3E show states of a cross section corresponding to FIG. 1B in manufacturing processes, and FIG. 3B, FIG. 3D, FIG. 3F show states of a cross section corresponding to FIG. 1D in the manufacturing processes. FIG. 4 is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 3E and FIG. 3F.

(23) In the process shown in FIG. 3A, FIG. 3B, the n.sup. type drift layer 2, the p.sup.+ type first gate region 3, and the n.sup.+ type source region 4 are formed in sequence by epitaxial growth on the surface of the n.sup.+ type SiC substrate 1 to form the semiconductor substrate 5.

(24) Subsequently, in the process shown in FIG. 3C, FIG. 3D, after a mask not shown and having an opening at a region where the trench 6 will be formed is arranged, the trench 6 is formed by performing anisotropic etching such as a reactive ion etching (RIE). Then, the n.sup. type channel layer 7 is formed by epitaxial growth. At this time, due to migration of the n.sup. type channel layer 7, the thickness of the n.sup. type channel layer 7 formed at the bottom and the end portion of the trench 6 become thicker than the thickness of the n.sup. type channel layer 7 formed on the surface of the sidewall of the long side of the trench 6.

(25) In addition, in the process shown in FIG. 3E and FIG. 3F, the second gate region 8 made of a p.sup.+ type layer is formed by epitaxial growth on the surface of the n.sup. type channel layer 7. After that, the second gate region 8 and the n.sup. type channel layer 7 are planarized, for example, by chemical mechanical polishing (CMP) until the n.sup.+ type source region 4 is exposed so that the second gate region 8 and the n.sup. type channel layer 7 remain only in the trench 6. Accordingly, a perspective cross-sectional structure shown in FIG. 4A is formed.

(26) Subsequently, in the process shown in FIG. 4B, a mesa structure is formed by performing a selective etching at the peripheral portion of the cell region. The depressed portions 13, 14 are formed in sequence by performing a two-step etching.

(27) First, by anisotropic etching such as RIE the n.sup.+ type source region 4 is removed from the peripheral portion of the cell region by etching to a position deeper than the n.sup.+ type source region 4. At the same time, the n.sup.+ type source region 4, the n.sup. type channel layer 7 and the second gate region 8 are partially removed from the vicinity of the end portion of the trench 6 to form the depressed portion 13. Specifically, a mask that has openings at the peripheral portion of the cell region and portions from which the n.sup.+ type source region 4, the n.sup. type channel layer 7, and the second gate region 8 are partially removed is arranged, and then the anisotropic etching is performed to form the depressed portion 13.

(28) Subsequently, anisotropic etching such as RIE is performed again using a mask that is different from the mask used in the above-described process to selectively etch an inside of the depressed portion 13 to a position deeper than the p.sup.+ type first gate region 3 at the peripheral portion of the cell region. Accordingly, the first gate region 3 is removed, and the depressed portion 14 is formed. Specifically, after a mask having an opening at a region where the depressed portion 14 will be formed (in the peripheral portion of the cell region, a peripheral side from a portion where the p type RESURF layer 15 is arranged) is arranged, anisotropic etching is performed to form the depressed portion 14.

(29) After the mask used at the etching is removed, a mask that has an opening at a region where the p type RESURF layer 15 and the p type guard ring layer, which is not shown, will be formed, is arranged, and p type impurities are ion-implanted from above the mask. Accordingly, as shown in FIG. 4C, the p type RESURF layer 15 and the like are formed. After that, the activation anneal process is performed in a gas atmosphere including an element that becomes a p type dopant, for example, in a mixed gas atmosphere of inert gas such as Ar and trimethyl aluminum (TMA) or B.sub.2H.sub.6 at a temperature equal to or higher than 1300 C., for example, at 1600 C. Accordingly, the impurities doped in each of the impurity layers such as p type RESURF layer 15 are activated.

(30) In addition, at the same time, the p type layer 16 is formed at the corner portion at the boundary portion between the bottom surface and the side surface of the depressed portion 13, and the p type layer 17 is formed at the corner portion at the boundary portion between the bottom surface and the side surface of the depressed portion 14. At this time, the impurity concentration of the p type layers 16, 17 is set to be equal to or higher than 110.sup.18 cm.sup.3 by controlling the amount of gas that includes the element becoming the p type dopant and is included in the atmosphere gas. In a case where gas that includes an element becoming a p type dopant is not introduced, a small amount of nitrogen (N) that is naturally present in the atmosphere is easily introduced in the growing SiC, and n type impurities are doped. An n type impurity concentration at this time is within a range from 110.sup.17 to 110.sup.18 cm.sup.3. Thus, when the p type impurity concentration of the p type layers 16, 17 is set to be equal to or higher than 110.sup.18 cm.sup.3, if the p type impurities are compensated by the n type impurities, the p type layer 16, 17 do not become at least n type.

(31) TMA or B.sub.2H.sub.6 is used as the gas including the p type dopant and used for forming the p type layers 16, 17. The p type layers 16, 17 can be formed using gas that is generally used in epitaxial growth of SiC, and the p type impurity concentration of the p type layers 16, 17 can be easily controlled, for example, by controlling gas flow rate.

(32) Although the later processes are not shown, the SiC semiconductor device is manufactured by performing manufacturing processes similar to the conventional art, such as a forming process of the gate electrode 9, a forming process of the interlayer insulating layer 10, a forming process of the contact holes, a forming process of the source electrode 11, and a forming process of the drain electrode 12.

(33) As described above, in the present embodiment, in the structure in which the depressed portion 13 is formed so that the JFET structure is not formed at the end portion of the trench 6 in which the second gate region 8 is disposed, the p type layer 16 is formed at the corner portion located at the boundary portion between the bottom surface and the side surface of the depressed portion 13. Thus, the p type layer 16 and the first gate region 3 or the second gate region 8 of p.sup.+ type have the same conductivity-type and a high concentration junction (PN junction of high concentration regions) is not formed therebetween. Thus, the SiC semiconductor device can prevent that the drain potential is revealed above the first gate region 3 and thereby dropping the breakdown voltage between the gate and the drain and can prevent generation of a high concentration junction leakage (gate leakage or drain leakage).

(34) In addition, the p type layer 17 is formed also on the corner portion of the depressed portion 14. Thus, the p type layer 16 and the p type RESURF layer 15 have the same conductivity type and a PN junction is not formed therebetween. Therefore, a drop in the drain breakdown voltage can be prevented.

Other Embodiments

(35) In each of the above-described embodiments, the n-channel type JFET in which the channel region is set at the n.sup. type channel layer 7 is taken as an example. However, the present disclosure can be applied to a p-channel type JFET in which conductivity types of the components are reversed.

(36) In the above-described embodiment, the n.sup.+ type source region 4 formed by epitaxial growth is described. However, the n.sup.+ type source region 4 may be formed by ion-implanting n-type impurities to the first gate region 3.

(37) In the above-described embodiment, the present disclosure is applied to a structure in which both of the p type layers 16, 17 are formed. However, the present disclosure can be applied to a structure that includes at least one of them. In each of the above-described embodiments, as the trench 6 that has the strip shape whose longitudinal direction is set to one direction, the rectangular shape is taken as an example. However, the trench 6 does not necessarily have a rectangular shape and the trench 6 may have a strip shape such as a parallelogram shape or a hexagonal shape in which center parts of end portions are sharpened (e.g., a shape in which only opposite two sides of a hexagon are elongated).