SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF

Abstract

A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Claims

1. A semiconductor component comprising, in a cross section of a gate width direction: a semiconductor substrate; a plurality of grooves formed on or over a surface of the semiconductor substrate to form a patterned surface with a plurality of raised portions and a plurality of recessed portions, the recessed portions are a plurality of bottoms of the grooves; an insulating film on or over the raised portions and the recessed portions, a part of the insulating film is formed in the grooves; and a metallic material on or over the raised portions and the recessed portions, a part of the metallic material is formed in the grooves, wherein, the insulating film on or over the raised portions has a function of gate insulating film, and the metallic material over the gate insulating film has a function of gate electrode.

2. The semiconductor component according to claim 1, wherein the metallic material includes W.

3. The semiconductor component according to claim 2, wherein the metallic material further includes TiN.

4. The semiconductor component according to claim 3, wherein W and TiN are laminated to form the metallic material.

5. The semiconductor component according to claim 4, wherein the gate electrode is sandwiched between source-drain regions.

6. The semiconductor component according to claim 5, wherein the grooves extend to the semiconductor substrate and to a depth of the source-drain region.

7. The semiconductor component according to claim 1, wherein the gate electrode is formed by embedding the grooves.

8. The semiconductor component according to claim 1, wherein the gate electrode is formed after removing a dummy gate.

9. The semiconductor component according to claim 1, wherein a width of one of the raised portions is wider than a width of one of the recessed portions.

10. The semiconductor component according to claim 9, wherein the width of one of the recessed portions is narrower than a depth of one of the grooves.

11. The semiconductor component according to claim 10, wherein the one of the grooves includes a slanted side surface with respect to a depth direction of the semiconductor substrate.

12. The semiconductor component according to claim 1, further comprising an element isolation region including a top surface, the top surface is higher than both a height of the raised portions and a height of the recessed portions.

13. The semiconductor component according to claim 12, the top surface is higher than a top surface of source-drain regions.

14. The semiconductor component according to claim 1, wherein the part of the metallic material is formed to fill the grooves complementary.

15. A semiconductor component comprising, in a cross section of a gate width direction: a semiconductor substrate; a plurality of grooves formed on or over a surface of the semiconductor substrate to form a patterned surface with a plurality of raised portions and a plurality of recessed portions, the recessed portions are a plurality of bottoms of the grooves; a gate insulating film on or over the raised portions and the recessed portions, a part of the gate insulating film is formed in the grooves; and a gate electrode on or over the raised portions and the recessed portions, a part of the gate electrode is formed in the grooves, wherein the gate electrode comprises a metallic material.

16. The semiconductor component according to claim 15, wherein the gate electrode includes W.

17. The semiconductor component according to claim 16, wherein the gate electrode further includes TiN.

18. The semiconductor component according to claim 17, wherein W and TiN are laminated to form the gate electrode.

19. The semiconductor component according to claim 18, wherein the raised portions are sandwiched between source-drain regions.

20. The semiconductor component according to claim 19, wherein the grooves extend to the semiconductor substrate and to a depth of the source-drain region.

21. The semiconductor component according to claim 15, wherein the gate electrode is formed by embedding the grooves.

22. The semiconductor component according to claim 15, wherein the gate electrode is formed after removing a dummy gate.

23. The semiconductor component according to claim 15, wherein a width of one of the raised portions is wider than a width of one of the recessed portions.

24. The semiconductor component according to claim 23, wherein the width of one of the recessed portions is narrower than a depth of one of the grooves.

25. The semiconductor component according to claim 24, wherein the one of the grooves includes a slanted side surface with respect to a depth direction of the semiconductor substrate.

26. The semiconductor component according to claim 15, further comprising an element isolation region including a top surface, the top surface being higher than both a height of the raised portions and a height of the recessed portions.

27. The semiconductor component according to claim 26, the top surface is higher than a top surface of source-drain regions.

28. The semiconductor component according to claim 15, wherein the part of the gate electrode is formed to fill the grooves complementary.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. 1 is a diagram illustrating a semiconductor component according to First Embodiment of the present invention.

[0031] FIG. 2 is a diagram illustrating the semiconductor component according to First Embodiment of the present invention.

[0032] FIG. 3 is a diagram illustrating the semiconductor component according to First Embodiment of the present invention.

[0033] FIG. 4 is a diagram illustrating the semiconductor component according to First Embodiment of the present invention.

[0034] FIG. 5 is a diagram illustrating a relevant portion of the semiconductor component in one of the steps of a manufacturing method according to First Embodiment of the present invention.

[0035] FIGS. 6A and 6B are diagrams illustrating a relevant portion of the semiconductor component in one of the steps of the manufacturing method according to First Embodiment of the present invention.

[0036] FIG. 7 is a diagram illustrating a relevant portion of the semiconductor component in one of the steps of a manufacturing method according to First Embodiment of the present invention.

[0037] FIGS. 8A and 8B are diagrams illustrating a relevant portion of the semiconductor component in one of the steps of the manufacturing method according to First Embodiment of the present invention.

[0038] FIG. 9 is a diagram illustrating a relevant portion of the semiconductor component in one of the steps of a manufacturing method according to First Embodiment of the present invention.

[0039] FIGS. 10A and 10B are diagrams illustrating a relevant portion of the semiconductor component in one of the steps of the manufacturing method according to First Embodiment of the present invention.

[0040] FIG. 11 is a diagram illustrating a relevant portion of the semiconductor component in one of the steps of a manufacturing method according to First Embodiment of the present invention.

[0041] FIGS. 12A and 12B are diagrams illustrating a relevant portion of the semiconductor component in one of the steps of the manufacturing method according to First Embodiment of the present invention.

[0042] FIG. 13 is a diagram illustrating a relevant portion of the semiconductor component in one of the steps of a manufacturing method according to First Embodiment of the present invention.

[0043] FIGS. 14A and 14B are diagrams illustrating a relevant portion of the semiconductor component in one of the steps of the manufacturing method according to First Embodiment of the present invention.

[0044] FIG. 15 is a diagram illustrating a relevant portion of the semiconductor component in one of the steps of a manufacturing method according to First Embodiment of the present invention.

[0045] FIGS. 16A and 16B are diagrams illustrating a relevant portion of the semiconductor component in one of the steps of the manufacturing method according to First Embodiment of the present invention.

[0046] FIG. 17 is a diagram illustrating a semiconductor component according to Second Embodiment of the present invention.

[0047] FIG. 18 is a diagram illustrating a variation of the semiconductor component according to Second Embodiment of the present invention.

[0048] FIGS. 19A and 19B are diagrams illustrating a semiconductor component according to an embodiment of the present invention.

[0049] FIGS. 20A and 20B are diagrams illustrating a semiconductor component according to an embodiment of the present invention.

[0050] FIG. 21 is a diagram illustrating a semiconductor component.

[0051] FIG. 22 is a diagram illustrating the semiconductor component.

[0052] FIG. 23 is a diagram illustrating the semiconductor component.

[0053] FIG. 24 is a diagram illustrating the semiconductor component.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] The following describes embodiments of the present invention.

[0055] Descriptions will be given in the following order.

[0056] 1. First Embodiment (rectangular grooves)

[0057] 2. Second Embodiment (tapered grooves)

[0058] 3. Other

1. First Embodiment

(A) Device Configuration

[0059] FIG. 1 to FIG. 4 are diagrams illustrating a semiconductor component 100 according to First Embodiment of the present invention.

[0060] FIG. 1 shows a top surface of the semiconductor component 100. FIG. 2 to FIG. 4 are cross sections of the semiconductor component 100. Specifically, FIG. 2 is a cross section perpendicular to the plane of the paper at X1-X2 of FIG. 1. FIG. 3 is a cross section perpendicular to the plane of the paper at Y1-Y2 of FIG. 1. FIG. 4 is a cross section perpendicular to the plane of the paper at Y3-Y4 of FIG. 1.

[0061] As illustrated in FIG. 1 to FIG. 4, the semiconductor component 100 includes a semiconductor substrate 101. The semiconductor substrate 101 is, for example, a monocrystalline silicon substrate, and includes an element isolation region 200 of insulating material such as silicon oxide. A semiconductor device 110 is provided on the semiconductor substrate 101 in a portion parted by the element isolation region 200.

[0062] As illustrated in FIG. 1, the semiconductor device 110 is an FET, and includes a gate electrode 111g and a pair of source-drain regions 112s and 112d.

[0063] As illustrated in FIG. 1, the gate electrode 111g forming the semiconductor device 110 is formed so as to be sandwiched between the source-drain regions 112s and 112d on a plane of the semiconductor substrate 101 (xy plane). Further, the gate electrode 111g extends in the x direction perpendicular to the channel length direction y along which the source-drain regions 112s and 112d are disposed. In other words, the gate electrode 111g is formed so that its longer side is along the channel width direction x.

[0064] The gate electrode 111g is formed using conductive materials, including, for example, metallic materials such as Ti, Ru, Hf, Ir, Co, W, Mo, La, Ni, Cu, and Al, and Si compounds and N compounds of these. These conductive materials may be appropriately combined to form the gate electrode 111g. Further, more than one conductive material may be appropriately laminated to form the gate electrode 111g.

[0065] As illustrated in FIG. 2, the gate electrode 111g is formed on the surface of the semiconductor substrate 101 via a gate insulating film 111z. The gate insulating film 111z is formed using high-dielectric (High-k) material, for example, such as oxides of metal selected from Al, Y, Zr, La, Hf, and Ta, and oxide silicide, nitride oxide, and oxide nitride silicide.

[0066] As illustrated in FIG. 2, the semiconductor substrate 101 has a patterned surface formed along the longitudinal direction x of the gate electrode 111g. The gate electrode 111g is formed so as to cover the patterned surface via the gate insulating film 111z. In the present embodiment, recurrently occurring grooves M of equal pitches are provided in the width direction x of a channel 101c, with the side surfaces situated along the depth direction z of the semiconductor substrate 101. The gate electrode 111g and the gate insulating film 111z are formed on the surfaces of raised portions CV and recessed portions TR of the grooves M.

[0067] As illustrated in FIG. 2, the gate electrode 111g formed on the patterned surface has a flat surface, and is thicker in portions corresponding to the recessed portions TR than in portions corresponding to the raised portions CV.

[0068] As illustrated in FIG. 3, in the raised portions CV, the gate electrode 111g is sandwiched between the source-drain regions 112s and 112d on the surface of the semiconductor substrate 101. In the recessed portions TR on the surface of the semiconductor substrate 101, as illustrated in FIG. 4, the gate electrode 111g is sandwiched between the source-drain regions 112s and 112d inside the recessed portions TR.

[0069] As illustrated in FIG. 3 and FIG. 4, the gate electrode 111g has different cross sectional shapes and different channel lengths L12 and L34 for the raised portions CV and the recessed portions TR.

[0070] Specifically, as illustrated in FIG. 3, in the raised portions CV, the gate electrode 111g is formed on the flat, non-recessed surface of the semiconductor substrate 101 via the gate insulating film 111z. Thus, in the raised portions CV, the channel length L12 corresponds to the distance between the source-drain regions 112s and 112d.

[0071] In contrast, in the recessed portions TR, the gate insulating film 111z is formed to cover the surfaces of the recessed grooves formed in the depth direction z of the semiconductor substrate 101 from the surface of the semiconductor substrate 101, as illustrated in FIG. 4. The gate electrode 111g fills the grooves provided with the gate insulating film 111z. Thus, in the recessed portions TR, the channel length L34 corresponds to the sum of the distance between the source-drain regions 112s and 112d and the distance of the gate electrode 111g filling the grooves to a depth of the source-drain regions 112s and 112d in the depth direction z.

[0072] That is, in the present embodiment, as illustrate in FIG. 3 and FIG. 4, the gate electrode 111g is formed in such a manner that the channel length L34 in the recessed portions TR is longer than the channel length L12 in the raised portions CV.

[0073] As illustrated in FIG. 3 and FIG. 4, side walls SW are provided on the side surfaces of the gate electrode 111g, sandwiching the gate electrode 111g on the surface of the semiconductor substrate 101.

[0074] As illustrated in FIG. 3 and FIG. 4, the low-concentration impurity regions 112Ls and 112Ld in the source-drain regions 112s and 112d forming the semiconductor device 110J are provided beneath the side walls SW. The low-concentration impurity regions 112Ls and 112Ld are so-called extension regions, and are formed as shallow junction regions at the surface of the semiconductor substrate 101.

[0075] As illustrated in FIG. 3 and FIG. 4, the high-concentration impurity regions 112Hs and 112Hd in the source-drain regions 112s and 112d are formed on the both sides of the low-concentration impurity regions 112Ls and 112Ld. The high-concentration impurity regions 112Hs and 112Hd are provided as deeper junction regions than the low-concentration impurity regions 112Ls and 112Ld. The high-concentration impurity regions 112Hs and 112Hd are covered with a silicide film, and are in contact with a source electrode and a drain electrode (neither is illustrated).

[0076] In this manner, the semiconductor device 110 forms an FET of so-called an LDD (Lightly Doped Drain) structure. As illustrated in FIG. 2 to FIG. 4, the semiconductor device 110 is covered with an interlayer insulating film such as a planarizing film SZ.

(B) Manufacturing Method

[0077] A manufacturing method of the semiconductor component is described below with regard to relevant portions.

[0078] FIG. 5 to FIGS. 16A and 16B are diagrams illustrating relevant portions of the semiconductor component in each step of the manufacturing method according to First Embodiment of the present invention.

[0079] As with FIG. 2, FIGS. 5, 7, 9, 11, 13, and 15 are cross sections perpendicular to the plane of the paper at X1-X2 of FIG. 1. Further, as with FIG. 3 or 4, FIGS. 6A and 6B, 8A and 8B, 10A and 10B, 12A and 12B, 14A and 14B, and 16A and 16B are cross sections perpendicular to the plane of the paper at Y1-Y2 or Y3-Y4 of FIG. 1. Specifically, FIGS. 6A, 8A, 10A, 12A, 14A, and 16A are cross sections perpendicular to the plane of the paper at Y1-Y2 of FIG. 1. FIGS. 6B, 8B, 10B, 12B, 14B, and 16B are cross sections perpendicular to the plane of the paper at Y3-Y4 of FIG. 1.

[0080] As illustrated in FIG. 5 to FIGS. 16A and 16B step by step, the semiconductor device (FET) 110 is formed by so-called a damascene process in the present embodiment.

(1) Transistor Forming Step

[0081] First, the transistor forming step represented in FIG. 5 and FIGS. 6A and 6B is performed for the manufacture of the semiconductor component.

[0082] As illustrated in FIG. 5 and FIGS. 6A and 6B, a transistor Tr is formed using an ordinary MOS process in a region of the semiconductor substrate 101 parted by the element isolation region 200. In the present embodiment, the transistor Tr formed on the surface of the semiconductor substrate 101 includes a dummy gate electrode 111gd via a dummy gate insulating film 111zd.

[0083] In this step, the dummy gate electrode 111gd is formed via the dummy gate insulating film 111zd on the surface of the semiconductor substrate 101 in a portion where a gate insulating film 111z and a gate electrode 111g of the semiconductor device 110 are to be formed. Further, in this step, the source-drain regions 112s and 112d of the semiconductor device 110 are formed on the both sides of the dummy gate electrode 111gd, prior to forming the gate insulating film 111z and the gate electrode 111g of the semiconductor device 110.

[0084] Specifically, first, the element isolation region 200 of an STI (Shallow Trench Isolation) structure is formed on the surface of the semiconductor substrate 101. The surface of the semiconductor substrate 101 is then oxidized to form a protective film of silicon oxide (not illustrated) for the prevention of channeling. For adjustment of threshold value, this is followed by ion implantation of impurities in a region of the semiconductor substrate 101 where the transistor Tr is to be provided. The protective film is removed thereafter.

[0085] Thereafter, as illustrated in FIG. 5 and FIGS. 6A and 6B, the dummy gate insulating film 111zd and the dummy gate electrode 111gd are formed.

[0086] For example, the surface of the semiconductor substrate 101 is subjected to a thermal oxidation process to deposit a silicon oxide film having a thickness of about 1 to 3 nm (not illustrated). Then, a polysilicon film having a thickness of about 30 to 100 nm (not illustrated) is deposited on the silicon oxide film (not illustrated) using, for example, a CVD method. The polysilicon film (not illustrated) is then patterned to form the dummy gate electrode 111gd. The silicon oxide film (not illustrated) is patterned to form the dummy gate insulating film 111zd.

[0087] Thereafter, as illustrated in FIGS. 6A and 6B, the source-drain regions 112s and 112d are formed.

[0088] First, as illustrated in FIGS. 6A and 6B, the low-concentration impurity regions 112Ls and 112Ld of the source-drain regions 112s and 112d are formed.

[0089] The low-concentration impurity regions 112Ls and 112Ld are formed by ion implantation of impurities on the surface of the semiconductor substrate 101, using the dummy gate electrode 111gd as a mask.

[0090] Specifically, n-type impurities such as As and P are injected for the formation of an n-type MOS semiconductor device 110. For p-type MOS, p-type impurities such as B and In are injected.

[0091] Then, as illustrated in FIGS. 6A and 6B, the side walls SW are formed.

[0092] For the formation of the side walls SW, an insulating film (not illustrated) is deposited so as to cover the dummy gate electrode 111gd on the surface of the semiconductor substrate 101. For example, a silicon nitride film is deposited as the insulating film (not illustrated), using a CVD method. The insulating film (not illustrated) is etched back to provide the side walls SW.

[0093] Then, as illustrated in FIGS. 6A and 6B, the high-concentration impurity regions 112Hs and 112Hd of the source-drain regions 112s and 112d are formed.

[0094] The high-concentration impurity regions 112Hs and 112Hd are formed by ion implantation of impurities on the surface of the semiconductor substrate 101, using the dummy gate electrode 111gd and the side walls SW as a mask.

[0095] Specifically, as in the case of the low-concentration impurity regions 112Ls and 112Ld, n-type impurities such as As and P are injected for n-type MOS. For p-type MOS, p-type impurities such as B and In are injected.

[0096] This is followed by a heat treatment to activate the injected impurities, and form the source-drain regions 112s and 112d.

[0097] A silicide film (not illustrated) is formed on the surface of the high-concentration impurity regions 112Hs and 112Hd. For example, a silicide film (not illustrated) as the silicide of metals such as Co, Ni, and Pt is formed.

[0098] In this manner, the transistor Tr of a different shape from the gate electrode 111g and the gate insulating film 111z of the semiconductor device 110 of FIG. 1 to FIG. 4 is formed in this step. Specifically, as illustrated in FIG. 5 and FIGS. 6A and 6B, the transistor Tr is formed to include the dummy gate electrode 111gd and the dummy gate insulating film 111zd that extend along the width direction x of the channel 101c on the surface (xy plane) of the semiconductor substrate 101, but not along the depth direction z of the semiconductor substrate 101.

(2) Planarizing Film Forming Step

[0099] Thereafter, as illustrated in FIG. 7 and FIGS. 8A and 8B, a planarizing film forming step is performed.

[0100] As illustrated in FIG. 7 and FIGS. 8A and 8B, a planarizing film SZ is formed on the surface of the semiconductor substrate 101.

[0101] In this step, the planarizing film SZ is formed on the surface of the semiconductor substrate 101 in such a manner as to expose the top surface of the dummy gate electrode 111gd in the transistor Tr formed in the previous step, and to cover the other portions.

[0102] Specifically, first, a silicon oxide film (not illustrated) is formed on the surface of the semiconductor substrate 101 so as to cover the transistor Tr. Then, for example, a CMP (Chemical Mechanical Polish) process is performed on the silicon oxide film (not illustrated) until the top surface of the dummy gate electrode 111gd is exposed.

[0103] As a result, the planarizing film SZ is formed, as illustrated in FIG. 7 and FIGS. 8A and 8B.

(3) Dummy Gate Electrode and Dummy Gate Insulating Film Removing Step

[0104] Thereafter, as illustrated in FIG. 9 and FIGS. 10A and 10B, a dummy gate electrode and dummy gate insulating film removing step is performed.

[0105] As illustrated in FIG. 9 and FIGS. 10A and 10B, the dummy gate electrode 111gd and the dummy gate insulating film 111zd of the transistor Tr formed in the previous step are removed. As a result of this step, the surface of the semiconductor substrate 101 that has been covered with the dummy gate electrode 111gd and the dummy gate insulating film 111zd is exposed, and an opening is formed in this surface portion.

[0106] Specifically, the dummy gate electrode 111gd is removed first. For example, the dummy gate electrode 111gd is selectively removed by dry etching, using Cl.sub.2 gas, HBr gas, and a mixed gas of Cl.sub.2 and HBr.

[0107] Then, the dummy gate insulating film 111zd is removed. For example, the dummy gate insulating film 111zd is selectively removed by wet etching, using hydrofluoric acid.

[0108] The dummy gate electrode 111gd and the dummy gate insulating film 111zd are removed in this manner to expose the surface of the semiconductor substrate 101 between the side walls SW.

(4) Groove Forming Step

[0109] As illustrated in FIG. 11 and FIGS. 12A and 12B, a groove forming step is performed.

[0110] As illustrated in FIG. 11 and FIGS. 12A and 12B, the grooves M are formed on the surface of the semiconductor substrate 101.

[0111] In this step, the grooves M are provided on the surface of the semiconductor substrate 101 by etching the opening surface of the semiconductor substrate 101. As a result, the patterned surface is formed on the surface of the semiconductor substrate 101.

[0112] Specifically, as illustrated in FIG. 11 and FIGS. 12A and 12B, a resist pattern PR is formed. The resist pattern PR is formed so as to cover the surface of the semiconductor substrate 101 where the raised portions CV are to be formed, and to expose the surface where the recessed portions TR are to be formed. In other words, though not illustrated, the resist pattern PR is formed to include portions that extend in stripes along the channel length direction y on the top surface.

[0113] Then, the semiconductor substrate 101 is etched to form the grooves M on the semiconductor substrate 101, using the resist pattern PR as a mask. For example, the grooves M are formed at a depth of about 30 to 60 nm by dry etching using a mixed gas of Cl.sub.2 and O.sub.2. Then, by a post process using hydrofluoric acid, the damaged layer (not illustrated) created by the etching is removed, followed by the removal of the resist pattern PR.

[0114] As a result, the raised portions CV and the recessed portions TR are formed on the surface of the semiconductor substrate 101, rendering the surface patterned.

(5) High-Dielectric Film Forming Step

[0115] As illustrated in FIG. 13 and FIGS. 14A and 14B, a high-dielectric film forming step is performed.

[0116] As illustrated in FIG. 13 and FIGS. 14A and 14B, a high-dielectric film 111zm is deposited so as to cover the patterned surface of the semiconductor substrate 101. In the present embodiment, the high-dielectric film 111zm is formed to cover not only the patterned surface of the semiconductor substrate 101, but the top surface of the planarizing film SZ and the opposing side surfaces of the side walls SW.

[0117] Specifically, as illustrated in FIG. 13, the high-dielectric film 111zm is formed so as to cover the surfaces of the raised portions CV and the recessed portions TR on the semiconductor substrate 101. As a result, as illustrated in FIG. 14A, the high-dielectric film 111zm covers the top surface of the raised portions CV. In the recessed portions TR, as illustrated in FIG. 14B, the high-dielectric film 111zm covers the bottom and side surfaces of the grooves M formed on the semiconductor substrate 101.

[0118] The high-dielectric film 111zm is formed by, for example, depositing high-dielectric material such as those exemplified above, using a CVD method or an ALD method. For example, a 2-nm thick hafnium oxide film is formed as the high-dielectric film 111zm. Specifically, the hafnium oxide film is formed by a CVD method, using HfCl.sub.2 and NH.sub.3. The hafnium oxide film may be formed by a CVD method, using an organic Hf gas.

(6) Metal Film Forming Step

[0119] As illustrated in FIG. 15 and FIGS. 16A and 16B, a metal film forming step is performed.

[0120] As illustrated in FIG. 15 and FIGS. 16A and 16B, a metal film 111gm is formed so as to cover the patterned surface of the semiconductor substrate 101, the top surface of the planarizing film SZ, and the opposing side surfaces of the side walls SW, via the high-dielectric film 111zm.

[0121] Specifically, as illustrated in FIG. 15, the metal film 111gm is formed so as to cover the surfaces of the raised portions CV and the recessed portions TR on the semiconductor substrate 101 via the high-dielectric film 111zm. As a result, as illustrated in FIG. 16A, the metal film 111gm in the raised portions CV covers the top surface via the high-dielectric film 111zm, and fills the space between the side walls SW. In the recessed portions TR, as illustrated in FIG. 16B, the metal film 111gm covers the bottom and side surfaces of the grooves M on the semiconductor substrate 101 via the high-dielectric film 111zm, and fills the space between the side walls SW.

[0122] The metal film 111gm is formed by, for example, depositing metallic material such as those exemplified above, using a sputtering method.

(7) Gate Electrode and Gate Insulating Film Forming Step

[0123] As illustrated in FIG. 2 to FIG. 4, a gate electrode and gate insulating film forming step is performed to complete the semiconductor device 110.

[0124] The gate electrode 111g and the gate insulating film 111z illustrated in FIG. 2 to FIG. 4 are formed by processing the high-dielectric film 111zm and the metal film 111gm. In the present embodiment, the gate electrode 111g and the gate insulating film 111z are formed by a planarization process, by which the high-dielectric film 111zm and the metal film 111gm formed on the planarizing film SZ are removed.

[0125] Specifically, the metal film 111gm and the high-dielectric film 111zm are subjected to CMP to expose the top surface of the planarizing film SZ. By sequentially polishing the metal film 111gm and the high-dielectric film 111zm in this manner, the gate electrode 111g and the gate insulating film 111z are formed.

[0126] After covering the surface with the interlayer insulating film (not illustrated), the source electrode and the drain electrode (not illustrated) are formed to complete the semiconductor device 110.

(C) Review

[0127] As described above, in the present embodiment, the semiconductor device 110 is provided on the semiconductor substrate 101. The semiconductor device 110 is a field-effect transistor, and includes the gate insulating film 111z, the gate electrode 111g, and the source-drain regions 112s and 112d. In the semiconductor device 110, the gate insulating film 111z is formed on the surface of the semiconductor substrate 101. The gate electrode 111g is formed on the surface of the semiconductor substrate 101 via the gate insulating film 111z. The source-drain regions 112s and 112d are provided on the both sides of the gate electrode 111g on the semiconductor substrate 101.

[0128] In the present embodiment, the semiconductor substrate 101 has a patterned surface in a portion where the gate electrode 111g is provided. In the raised portions CV on the patterned surface of the semiconductor substrate 101, the gate insulating film 111z is formed to cover the surface of the semiconductor substrate 101 that lies on the same plane as the surface of the source-drain regions 112s and 112d. The gate electrode 111g is formed on the top surface of the gate insulating film 111z. In the recessed portions TR on the patterned surface of the semiconductor substrate 101, the gate insulating film 111z is formed to cover the surfaces of the grooves M formed toward the interior of the semiconductor substrate 101 than the surface of the source-drain regions 112s and 112d. The gate electrode 111g is provided so as to fill the grooves M provided with the gate insulating film 111z. The source-drain regions 112s and 112d are formed in the same shape for the raised portions CV and the recessed portions TR on the patterned surface of the semiconductor substrate 101.

[0129] As described above, in the present embodiment, the channel width direction x of the semiconductor device (FET) 110 is along the patterned surface. Thus, the effective channel width can be increased.

[0130] Particularly, in the present embodiment, because the side surfaces of the grooves M on the patterned surface of the semiconductor substrate 101 are along the depth direction z of the semiconductor substrate 101, the effective channel width can be effectively increased.

[0131] Further, because the channel is formed by the patterned side walls, the S factor can be improved by the same effect provided by the gate. Because the recessed portions TR have the same impurity profile as that of the raised S/D structure, the S factor can be further improved by the corner effect.

[0132] Thus, low-voltage driving can easily be realized in the present embodiment.

[0133] As described above, the gate is formed by a damascene process in the semiconductor device 110. Thus, it is not required to provide a wide patterned surface in the channel length direction y by taking into consideration the alignment of the gate electrode 111g for fabrication.

[0134] Specifically, as illustrated in FIG. 1, the patterned shape can be formed in the same width as the channel length as in region TA defined by the width of the gate electrode 111g (the distance defined by y direction) , and it is not required to form a wider patterned shape than the channel length. In other words, the surface of the semiconductor substrate 101 is patterned only in the portion directly below the gate electrode 111g.

[0135] Specifically, in the raised portions CV and the recessed portions TR, the source-drain regions 112s and 112d have a flat top surface, and the same depth in the semiconductor substrate 101.

[0136] Because the surface of the source-drain regions 112s and 112d is not patterned in the present embodiment, the source and drain electrodes (not illustrated) can easily be formed. Further, miniaturization of the source and drain electrodes can easily be realized along the channel length direction y.

[0137] Further, in the present embodiment, because the source-drain regions 112s and 112d are formed before forming the pattern, diffusion of electric field in the recessed portions TR, and the resulting higher off current in the recessed portions TR than in the raised portions CV can be prevented.

[0138] Thus, according to the present embodiment, semiconductor device characteristics can be improved, and miniaturization of the semiconductor device can be realized with ease.

2. Second Embodiment

[0139] Second Embodiment of the present invention is described below.

(A) Device Configuration, etc.

[0140] FIG. 17 is a diagram illustrating a semiconductor component 100b according to Second Embodiment of the present invention.

[0141] As is FIG. 2, FIG. 17 is a cross section perpendicular to the plane of the paper at X1-X2 of FIG. 1. The cross section perpendicular to the plane of the paper at Y1-Y2 of FIG. 17 is as shown in FIG. 3. The cross section perpendicular to the plane of the paper at Y3-Y4 of FIG. 17 is as shown in FIG. 4.

[0142] As illustrated in FIG. 17, the present embodiment differs from First Embodiment in a gate electrode 111gb and a gate insulating film 111zb of the semiconductor device 110b, as illustrated in FIG. 17. The other configuration is the same as in First Embodiment. Accordingly, descriptions will not be repeated for the overlapping parts.

[0143] As illustrated in FIG. 17, the semiconductor device 110b is an FET, and includes the gate electrode 111gb, as in First Embodiment.

[0144] As illustrated in FIG. 17, the gate electrode 111gb forming the semiconductor device 110b extends in the direction x perpendicular to the channel length direction y. In other words, the gate electrode 111gb is formed so that its longer side is along the channel width direction x.

[0145] As illustrated in FIG. 17, the gate electrode 111gb is formed on the surface of the semiconductor substrate 101 via the gate insulating film 111zb.

[0146] As illustrated in FIG. 17, the semiconductor substrate 101 has a patterned surface along the longitudinal direction x of the gate electrode 111gb. The gate electrode 111gb is formed so as to cover the patterned surface via the gate insulating film 111zb.

[0147] In the present embodiment, as illustrated in FIG. 17, recurrently occurring grooves Mb with slanted side surfaces with respect to the depth direction z of the semiconductor substrate 101 are provided. The grooves Mb have bottom surfaces along the surface (xy plane) of the semiconductor substrate 101, and an opening area that becomes smaller from the surface of the semiconductor substrate 101 downwardly towards inside. Specifically, the grooves Mb on the patterned surface of the semiconductor substrate 101 are formed to include surfaces that are slanted with respect to the depth direction z of the semiconductor substrate 101. The gate electrode 111gb and the gate insulating film 111zb are formed on the surfaces of the raised portions CVb and the recessed portions TRb formed by the grooves Mb.

[0148] As in FIG. 3 and FIG. 4 of First Embodiment, the gate electrode 111gb has different cross sectional shapes, and different channel lengths L12 and L34 for the raised portions CVb and the recessed portions TRb. That is, as in First Embodiment, the channel length L34 in the recessed portions TR is longer than the channel length L12 in the raised portions CV in the semiconductor device 110b (see FIG. 3 and FIG. 4).

[0149] In the present embodiment, the semiconductor device 110b is formed in the manner described in First Embodiment, except that (4) the groove forming step is different.

[0150] Though not illustrated, in (4) the groove forming step of the present embodiment, the resist pattern PR is formed as in First Embodiment (see FIG. 11, and FIGS. 12A and 12B).

[0151] The difference from First Embodiment is that the grooves Mb are formed on the semiconductor substrate 101 by digging the (100) plane of the semiconductor substrate 101 and exposing the (111) plane through etching of the semiconductor substrate 101 using the resist pattern PR as a mask. For example, wet etching using an alkaline etchant such as those containing KOH is performed. Specifically, etching is performed to provide the grooves Mb about 30 to 60 nm deep. The resist pattern PR is removed thereafter.

[0152] As a result, the raised portions CVb and the recessed portions TRb are formed on the surface of the semiconductor substrate 101, providing the patterned surface.

[0153] Subsequently, the (5) high-dielectric film forming step, (6) metal film forming step, and (7) gate electrode and gate insulating film forming step are sequentially performed as in First Embodiment to complete the semiconductor device 110b.

(B) Review

[0154] As described above, in the present embodiment, the semiconductor device (FET) 110b has the patterned shape formed along the channel width direction x, as in First Embodiment. In this way, the effective channel width can be increased. Further, because the channel is formed by the patterned shaped side walls, the S factor can be improved by the same effect provided by the gate.

[0155] Thus, as in First Embodiment, low-voltage driving can easily be realized also in the present embodiment.

[0156] Further, because the gate is formed by a damascene process as in First Embodiment, the effects described in First Embodiment can be desirably obtained also in this embodiment.

[0157] Thus, according to the present embodiment, semiconductor device characteristics can be improved, and miniaturization of the semiconductor device can be realized with ease.

(C) Variation

[0158] The foregoing embodiment described the grooves Mb with the bottom surfaces being horizontal to the surface (xy plane) of the semiconductor substrate 101, as illustrated in FIG. 17. However, the invention is not limited to this.

[0159] FIG. 18 is a diagram illustrating a variation of the semiconductor component 100b according to Second Embodiment of the present invention.

[0160] As is FIG. 17, FIG. 18 is a cross section perpendicular to the plane of the paper at X1-X2 of FIG. 1. The cross section perpendicular to the plane of the paper at Y1-Y2 of FIG. 18 is as shown in FIG. 3. The cross section perpendicular to the plane of the paper at Y3-Y4 of FIG. 18 is as shown in FIG. 4.

[0161] As illustrated in FIG. 18, the grooves Mb may be formed in such a manner that, instead of the bottom surface, the slanted surfaces with respect to the surface (xy plane) of the semiconductor substrate 101 intersect at the bottom. Specifically, the grooves Mb may be formed to have a triangular cross section, instead of being tapered.

3. Other

[0162] The present invention is not limited to the foregoing embodiments, and may be varied in many ways.

[0163] FIGS. 19A and 19B are diagrams illustrating a semiconductor component 100c according to an embodiment of the present invention.

[0164] As illustrated in FIGS. 19A and 19B, the source-drain regions 112s and 112d may be formed so that the level of its top surface is partly below the surface of the semiconductor substrate 101 provided with the gate insulating film 111z. Specifically, the source-drain regions 112s and 112d may be formed so that the top surface of the high-concentration impurity regions 112Hs and 112Hd is below the surface of the semiconductor substrate 101 provided with the gate insulating film 111z.

[0165] In this case, the top surface of the high-concentration impurity regions 112Hs and 112Hd is partially removed in (1) the transistor forming step of First Embodiment. Subsequently, the steps described in First Embodiment are performed to form the semiconductor component 100c.

[0166] FIGS. 20A and 20B are diagrams illustrating a semiconductor component 100d according to an embodiment of the present invention.

[0167] As illustrated in FIGS. 20A and 20B, a stress applying layer SK may be formed so as to cover the top surface of the source-drain regions 112s and 112d. For example, the stress applying layer SK may be formed so as to cover the top surface of the high-concentration impurity regions 112Hs and 112Hd of the source-drain regions 112s and 112d. The stress applying layer SK is, for example, an insulating film such as a silicon nitride film, and is formed to apply stress to the channel of the semiconductor device 110, and thus to improve carrier mobility. The stress applying layer SK is formed using a material appropriately selected to apply tensile stress, when the semiconductor device (FET) 110 is an n-type MOS transistor. When the semiconductor device (FET) 110 is a p-type MOS transistor, a material appropriately selected to apply compressional stress is used to form the stress applying layer SK.

[0168] In this case, the stress applying layer SK is formed so as to cover the components of the transistor Tr in (1) the transistor forming step of First Embodiment. Subsequently, the steps described in First Embodiment are performed to form the semiconductor component 100d.

[0169] Instead of the insulating film, a silicide film (not illustrated) that covers the top surface of the high-concentration impurity regions 112Hs and 112Hd may be formed as the stress applying layer SK.

[0170] The semiconductor components 100, 100b, 100c, and 100d of the foregoing embodiments correspond to semiconductor components according to embodiments of the present invention. The semiconductor substrate 101 of the foregoing embodiments corresponds to a semiconductor substrate according to an embodiment of the present invention. The semiconductor devices 110 and 110b of the foregoing embodiments correspond to semiconductor devices according to embodiments of the present invention. The gate electrodes 111g and 111gb of the foregoing embodiments correspond to gate electrodes according to embodiments of the present invention. The dummy gate electrode 111gd of the foregoing embodiments corresponds to a dummy gate electrode according to an embodiment of the present invention. The metal film 111gm of the foregoing embodiments corresponds to a conductive film according to an embodiment of the present invention. The gate insulating films 111z and 111zb of the foregoing embodiments correspond to gate insulating films according to embodiments of the present invention. The dummy gate insulating film 111zd of the foregoing embodiments corresponds to a dummy gate insulating film according to an embodiment of the present invention. The high-dielectric film 111zm of the foregoing embodiments corresponds to an insulating film according to an embodiment of the present invention. The source-drain regions 112d and 112s of the foregoing embodiments correspond to source-drain regions according to embodiments of the present invention. The raised portions CV and CVb of the foregoing embodiments correspond to raised portions according to embodiments of the present invention. The grooves M and Mb of the foregoing embodiments correspond to grooves according to embodiments of the present invention. The planarizing film SZ of the foregoing embodiments corresponds to a planarizing film according to an embodiment of the present invention. The recessed portions TR and TRb of the foregoing embodiments correspond to recessed portions according to embodiments of the present invention.

[0171] The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2009-298319 filed in the Japan Patent Office on Dec. 28, 2009, the entire contents of which is hereby incorporated by reference.

[0172] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.