PHASED ARRAY MODULE

Abstract

A phased array module includes a plurality of antenna boards. Each antenna board has an identical layout and has a plurality of antenna elements so positioned that together they form a matrix pattern on the antenna board and an integrated circuit containing a plurality of transceiver devices. Each transceiver is connected with an antenna element on the antenna board, such that corner antenna elements of three adjacent antenna boards of the plurality form an equilateral triangle. The matrix pattern formed by the plurality of antenna elements is square-shaped or rectangular-shaped.

Claims

1.-16. (canceled)

17. A phased array module comprising a plurality of antenna boards, each antenna board having an identical layout and comprising a plurality of antenna elements so positioned to form together a matrix pattern on the antenna board and an integrated circuit containing a plurality of transceiver devices each connected with an antenna element on said antenna board, wherein corner antenna elements of three adjacent antenna boards of said plurality form an equilateral triangle, wherein said matrix pattern formed by said plurality of antenna elements is square shaped or rectangular shaped.

18. The phased array module as in claim 17, wherein each antenna board comprises N2 antennas, N being an integer number.

19. The phased array module as in claim 17, wherein an integrated circuit of an antenna board of said plurality is arranged to act as a master node and the integrated circuits of the remaining antenna boards of said plurality are arranged to act as slave nodes, which, in receive mode, each receive as input a signal output by a different antenna element of said master node or, in transmit mode, each transmit as output a signal input to a different antenna element of said master node.

20. The phased array module as in claim 19, wherein said integrated circuit acting as master node and said integrated circuits acting as slave nodes have a same architecture.

21. The phased array module as in claim 19, wherein said integrated circuit acting as master node and said integrated circuits acting as slave nodes have a same number of antenna elements.

22. The phased array module as in claim 19, wherein said master node is connected to a baseband circuit arranged for processing baseband input/output signals.

23. The phased array module as in claim 22, further comprising an analog-to-digital converter to process said baseband signals.

24. The phased array module as in claim 19, wherein said integrated circuit arranged to act as a master node and its antenna board are on one side of a base board and said integrated circuits arranged to act as a slave nodes and their antenna board on the opposite side of said base board.

25. The phased array module as in claim 17, wherein at last one integrated circuit comprises a tone generator (308) for generating a test signal for calibration.

26. The phased array module as claim 17, wherein the clock of an integrated circuit of a slave node operable as reference is connected to the clock of the integrated circuit acting as master node.

27. The phased array module as in claim 17, wherein an integrated circuit is configured as a slave node, wherein one antenna element of the antenna board of said slave node is arranged to be reference receive antenna and two or more other antenna elements of said antenna board are arranged as transmit antenna elements.

28. The phased array module as in claim 17, wherein said antenna elements of at least one of said antenna boards have a same signal path length to said integrated circuit.

29. A method for calibrating a pair of antenna elements of a phased array module as claim 17, the method comprising: selecting in said phased array module two antenna paths to be calibrated, each antenna path comprising an antenna element of said pair and an RF frontend to which said antenna element is connected, selecting in said phased array module a further antenna element as reference antenna in a reference antenna path, said reference antenna path also comprising a RF front end to which said reference antenna is connected, wherein said reference antenna is so positioned that the geometric distance to said two antenna paths is the same, calibrating said pair of antenna elements by using the two antenna paths for transmitting a signal and the reference antenna path for receiving the transmitted signal, or vice versa, wherein the transmitted signal propagates through antenna spill over.

30. The method for calibrating as in claim 29, wherein performing said calibration comprises a gain or phase shift comparison for said two antenna paths.

31. The method for calibrating as in claim 29, wherein said two antenna elements are located on a same antenna board.

32. The method for calibrating as in claim 29, wherein said reference antenna and one of said two antenna elements are located on a same antenna board.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The invention will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.

[0037] FIG. 1 illustrates a phased array module comprising a master chip and slave chips, including antennas and connection Input/Output ports.

[0038] FIG. 2 illustrates an arrangement of slave chips of a phased array module as known in the art.

[0039] FIG. 3 illustrates how two sets of calibrated elements are obtained within the same slave node with the arrangement of FIG. 1.

[0040] FIG. 4 illustrates a cross-section of a phased array module comprising a master node and a plurality of slave nodes.

[0041] FIG. 5 illustrates a possible architecture of an integrated circuit for use in a phased array module according to the invention.

[0042] FIG. 6 illustrates the architecture of FIG. 5 adapted for use as a master node.

[0043] FIG. 7 illustrates the architecture of FIG. 5 adapted for use as a slave node.

[0044] FIG. 8 illustrates an arrangement of the slave tiles of the phased array module according to an embodiment of the invention.

[0045] FIG. 9 illustrates a chip-to-antenna signal routing for the arrangement of FIG. 8.

[0046] FIG. 10 illustrates an arrangement of the slave tiles with a 3×3 antenna array according to an embodiment of the invention.

[0047] FIG. 11 illustrates an arrangement of the slave tiles with rectangular shape according to an embodiment of the invention.

[0048] FIG. 12 illustrates the master and slave chip configuration when a certain antenna is under calibration.

[0049] FIG. 13 illustrates another configuration when the reference antenna belongs to the same chip as the antennas under calibration.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0050] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims.

[0051] Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

[0052] It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

[0053] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0054] Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

[0055] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0056] It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.

[0057] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0058] The present invention presents a phased array module comprising a plurality of antenna boards each comprising an integrated circuit. The architecture of the integrated circuits, which each contain a plurality of transceivers, and the antenna module design allow implementing autocalibration during the production phase as well as on-site calibration. In this way the test and calibration cost at production stage can be reduced. With the proposed solution, the phase and gain variance of each antenna path of the phased array module can be calibrated with low cost.

[0059] The phased array module comprises a plurality of integrated circuits (ICs) each provided on a different antenna board. The phased array module has a same high level representation as in FIG. 1 already shown previously: one of the integrated circuits and its associated antenna board can be arranged to act as a master node 101 and the other integrated circuits as slave nodes 102, to each of which a plurality of antenna 103 is connected. The connect port in the master chip is output I/O 104 and each slave chip is connected to the master chip via an input I/O 105. The various integrated circuits of the phased array module are in this description also referred to as tiles or just chips. Preferably the master chip and the slave chips have the same architecture. However, in principle the master chip may have a different architecture than the slave nodes in certain embodiments. In the description below all ICs are assumed to have a same schematic. Using only one type of chip to implement a master/slave multi-tile configuration yields clear benefits as will become apparent.

[0060] A typical cross section view of a multi-chip phased array module obtained after assembly of the chips, with one chip acting as master node and a plurality of slave nodes, on the respective antenna boards, is shown in FIG. 4. A plurality of antenna boards 107 each comprising a plurality of antenna elements, e.g. patch antennas, are connected via RF solder bumps 109 to a base board 112 of the phased array module. Each antenna board comprises an integrated circuit which is connected to the antenna board via a RF pillar 111. Typically an antenna board provided with the integrated circuit acting as the master node 110 is placed at one side of the base board and the antenna boards 107 with the chips 108 acting as slave nodes 106 are at the opposite side of the base board. Instead of patch antennas also the use of for example monopole, dipole or bowtie antennas can be envisaged.

[0061] FIG. 5 illustrates an architecture of an integrated circuit that can be applied in a phased array module according to the present invention. On chip level, there are a number of parallel transceiver front-ends (313), typically one with transmit functionality and one with receive functionality, on a same die connected with a power combiner (302)/splitter (303) and a transmit phase shifter (319)/receive phase shifter (301). Each antenna front-end (315) can be configured as either transmitter or receiver independently by means of an antenna switch (shown as ‘TR switch’ in FIG. 5). The integrated circuit also includes baseband and local oscillator (LO) (306) functionality needed for operation as a master node. The IC of FIG. 5 configured to act as a master node can up/down convert (304/305) the baseband signal by the local oscillator and mixer blocks when the paths for RF signal I/O (300) are muted and the switches (313) are closed to connect to the mixer. This is illustrated in FIG. 6. The IC of FIG. 5 can also be configured to act as a slave node by muting the LO, baseband processing blocks and mixers in FIG. 5 and closing the switches (314) to the signal I/O. The final configuration so obtained is shown in FIG. 7. In that case, the splitter (303) and combiner (302) of the slave node transmit and receive the modulated mm-wave signal via the signal I/O interface (311/312) connected to the master node. To steer the beam at each slave node transceiver element, the phase shifter (301/319) at each signal path controls the signal phase independently.

[0062] FIG. 6 illustrates an integrated circuit acting as a master node and its connection with a number of ICs (for example M=16) acting as slave nodes to form all together a phased array transceiver module under normal operation. Antennas (403) are connected in the slave nodes via each antenna I/O interface (404). In this case a master chip (400) with M I/O ports to connect to M slave chips, which are each provided with N antennas, form a M×N-antenna module. A baseband IC (405) processes the baseband input/output signals.

[0063] FIG. 7 illustrates an IC being operative as a slave node. The LO and baseband parts are disabled where the RF amplifier for Rx (501) and for Tx (502) are connected to the signal IO (503), which is further connected to the master chip. It is noted that under normal operation a slave node IC is configured either as a transmitter or as a receiver for all antenna paths simultaneously, because the I/O interface (503) is shared by the receive amplifier (501) and the transmit amplifier (502) of the slave node.

[0064] A calibration is performed by comparing each time e.g. the gain and/or phase shift for two antenna paths using a reference antenna path where the active antenna paths and reference antenna path are from the same mother board (112). An antenna path includes an antenna element and an RF frontend formed by the antenna front end (315) and a phase shifter (301,319). In receive mode, the gain is adjusted by low-noise amplifier, LNA, (317) and phase shifter (301). In transmit mode, the gain is adjusted by power amplifier, PA, (318) and phase shifter (319) It is noted that the propagation occurs through antenna leakage/spill over where no explicit electromagnetic coupler is required. This results in a simpler circuit implementation. The chip the reference antenna is connected to, is referred to as the reference chip. An antenna path comprises the antenna element itself as well as the RF frontend to which the antenna is connected. The two RF frontends with their respective antennas may belong to a same slave node or to two different nodes. Also the reference antenna that is part of the reference antenna path, may be located on the antenna board containing one of the antennas under calibration or on the antenna board of a different slave node. If the antennas are calibrated in a transmit mode, the integrated circuit the reference antenna is connected to, is referred to as a reference receiver. If the antennas are calibrated in a receive mode, the integrated circuit the reference antenna is connected to, is referred to as a reference transmitter.

[0065] For calibration purposes, the integrated circuit of FIG. 5 also includes a tone generation block (308) and the calibration DAC (307) that is activated in the chip configured as master node when two antenna paths are to be calibrated in transmit mode and the master chip thus operates as transmitter. In this case, two slave antenna frontends are configured as slave transmitter and cascaded to the master node. As already mentioned, the two slave antenna frontends may belong to a same slave node or to two different slave nodes. Thanks to the distribution of reference frequency (315) across the board through the module, the transmit and receive node are well synchronized; thus no third part external circuit/equipment is needed.

[0066] Similarly, when two slave antenna frontends are configured as receiver in calibration, the slave receiver is connected to the master IOs (311/312). In the master chip the downconversion mixer (304) is enabled. The baseband signal goes to a calibration ADC block (309) in the master chip, where the digitally quantized gain and phase information is accessible via a Serial Peripheral Interface (SPI) port (310). The integrated circuit of one specific node operates as reference transmitter and its tone generator (308), DAC (307), LO (306) and upconversion mixer (305) are enabled.

[0067] In order to be able to calibrate each slave node, i.e. to calibrate all antenna paths of that node, the node needs an antenna path to be used as a reference antenna path, as already mentioned. Calibration of the phase shift or gain of each pair of antennas paths is performed with respect to the reference antenna. Note that for any slave node the pair of antennas under calibration may belong to a same IC or may contain one antenna of that slave IC and one antenna of a neighbouring slave IC.

[0068] The present invention presents a phased array module comprising a plurality of slave nodes so arranged that the drawback is overcome that the calibration is to be performed separately for different subsets (see FIG. 3). It is recalled that to perform a calibration over any two signal paths it is required to find a reference transmitter or receiver antenna so positioned that the geometric distance to the two paths under calibration is the same. To achieve a low-loss signal routing from one slave tile to N antenna patches while maintaining a full coverage of antenna elements, an offset is introduced between either rows or columns of different slave tiles to form an equilateral triangle (75) between the antenna elements of antenna boards of different slave nodes positioned at the edges between three adjacent slave nodes. With adjacent slave nodes is meant that those slave nodes pair-by-pair can be considered adjacent or neighbouring. FIG. 8 provides an illustration. In this embodiment the antenna arrangement within the same antenna board is kept square shaped to allow for H-shape signal routing. All antenna boards have the same arrangement. The antenna elements on each antenna board are thus positioned to form together a same matrix pattern as on the other antenna boards. Note that at the outside dummy antennas (76) may be provided. These are used to ensure the edge patch antennas have similar surroundings (i.e. a similar electromagnetic environment) as the centre antennas.

[0069] In the scheme of FIG. 8 antenna element ‘1’ in 72 can be used as reference to calibrate antennas ‘1’ and ‘2’ in tile 71. Antenna ‘5’ in tile 73 can be reference for antennas ‘4’ and ‘12’ in tile 71. Similarly, element ‘9’ in 73 can be reference for antennas ‘8’ and ‘16’ in 71. In this way odd and even rows can be calibrated. Moreover, adjacent rows can be calibrated in this configuration by using antenna ‘3’ in 71 or ‘9’ 73 as a reference for the antenna pair ‘4/7’ in 71. To calibrate mismatches between different tiles, antenna ‘4’ in 72, antenna ‘4’ in 71 and antenna ‘1’ in node 73 form an equilateral triangle which can be used in the calibration procedure as well. In other words one can also state that antenna ‘4’ in 72, antenna ‘4’ in 71 and antenna ‘1’ in node 73 together with antenna ‘1’ of tile 74 form a parallelogram (and different from a rectangle). Calibration of antennas ‘4’ and ‘8’ in tile 71 can be done by linking the relative phase and gain information among calibrated pairs of ‘4/7’ and ‘7/8’ in tile 71, where antenna element ‘7’ in tile 71 is used as an intermediate node help to propagate. The proposed configuration reduces the local signal routing complexity in certain embodiments of the invention, like e.g. in the embodiment shown in FIG. 8, while keeping full self-calibration coverage. FIG. 9 shows the symmetric chip to antenna signal routing where each signal path is of the same length. Thanks to the square antenna matrix layout as in FIG. 8, it is much easier to equalize the distance than a non-square shape floorplan of the patch antennas.

[0070] In another embodiment tiles are used that form an odd number squared array, like for example the 3×3 array of FIG. 10. As in the previously discussed embodiments an equilateral triangle, in FIG. 10 formed by antenna ‘3’ in tile 92, antenna ‘1’ in 93 and antenna ‘3’ in tile 91, at the boundary corner is preserved. Antenna path towards/from antennas ‘4’ and ‘5’ from tile 91 can be calibrated via antenna ‘1’ in tile 92. Considering the antennae ‘5’ and ‘1’ in tile 91, they can be calibrated by using antenna ‘2’ in the same tile as a reference. The antenna ‘4’ calibration can propagate back to antenna ‘1’ in tile 91 by using antenna ‘5’ as an intermediate node as the relative gain/phase between ‘5’ and 1′ is known.

[0071] Yet another embodiment is illustrated in FIG. 11. The antenna layout here has in each tile a rectangular shape, which does not contain N.sup.2 antennas. Here, to propagate vertically by linking antennas ‘7’ and ‘4’ in 1001, only antenna element ‘3’ in 1001 can be used for reference, as there is no reference node in tile 1003 that can serve as a possible reference.

[0072] FIG. 12 shows the phased array module and a chip configuration when the phased array module is calibrated for antenna paths of several transmitter slave nodes. Assume that e.g. a low frequency IQ sinusoidal signal is generated from the on-chip tone generator and DAC in the integrated circuit (1104) of the master node. The tone is upconverted with the LO block in the master chip and is fed to slave chips via their I/O port. The signal is further amplified in the slave nodes and fed to open space via an antenna in the slave nodes. A selected chip (1105) is configured as reference receiver to process the spill-over leakage signal, i.e. the signal portions that leak back from the various transmitter slave antennas (1101, 1102, 1103) when they transmit their signal (see FIG. 11). In the reference receiver the LO block runs at the same frequency of the master chip. Thus, after downconversion and A/D conversion, the phase and gain information is measured by the ADC. To keep an identical environment for the antenna path under calibration such that the spill over path is matched, any other front end circuit is disabled. It is noted that when a chip operates as reference transceiver, its reference clock is connected to master chip (1112) to keep the coherence.

[0073] FIG. 13 illustrates the scenario when the antenna paths under calibration and the reference path are located at the same slave node where the master chip is redundant. A tone signal is generated, upconverted and split to frontend/antennas 1201 and 1203. Assuming antenna 1202 is the reference antenna, the received signal is fed to the mixer and downconverted with the common LO shared with the transmitter. Then the phase/amplitude information is obtained via the ADC. In other words, all processing may in this case be performed in the slave node.

[0074] A similar configuration can be implemented for slave receiver calibration. The reference antenna then is a transmitter antenna via which a test signal for calibration is transmitted that is generated using the tone generator and DAC shown in FIG. 13. Antennas 1201 and 1203 now are receive antennas which each receive said test signal. The combined signal is then fed to the mixer and so on. Such scenario corresponds to the case mentioned in FIG. 8 when ‘7’ and ‘4’ in tile 71 uses ‘3’ as a reference.

[0075] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. The invention is not limited to the disclosed embodiments.

[0076] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.