RADIO FREQUENCY POWER AMPLIFIER

Abstract

According to one aspect, an integrated circuit includes a power amplifier having a succession of at least two amplifier stages. The two amplifier stages include a first amplifier stage configured to receive a radio frequency signal as input and a last amplifier stage configured to deliver as an output of an amplified radio frequency signal. The power amplifier further includes a safety circuit with a control circuit configured to compare the amplified radio frequency signal voltage with a threshold voltage. The safety circuit further comprises a gain reduction circuit configured to reduce a bias voltage of an upstream amplifier stage of the last amplifier stage when the amplified radio frequency signal voltage is greater than the threshold voltage.

Claims

1-8. (canceled)

9. An integrated circuit, comprising: a power amplifier, comprising: a first amplifier stage configured to receive an input radio frequency signal; a last amplifier stage configured to deliver an amplified radio frequency signal, the first amplifier stage and the last amplifier stage arranged in succession to each other, and a safety circuit, comprising: a control circuit configured to compare a voltage of the amplified radio frequency signal with a threshold voltage, and a gain reduction circuit configured to reduce a gain of an upstream amplifier stage to the last amplifier stage in response to the voltage of the amplified radio frequency signal being greater than the threshold voltage.

10. The integrated circuit of claim 9, wherein the control circuit includes a threshold voltage generator circuit configured to generate the threshold voltage.

11. The integrated circuit of claim 10, wherein the threshold voltage generator circuit includes a variable current source and a variable resistor, the threshold voltage being adjustable based on a variation of the variable current source, the variable resistor, or a combination thereof.

12. The integrated circuit of claim 10, wherein the control circuit comprises: a rectifier configured to generate a rectified voltage of the amplified radio frequency signal; a comparator circuit configured to: compare the rectified voltage of the amplified radio frequency signal with the threshold voltage, and generate an output signal in response to the rectified voltage of the amplified radio frequency signal being greater than the threshold voltage; and a filter circuit configured to remove radio frequencies of the output signal.

13. The integrated circuit of claim 12, wherein the gain reduction circuit comprises an amplification circuit configured to: generate an amplified output signal at an output of the filter circuit; and transfer to an input of the upstream amplifier stage to reduce a gate voltage of an input transistor of the upstream amplifier stage.

14. The integrated circuit of claim 9, wherein the gain reduction circuit is configured to reduce the gain of the upstream amplifier stage by decreasing a bias voltage of the upstream amplifier stage.

15. The integrated circuit of claim 9, wherein the first amplifier stage is a driver stage amplifier and the last amplifier stage is a power stage amplifier, the gain reduction circuit configured to reduce the gain of the driver stage amplifier in response to the voltage of the amplified radio frequency signal is greater than the threshold voltage.

16. A device, comprising: an antenna; and an integrated circuit, comprising: a power amplifier coupled to the antenna and configured to deliver an amplified radio frequency signal to the antenna from an input radio frequency signal received at an input of the power amplifier, the power amplifier comprising: a first amplifier stage configured to receive the input radio frequency signal; a last amplifier stage configured to deliver the amplified radio frequency signal to the antenna, the first amplifier stage and the last amplifier stage arranged in succession to each other; and a safety circuit, comprising: a control circuit configured to compare a voltage of the amplified radio frequency signal with a threshold voltage, and a gain reduction circuit configured to reduce a gain of an upstream amplifier stage to the last amplifier stage in response to the voltage of the amplified radio frequency signal being greater than the threshold voltage.

17. The device of claim 16, wherein the control circuit includes a threshold voltage generator circuit configured to generate the threshold voltage.

18. The device of claim 17, wherein the threshold voltage generator circuit includes a variable current source and a variable resistor, the threshold voltage being adjustable based on a variation of the variable current source, the variable resistor, or a combination thereof.

19. The device of claim 17, wherein the control circuit comprises: a rectifier configured to generate a rectified voltage of the amplified radio frequency signal; a comparator circuit configured to: compare the rectified voltage of the amplified radio frequency signal with the threshold voltage, and generate an output signal in response to the rectified voltage of the amplified radio frequency signal being greater than the threshold voltage; and a filter circuit configured to remove radio frequencies of the output signal.

20. The device of claim 19, wherein the gain reduction circuit comprises an amplification circuit configured to: generate an amplified output signal at an output of the filter circuit; and transfer to an input of the upstream amplifier stage to reduce a gate voltage of an input transistor of the upstream amplifier stage.

21. The device of claim 16, wherein the gain reduction circuit is configured to reduce the gain of the upstream amplifier stage by decreasing a bias voltage of the upstream amplifier stage.

22. The device of claim 16, wherein the first amplifier stage is a driver stage amplifier and the last amplifier stage is a power stage amplifier, the gain reduction circuit configured to reduce the gain of the driver stage amplifier in response to the voltage of the amplified radio frequency signal is greater than the threshold voltage.

23. A power amplifier, comprising: a first amplifier stage configured to receive an input radio frequency signal; a last amplifier stage configured to deliver an amplified radio frequency signal, the first amplifier stage and the last amplifier stage arranged in succession to each other; and a safety circuit, comprising: a control circuit configured to compare a voltage of the amplified radio frequency signal with a threshold voltage, and a gain reduction circuit configured to reduce a gain of an upstream amplifier stage to the last amplifier stage in response to the voltage of the amplified radio frequency signal being greater than the threshold voltage.

24. The power amplifier of claim 23, wherein the control circuit includes a threshold voltage generator circuit configured to generate the threshold voltage.

25. The power amplifier of claim 24, wherein the threshold voltage generator circuit includes a variable current source and a variable resistor, the threshold voltage being adjustable based on a variation of the variable current source, the variable resistor, or a combination thereof.

26. The power amplifier of claim 24, wherein the control circuit comprises: a rectifier configured to generate a rectified voltage of the amplified radio frequency signal; a comparator circuit configured to: compare the rectified voltage of the amplified radio frequency signal with the threshold voltage, and generate an output signal in response to the rectified voltage of the amplified radio frequency signal being greater than the threshold voltage; and a filter circuit configured to remove radio frequencies of the output signal.

27. The power amplifier of claim 26, wherein the gain reduction circuit comprises an amplification circuit configured to: generate an amplified output signal at an output of the filter circuit; and transfer to an input of the upstream amplifier stage to reduce a gate voltage of an input transistor of the upstream amplifier stage.

28. The power amplifier of claim 23, wherein the gain reduction circuit is configured to reduce the gain of the upstream amplifier stage by decreasing a bias voltage of the upstream amplifier stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Other advantages and features of the invention will appear on examination of the detailed description of embodiments and implementations, which are in no way limiting, and of the appended drawings in which:

[0049] FIG. 1 is a block diagram of an embodiment integrated circuit; and

[0050] FIG. 2 is a block diagram of an embodiment integrated circuit.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0051] FIG. 1 illustrates an integrated circuit according to an embodiment of the invention.

[0052] The integrated circuit comprises a power amplifier AMP. The power amplifier AMP is configured to amplify a radio frequency RF signal received at the input DSIN and deliver the amplified radio frequency signal at the output PSOUT. This amplified radio frequency signal can be delivered to a radio antenna (not represented).

[0053] Such a power amplifier AMP can in particular be integrated into an object comprising a radio antenna, in particular so as to be able to be used within the framework of the Internet of Things.

[0054] In the represented embodiment, the power amplifier AMP includes two amplifier stages DS, PS. A first amplifier stage is a driver stage DS. The second amplifier is a power stage PS.

[0055] The first amplifier stage, the driver stage DS, is placed upstream of the second amplifier stage, the power stage PS.

[0056] In particular, the driver stage DS is configured to receive as input DSIN the radio frequency signal RF, and the power stage PS is configured to deliver the amplified radio frequency signal RFAMP.

[0057] The driver stage DS and the power stage PS each comprise two cascaded transistors to amplify the signal that they receive as input.

[0058] The driver stage DS is configured to receive a bias voltage on the gate of an input transistor of this driver stage.

[0059] In nominal operation, the bias voltage is defined by a direct voltage source VGDS0 and by a resistor R1. The resistance R1 can be in the range of 1 kΩ.

[0060] The power amplifier AMP also comprises a safety circuit SFTC. The safety circuit SFTC comprises control circuit CM and gain reduction circuit GRM.

[0061] These circuit CM, GRM are configured to regulate the gain of the power amplifier AMP depending on the voltage of the amplified radio frequency signal RFAMP at the output PSOUT of the power stage PS.

[0062] In particular, the control circuit (CM) is configured to detect an overvoltage of the amplified radio frequency signal RFAMP.

[0063] The control circuit CM comprise a rectifier RDS configured to receive the amplified radio frequency signal RFAMP and to deliver a direct signal from this amplified radio frequency signal RFAMP.

[0064] The control circuit CM also comprise a threshold voltage generator GVTH. The threshold voltage generator GVTH is configured to be able to generate a threshold voltage VTH.

[0065] In particular, the threshold voltage generator GVTH comprises a current source SCG and a resistor R0 in series. In particular, the resistor R0 has a first terminal which is connected to the current source and a second terminal which is connected to ground GND. As represented in FIG. 2, the gate of the second transistor T0 is connected to the current source SCG and to the first terminal of the resistor R0 so as to receive the threshold voltage VTH.

[0066] In particular, the current source is configured to deliver a current equal to Vbg/Rbg, where Vbg and Rbg are voltage and resistance parameters of the current source. Thus, the threshold voltage VTH which can be received by the gate of the second transistor is equal to Vbg/Rbg*R0.

[0067] Preferably, the threshold voltage VTH can be adjusted using a digital-to-analogue converter DAC allowing setting the current delivered by the current source SCG and/or the value of the resistance R0.

[0068] In the embodiment shown in FIG. 1, the digital-to-analogue converter DAC allows setting the current delivered by the current source SCG.

[0069] In particular, the threshold voltage is selected to be less than a voltage at the output PSOUT of the power stage PS which can damage the latter. For example, the threshold voltage can be in the volt range.

[0070] Furthermore, the control circuit CM also comprise a comparator COMP configured to compare the direct signal derived from the amplified radio frequency signal with the threshold voltage VTH.

[0071] As represented in FIG. 2, the comparator can be made from two transistors T1, T0, in particular NMOS transistors. The transistors T1, T0 each have a source which is connected to the source of the other transistor.

[0072] A first transistor T1 has a gate configured to receive the amplified radio frequency signal RFAMP.

[0073] More particularly, a capacitive divider DCP can be provided upstream of the gate of the first transistor T1 in order to reduce the voltage of the amplified radio frequency signal RFAMP in order to adapt it to the first transistor T1. This capacitive divider DCP comprises two capacitors Ct, Cb in series.

[0074] A first capacitor Ct has a first terminal connected to the output of the power stage DS, in particular to a drain of an output transistor of the power stage. Thus, this first capacitor Ct is configured to receive a voltage VDRAIN from the output of the power stage.

[0075] The first capacitor Ct also has a second terminal connected to a first terminal of a second capacitor Cb of the capacitive divider DCP.

[0076] The second capacitor Cb has a second terminal connected to a ground GND.

[0077] The gate of the first transistor T1 is connected to the second terminal of the capacitor Ct and to the first terminal of the capacitor Cb.

[0078] Furthermore, a resistor Rb has a first terminal connected to the gate of the first transistor, to the second terminal of the capacitor Ct and to the first terminal of the capacitor Cb.

[0079] Moreover, the second transistor T0 of the comparator has a gate configured to receive the threshold voltage VTH.

[0080] Moreover, the source of the first transistor T1 and the source of the second transistor T0 are connected to a current source SC0 and to a capacitor CP0 which are mounted in parallel.

[0081] The current source SC0 can for example deliver a current in the range of 10 μA.

[0082] The capacitor CP0 can have a capacitance in the range of a few picofarads.

[0083] Moreover, the second transistor T0 has a drain connected to a voltage source VDD and the first transistor T1 has a drain forming an output of the comparator.

[0084] Thus, when the divided voltage of the amplified radio frequency signal RFAMP received by the gate of the first transistor is greater than the threshold voltage VTH, a current I1 passes through the first transistor T1.

[0085] This current I1 therefore allows indicating that the voltage of the radio frequency signal RFAMP is too high.

[0086] In order to eliminate certain frequencies from the current I1, the control circuit CM comprise a filter FT, represented in FIG. 1. The filter FT is thus connected to the output of the comparator COMP. This filter FT can be made using a capacitor CFT having a first terminal connected to the drain of the first transistor T1 of the comparator COMP, and a second terminal connected to the ground GND.

[0087] Furthermore, the gain reduction circuit GRM comprise circuit AM for amplifying the current I1 delivered by the filter.

[0088] These amplification circuit AM comprise two current mirrors CM1, CM2. A first current mirror CM1 comprises two PMOS transistors T2 and T3.

[0089] In particular, the transistor T2 has a drain connected to the filter output FT, that is to say to the first terminal of the capacitor CFT. The transistor T2 also has a gate connected to a gate of the transistor T3 and to the drain of the transistor T2. The transistor T2 and the transistor T3 each have a source connected to the voltage source VDD.

[0090] A second current mirror CM2 comprises two NMOS transistors T4 and T5.

[0091] In particular, the transistor T4 has a drain connected to a drain of the transistor T3 and a source connected to the ground GND. The transistor T4 has a gate connected to a gate of the transistor T5 and to the drain of the transistor T4.

[0092] The transistor T5 has a drain connected to the gate of the input transistor of the driver stage and a source connected to the ground.

[0093] Thus, the drain of the transistor T5 is connected to the first terminal of the resistor R1.

[0094] The two current mirrors CM1, CM2 allow multiplying the current at the output of the filter by the ratios between the transistors T2, T3 and between the transistors T4 and T5.

[0095] These two current mirrors CM1, CM2 thus allow generating a current IVGDS at the drain of the transistor T5. This current IVGDS allows reducing the bias voltage of the gate of the input transistor of the driver stage. This current IVGDS will be proportional to the current I1 exiting the filter and at a ratio k equal to a product of the ratios between the transistors T2, T3 and between the transistors T4 and T5.

[0096] The current IVGDS through the resistor R1 provides a voltage drop equal to (−k*I1*R1).

[0097] Thus, the gate voltage of the driver stage equal to (VGDS0−k*I1*R1) is reduced.

[0098] This allows reducing the gain of this driver stage. The reduction of the gain of the driver stage allows reducing the voltage swing of the amplified radio frequency signal. Thus, when the voltage of the amplified radio frequency signal is sufficiently reduced, the voltage of the amplified radio frequency signal at the comparator, that is to say at the gate of the first transistor T1, becomes lower than the threshold voltage VTH. Therefore, the current I1 is no longer generated such that the bias current is that defined by the voltage source VGDS0 and by the resistor R1.

[0099] The safety circuit thus allows limiting the voltage of the amplified radio frequency signal below a voltage which could damage the power stage.

[0100] Moreover, a current mirror CM3 comprising the transistor T2 and a transistor T6 is provided to create an opposite current IVGDS_N relative to the current IVGDS.

[0101] The transistor T6 is a PMOS transistor. This transistor T6 has a gate connected to the gate of the transistor T2, a drain connected to the second terminal of the resistor R1 and to the voltage source which is connected to the voltage source VGDS0. The transistor T6 also has a source connected to the voltage source VDD.

[0102] The opposite current IVGDS_N is therefore generated at the drain of the transistor and delivered at the output of the voltage source VGDS0. In this manner, the current VGDS0 will always be close to 0 mA without any disturbance of the voltage source VGDS0.

[0103] As previously seen, the safety circuit SFTC allows protecting the last amplifier stage.

[0104] Furthermore, the safety circuit SFTC does not interfere with the performance of the power amplifier. Indeed, the gain reduction circuit do not intervene during a nominal operation of the antenna.

[0105] Furthermore, reducing the gain, not of the last amplifier stage, but of a stage upstream of the last amplifier stage, allows obtaining a rapid amplified signal voltage reduction.

[0106] The safety circuit allows the use of simple and inexpensive amplifier stages.

[0107] Furthermore, this safety circuit is also inexpensive to manufacture.