Hardened White Box Implementation

Abstract

A processor device has an executable implementation of a cryptographic algorithm implemented thereon that is white-box-masked by a function f The implementation comprises an implemented computation step S by which input values x are mapped to output values s=S[x], and which is masked to a white-box-masked computation step T by means of an invertible function f. As a mapping f there is provided a combination (f=(c1, c2, . . . )*A) of an affine mapping A having an entry width BA and a number of one or several invertible mappings c1, c2, . . . having an entry width Bc1, Bc2, . . . respectively, wherein BA=Bc1+Bc2+ . . . . Output values w are generated altogether by the mapping f. The affine mapping A is constructed by a construction method coordinated with the invertible mappings c1, c2, and etc.

Claims

1-15. (canceled)

16. A processor device having an executable white-box-masked implementation of a cryptographic algorithm implemented thereon, which is configured to generate an output text from an input text while employing a secret key K, wherein the implementation comprises an implemented computation step S by which input values x are mapped to output values s=S[x], and which is masked to a white-box-masked computation step T by means of an invertible function f, by which output values w of f are formed, wherein a) as a mapping f, a combination (f=(c1, c2, . . . )*A) is provided of an affine mapping A having an entry width BA and a number of one or several invertible mappings c1, c2, . . . having an entry width Bc1, Bc2, . . . respectively, wherein BA=Bc1+Bc2+ . . . , wherein through the mapping f output values w are generated; b) the affine mapping A is configured to be applied to output values s of the computation step S and additionally to one or several obfuscation values y which are statistically independent of the output values s of the computation step S, according to a=A(S[x], y)=A(s, y); c) the one or several invertible mappings c1, c2, . . . are configured to map output values a of the affine mapping A to output values w of the mapping f, according to w=(c1, c2, . . . )(A (s,y)); d) the affine mapping A is constructed by a construction method coordinated with the invertible mappings c1, c2, . . . , wherein: d1) the output values a of the affine mapping A are represented as a concatenation of output-value parts a=a1|a2 . . . and the output values w of the mapping f are represented as a concatenation of output-value parts w=w1|w2 . . . , wherein output-value parts a1, a2, . . . and w1, w2, . . . respectively have the same entry width Bc1, Bc2, . . . as the invertible mappings c1, c2, . . . ; d2) an input value x=xi is set; and d3) the affine mapping A is selected or formed such thatfor fixed input value xiby applying A on s=S [xi] with all possible obfuscation values y, all possible output-value parts a1 or/and all possible output-value parts a2, . . . of the affine mapping A are generated, namely for at least one individual output-value part a1, a2, . . . or for each individual output-value part a1, a2, . . . .

17. The processor device according to claim 16, wherein the number of obfuscation values y is stipulated equal to the entry width Bc1=Bc2= . . . of the invertible mappings c1, c2, . . . and comprises feature d3), that the affine mapping A is split up into partial mappings P1, Q1, P2, Q2, . . . so that it holds: a1(x,y)=P1(x)+Q1(y), a2(x,y)=P2(x)+Q2(y) . . . , wherein at least one or all of the partial mappings Q1, Q2, . . . are invertible mappings.

18. The processor device according to claim 17, wherein the affine mapping A comprises a linear mapping which is formed by a matrix MA, which is organized in columns and rows, wherein: the output values s of the computation step S are associated with a number n of columns N in the matrix MA and the statistically independent obfuscation values y are associated with a number m of columns Mseparated from columns Nin the matrix MA, wherein the number m columns M for the obfuscation values y is equal to the number m of the obfuscation values y; the matrix MA comprises an invertible partial matrix which is formed: by those m columns M of the matrix MA which are associated with the obfuscation values y, and the same number m of mutually adjacent rows of the matrix MA; in particular by the last m columns M of the matrix MA in combination with either the first, second, . . . or last m rows of the matrix MA.

19. The processor device according to claim 18, wherein the number of obfuscation values y is four or an integral multiple of four, in particular eight, and the invertible partial matrix is formed by the last four columns of the matrix MA and in addition the first, or the second, or the third . . . or last four rows of the matrix MA, or according to the integral multiple, several such groups of four columns and four rows.

20. The processor device according to claim 16, wherein for carrying out the implementation of the white-box-masked computation step T there has been supplied a look-up table STab[x] representing the computation step S, or a look-up table STab[x,y] representing the computation step S and the obfuscation values y.

21. The processor device according to claim 16, wherein the white-box-masked computation step T is represented by a white-box-masked look-up table TTab [x, y] in which values f(s, y) are recorded, in particular the result of the application of one or several invertible mappings c1, c2, . . . to A(s, y).

22. The processor device according to claim 16, wherein the implementation additionally comprises a further invertible function g to be applied to input values x of the computation step S, or to input values x of the computation step S and to obfuscation values y according to g.sup.1(x) or g.sup.1(x, y).

23. The processor device according to claim 16, wherein there is provided as an algorithm a block cipher having several rounds, in particular DES or AES, and as a computation step S: one or several SBox operations or one or several inverse SBox operations, respectively of one round; or a combination of one or several SBox operations or one or several inverse SBox operations, respectively of one round, with one or several further operations of the round.

24. The processor device according to claim 23 with algorithm DES, wherein as an input value x, there is/are provided either one or several expanded right entry bits ri (r1|r2| . . . ) of a round, or a linkage (x=r1 XOR k1|r2 XOR k2| . . . ) of one or several expanded right entry bits ri of a round with one or several key bits ki; or/and one or several left entry bits li of the round go into the obfuscation values y.

25. The processor device according to claim 23 having algorithm DES, wherein the obfuscation values y are computed by means of a function V from one or several left entry bits li of the round or/and from one or several expanded right entry bits ri of the round, wherein in particular V is electively a linear mapping or a hash function.

26. The processor device according to claim 25, wherein the algorithm has several rounds and the function V is newly chosen for every round.

27. The processor device according to claim 23 having algorithm DES, wherein the further operations comprise one or several of the following: permutation P; expansion E; addition of left and right entry bits l, r or left and expanded right entry bits l, r.

28. The processor device according to claim 23 having algorithm AES, wherein there is provided as an input value x an input value or part of an input value of an AddRoundKey operation or a SubBytes operation or an inverse SubBytes operation of an AES round; or/and the further operations comprise one or several of the following: MixColumn operation or one or several substeps of the MixColumn operation or inverse MixColumn operation or one or several substeps of the inverse MixColumn operation.

29. The processor device according to claim 16, wherein the obfuscation values y are computed respectively by means of a function V from bits of the input text, wherein in particular V is electively a linear mapping or a hash function.

30. The processor device according to claim 29, wherein the algorithm has several rounds and the function V is newly chosen for every round.

31. The processor device according to claim 16, wherein the computation step S has been implemented on the processor device as a white-box-masked computation step T in that: (i) the computation step S has been carried out to generate output values s, and (ii) the invertible function f has been applied to the generated output values s of the computation step S and the obfuscation values y, and a thereby achieved result T has been implemented on the processor device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Hereinafter the invention will be explained more closely on the basis of exemplary embodiments and with reference to the drawings, in which are shown:

[0052] FIG. 1 a DES round in standard representation, according to the prior art, suitably as the basis of the invention;

[0053] FIG. 2 a DES round in an alternative representation, having S-box operations S embedded in operations T, and specifically suitably as the basis of the invention;

[0054] FIG. 3 a detail representation of an individual operation T in the DES round of FIG. 2;

[0055] FIG. 4 a first part of a white-box masking of a DES round according to FIG. 1, or according to FIG. 2 and FIG. 3, carried out by applying an affine mapping A, according to embodiments of the invention.

[0056] FIG. 5 a function f split up into an affine mapping A and two invertible mappings c1 and c2 for white-box masking a DES round according to FIG. 1, or according to FIG. 2 and FIG. 3, to S-box-output values s (x1), s (x2), s (x3), . . . achieved for different input values x1, x2, x3, according to embodiments of the invention.

DETAILED DESCRIPTION OF EMBODIMENT EXAMPLES

[0057] FIG. 1 shows a DES round according to the prior art. By means of FIG. 1 it is indicated that a computation step S, as is the basis of the invention, can be for example a S-box operation or the totality of the eight S-boxes of a DES round. At the entry of a DES round, 64 bit entry data are divided into 32 bit left side L=lj, j=0, . . . , 31 and 32 bit right side R=rj, j=0, . . . , 31. The bits of the right side R are expanded by means of an expansion operation to 48 bit expanded entry data E=fj, j=0, . . . , 47 of the right side. The 48 bit expanded entry data E having 48 bit key data K=kj, j=0, . . . 47 are linked by means of an XOR operation to input values xj=rj XOR kj, j=0, . . . , 47 for eight S-boxes S. Each of the eight S-boxes S=S1, . . . S8 processes six bits input values xj to respectively four bits output values sj. The four-bit-wide output values sj of the eight S-boxes S=S1, . . . S8 are fed to a permutation operation P. The output values of the permutation P are XORed with bits of the left side and fed to the next DES round. For standard DES, the DES round ends here.

[0058] According to the invention, and as represented in FIG. 4, a first part of a white-box masking is applied to the DES S-box Si (dashed encircled region in FIG. 1) by applying an affine mapping A which comprises a linear mapping MA or in a special case is also formed by a linear mapping MA. For the first part of the white-box masking, the output values sj of the S-boxes are fed to a matrix MA by which the linear mapping is represented in the affine mapping A according to a=A(S[x])=MA(S[x]). Further, in addition to the output values sj of the S-boxes, statistically independent values y are fed to the matrix MA, for example two or more bits lj, j=0, . . . , 31 of the left side 64 bit entry data at the entry of the DES round. To attain, according to an especially advantageous embodiment of the invention, the special hardening of the white-box masking already in this first masking step, the matrix MA is so configured that in addition to the S-Box output values sj, incoming values y are statistically independent of the S-Box output values sj, and that each bit in the output values w of the matrix MA depends on at least one bit from the obfuscation values y. Alternatively other embodiments of the matrix MA are possible.

[0059] Hereinafter there is set forth by means of FIG. 2 and FIG. 3 an alternative particularly suitable representation of a DES round for implementing the invention, in which the operations specific to a DES round S-box operation S and permutation P are summarized in a combined operation T. In so doing, the first part of the white-box masking will be applied with the mapping A, or concretely with the matrix MA, to the combined operation T, in which the S-Box operation is contained (see FIG. 4).

[0060] FIG. 2 shows a DES round in an alternative representation, specifically suitably for the application of a white-box masking according to the invention. At the entry of the DES round, first as in FIG. 1, 64 bit entry data are divided into 32 bit left side L=lj, j=0, . . . , 31 and 32 bit right side R=rj, j=0, . . . 31, and the bits of the right side are expanded to 48 bit E(Rj). For the alternative representation of FIG. 2, two or more bits of the 32 bit L=lj, j=0, . . . , 31 of the left side of the round entry data are employed as obfuscation width y. In this way, upon executing the DES round, the DES-specific eight S-box operations are executed by the fact that a multiplicity of eight or ten combined operations T=T0, . . . T7 or T0, . . . T9 is carried out, in which the S-Box operations S=S1, . . . S8 are comprised.

[0061] FIG. 3 shows the detailed structure of an individual combined operation T=Ti, i=0, . . . 7 (or 0, . . . 9 where applicable) of FIG. 2. (Optionally additionally present padding with zero bits and shifts are omitted in FIG. 3 in favor of better clarity.) In the combined operations T=Ti of FIG. 2 and FIG. 3, as opposed to the S-boxes S of the DES representation of FIG. 1, the key kj and the DES-typical permutation P are already taken into account in the operation T. The S-box with the key kj taken into account is represented in FIG. 3 by the operation box Si (XORkij), the permutation by P. Further, before the computation step S, thus before the S-box operations S1, . . . , S8, eight (or ten) overall tables T0, . . . T7 (or T0, . . . T9) are generated, in which respectively six-bit entry values xj=rj, j=0, . . . 47 (now not XORed with k, because the key bits kj are already contained in S) for the eight S-boxes S and two bit obfuscation values lj, j=0, . . . , 31 are contained and for ten overall tables Ti further bits obfuscation values lj, j=0, . . . , 31 are contained. Here, the two or more, for example four, bit obfuscation values lj are not processed by the S-boxes. The respectively six bit entry values xj=rj XOR kj are respectively processed by an S-box. Therefore the overall tables Ti deliver output values which contain exit values sj of the S-boxes as well as obfuscation values lj.

[0062] As represented in FIG. 4, the first part of the white-box masking of the implementation is carried out by feeding the output values of the combined operations (overall tables) Ti to the matrix MA according to the invention by which the affine mapping A according to the invention is represented. Here, the exit values S(x) of the computation step S, bits of the entry value x, i.e. bits rj of the right side, as well as the statistically independent values y, i.e. the bits employed as obfuscation values lj of the left side of the DES round entry value, are fed to the matrix MA. A separate fetching of the statistically independent values y=lj is not required here, because they are already contained in the combined operation T. For this reason the DES representation of FIG. 2 is particularly well suitable for implementing the invention. The result of the masking are partially white-box-masked operations. These partially white-box masked operations are subsequently still masked with invertible mappings c1, c2, . . . to (completely) white-box masked operations Ti, i=0, . . . 9 or i=0, . . . 7 (cf. FIG. 5) and thereupon implemented in the processor device.

[0063] In the embodiment of FIG. 4, the affine mapping A contained in the mapping f employed in the white-box masking is configured as a matrix MA, having coefficients aij, i=0, . . . l1, j=0, . . . n+m1.

[0064] The matrix MA is multiplied by the entry vector (s,y), containing S-box exit values s=S[x] (x are e.g. bits r of the right side), and obfuscation values y (e.g. bits of the left side) to generate an exit vector a. The sum formula in FIG. 4 illustrates this aspect for an individual row i having the coefficients aij (j=0, . . . n+m1) of the matrix MA, and a thereby generated individual record i of the exit vector a. In the entry vector (s,y), the S-box exit values s are contained in the upper n records and the obfuscation values y in the lower m records. In the matrix MA are correspondingly contained on the left the n coefficients aij, j=0, . . . n1 of MA to be multiplied with the S-box exit values s=s0, . . . sn1. On the right in the matrix MA are contained the m coefficients aij, j=n, . . . n+m1 of MA to be multiplied with the obfuscation values y=y0, . . . ym-1.

[0065] The matrix MA is constructed according to the invention such that an invertible partial matrix is formed by the last m columns of the matrix MA, i.e. the m coefficients aij, j=n, . . . n+m1 of MA to be multiplied by the obfuscation values y=y0, . . . ym-1, and the first (or second or third . . . or last) m rows of the matrix MA.

[0066] As a result of this in particular the effect is achieved that the right sum of the sum equation for i (i designates individual bits)

.sub.j=0.sup.m-1a.sub.i,n+jy.sub.j

disappears for no row index i, i=0, . . . l1. This effect is attained by the fact that in every row i, at least one of the coefficients ai, n+j, j=0, . . . m1, which are to be multiplied with the obfuscation values y=yj, j=0, . . . m1, is non-zero. Through the effect it is ensured that in no row i, i=0, . . . l1 the obfuscation values y in the output vector a disappear, thus in every row i in the record i of the output vector a at least one obfuscation value yj is contained. This in turn has the further-reaching effect that the output values a of the affine mapping A are statistically balanced.

[0067] FIG. 5 shows a function f for white-box masking a DES round according to FIG. 1, or according to FIG. 2 and FIG. 3, according to embodiments of the invention. The function f is split up into an eight-bit wide affine mapping A and two respectively four bit wide invertible mappings c1 and c2. The function f is applied to four bit wide S-box output values s(x) and four bit wide obfuscation values y. In the image of FIG. 4, the width of the S-box exit values thus is n=4 and the width of the obfuscation values m=4: According to FIG. 5, different input values x=x1, x2, x3, . . . respectively are successively stipulated and the masking f=c(A(s(x),y)) carried out with every input value x=x1, x2, x3, . . . .

[0068] First, an input value x to be processed by S-boxes of the DES round is set. FIG. 5 shows three such set input values x, namely x1, x2 and x3, for three executions of a DES round masking. A DES S-box operation is applied to the input value x so that four bit s(x) are generated, i.e. four bit s(x1) or s(x2) or s(x3) etc.

[0069] In addition, four bit statistically independent obfuscation values y are supplied.

[0070] For the respective x=x1, x2, x3, . . . thus altogether eight bit data are supplied, namely four bit S-box-output values s(x) and four bit obfuscation values y as an input values for the affine mapping A (e.g. matrix MA).

[0071] The affine mapping A is applied to the four bit output values s(x) of the computation step S and the four bit statistically independent obfuscation values y, according to a=A(S[x], y)=A(s, y).

[0072] Through the two invertible mappings c1, c2, output values a of the affine mapping A are mapped to output values w of the mapping f, according to (w1, w2)=(c1, c2)((a1, a2) (s(x),y))=(c1, c2)(A (S[x],y)).

[0073] The output values a of the affine mapping A are in this connection represented as a concatenation of each four bit wide output-value parts a=a1|a2. In this connection it should be noted that output-value parts are designated with ai which are one or several bit wide, wherein individual bits are designated with i. The output values w of the mapping f are represented as a concatenation of output-value parts w=w1|w2. The output-value parts a1, a2, and w1, w2, respectively have the same entry width Bc1, Bc2 as the invertible mappings c1, c2. In the embodiment example of FIG. 5, a1, a2, w1, w2, c1 and c2 respectively are four bit wide.

[0074] According to the invention, there is attained by the construction of the affine mapping A with invertible partial matrices for the obfuscation values y that if one varies the obfuscation values y for fixed x, for all possible x the same set M of partial-output values ai of A always arises. Without this special construction different sets Mj would generally arise for different xj. In this connection the inventors designate the sets Mj also as paths. The special construction of A thus ensures that there is only one single path for ai. It is thereby ensured that the invertible functions ci are path-preserving. Otherwise a harmful scrambling of the sets Mj can arise from the invertible mapping ci. The special construction of A thus also ensures that the mappings ci can be selected arbitrarily from the total amount of the invertible mappings and the statistical balance of the total function f is retained.

[0075] When the processor device is put into operation and thereby the cryptographic algorithm is executed, e.g. within a software application, then the white-box-masked operations Ti are executed. By executing the white-box-masked operations Ti, in particular the DES-specific S-box operations are executed in hardened white-box-masked form. Because neither the S-boxes S nor the combined S-boxes T are implemented in the processor device in direct form, but merely the S-box operations white-box-masked to T according to the invention, attacks on the processor device are prevented or at least considerably impeded.

Glossary

[0076] S: computation step, in particular DES SBOX or eight DES S-boxes, in particular for standard representation of DES
T: operation comprising computation step S, for alternative DES representation
T: white-box-obfuscated computation step S, having S embedded in T where applicable
x: input value in computation step S (or T)
y: obfuscation value
r: expanded right side of the input of a round
k: key
s: output value of S (e.g. S-box)
w: output value of T(masked S)
If S=DES S-box or eight DES S-boxes:
x=r XOR k for standard representation of DES
x=r for alternative representation of DES
l=bits from left side of the bits at the DES round-entry (32 bit)
r=bits from right side of the bits at the DES round-entry (32 bit)
r=bits from expanded right side r at the DES round-entry (48 bit)

CITED PRIOR ART

[0077] [1] A Tutorial on White-box AES, James A. Muir, Cryptology ePrint Archive, Report 2013/104, eprint.iacr.org/2013/104 [0078] [2] DE 102014016548.5 (submitted on 10 Nov. 2014) [0079] [3] Differential Computation Analysis: Hiding your White-Box Designs is Not Enough, J. W. Bos, Ch. Hubain, W. Michiels, and Ph. Teuwen, eprint.iacr.org/2015/753, retrieved on 31 Jul. 2015