Amplifier arrangement

Abstract

An amplifier arrangement is presented, comprising a first differential stage (DS1) comprising at least two transistors (M1, M1) having a first threshold voltage (Vth1), at least a second differential stage (DS2) comprising at least two transistors (M3, M3) having a second threshold voltage different from the first threshold voltage, at least one of the transistors of the first and second differential stage (DS1, DS2), respectively, has a control input commonly coupled to an input of the amplifier arrangement, at least one transistor (M1) of the first differential stage and one transistor (M3) of the second differential stage are arranged in a common current path, which is coupled to an output of the amplifier arrangement.

Claims

1. An amplifier arrangement, comprising: a first differential stage comprising at least two transistors having a first threshold voltage, at least a second differential stage comprising at least two transistors having a second threshold voltage different from the first threshold voltage, at least one of the transistors of the first and second differential stage, respectively, has a control input commonly coupled to an input of the amplifier arrangement, at least one transistor of the first differential stage and one transistor of the second differential stage are arranged in a common current path, which is coupled to an output of the amplifier arrangement, and the input of the amplifier arrangement comprising a differential input with two terminals, a first of which being coupled to the control input of at least one transistor of the first differential stage and to the control input of at least one transistor of the second differential stage, and a second of the differential input terminals being coupled to the control input of at least another transistor of the first differential stage and to the control input of at least another transistor of the second differential stage.

2. The amplifier arrangement of claim 1, in which the two transistors of the first differential stage have a common source node, and in which the two transistors of the second differential stage have a common source node.

3. The amplifier arrangement of claim 2, in which the common source node of the two transistors of the second differential stage is coupled to a drain terminal of one of the transistors of the first differential stage, and wherein the second differential stage comprises a further transistor pair having a common source node, the common source node being coupled to a drain terminal of another one of the transistors of the first differential stage, thus forming a cascade structure.

4. The amplifier arrangement of claim 1, wherein the common current path further comprises a load.

5. The amplifier arrangement of claim 4, the load comprising at least one of the following: a resistor, a current source, a current mirror, a cascode transistor.

6. An amplifier arrangement comprising: a first differential stage comprising at least two transistors having a first threshold voltage, at least a second differential stage comprising at least two transistors having a second threshold voltage different from the first threshold voltage, at least one of the transistors of the first and second differential stage, respectively, has a control input commonly coupled to an input of the amplifier arrangement, at least one transistor of the first differential stage and one transistor of the second differential stage are arranged in a common current path, which is coupled to an output of the amplifier arrangement, and a complementary first differential stage comprising at least two transistors having opposite conductivity type compared to the transistors of the first differential stage, and comprising at least a complementary second differential stage comprising at least two transistors having opposite conductivity type compared to the transistors of the second differential stage.

7. The amplifier arrangement of claim 1, in which at least one control input of one transistor of the first and/or second differential stage is connected to a constant bias voltage.

8. The amplifier arrangement of claim 1, in which the transistors are of Metal Oxide Semiconductor or other field-effect transistor type.

9. The amplifier arrangement of claim 1, wherein the first threshold voltage is defined by a first thickness of the gate oxide of the transistors of the first differential stage, and wherein the second threshold voltage is defined by a second thickness of the gate oxide of the transistors of the second differential stage, different from the first thickness.

10. The amplifier arrangement of claim 1, wherein the first threshold voltage is defined by a first doping of the transistors of the first differential stage, and wherein the second threshold voltage is defined by a second doping of the transistors of the second differential stage, different from the first doping.

11. The amplifier arrangement of claim 1, wherein the first threshold voltage is defined by a first bulk voltage of the transistors of the first differential stage, and wherein the second threshold voltage is defined by a second bulk voltage of the transistors of the second differential stage, different from the first bulk voltage.

12. The amplifier arrangement of claim 1, wherein the first and second threshold voltage is defined by respective dual gate transistors with floating gate.

Description

(1) The present amplifier arrangement will be further explained and illustrated by several embodiments using exemplary schematics.

(2) FIG. 1 shows an exemplary embodiment of the present principle,

(3) FIG. 2 shows a complementary exemplary embodiment based on the one of FIG. 1,

(4) FIG. 3 shows another example adding a third differential stage to the embodiment of FIG. 2,

(5) FIG. 4 shows an additional embodiment as a simplified version of cascading three differential pairs,

(6) FIG. 5 shows an embodiment using current mirrors for providing the output of the amplifier, and

(7) FIG. 6 shows an embodiment using BiCMOS technology.

(8) FIG. 1 shows a first example of an embodiment of an amplifier arrangement according to the present principle. The amplifier arrangement comprises a first differential stage DS1. The first differential stage comprises two MOS transistors M1, M1, the source nodes of which are directly connected together and, via a current source ID, to ground potential. The current source ID supplies the drain current for the two transistors M1, M1. Each transistor M1, M1 has a control input, namely in this case the respective gate terminal. The two gate terminals of the respective transistors of the first differential stage are forming a differential input, at which a differential input signal +VIN1, VIN1 can be supplied. Further on, the amplifier arrangement comprises a second differential stage. The second differential stage DS2 comprises two transistor pairs. Each transistor pair comprises two transistors M3, M3 forming a respective differential pair. Each differential pair comprising the two transistors M3, M3 has their source nodes connected directly together and to a drain terminal of a respective transistor M1, M1 of the first differential stage. Thus, a cascade of differential pairs is constituted.

(9) Each differential pair of the second differential stage has a differential input formed at gate terminals of the respective transistors M3, M3. On the input side, the differential pairs of the second differential stage are connected in parallel to the common differential input of the amplifier arrangement. Therefore, all three differential pairs of the two differential stages are connected in parallel on their input side.

(10) The further processing of the drain currents I1 to I4 given at the four drain terminals of the four transistors M3, M3 of the two differential pairs of the second differential stage are explained later. In the end, an output signal is generated from at least a selection of those four currents.

(11) It should be noted that all transistors M3, M3 of the second differential stage have a second threshold voltage in common which is lower than the first threshold voltage of the two transistors M1, M1 of the first differential stage. The use of transistors M1, M1; M3, M3 with different threshold voltages allows for the correct bias points even when the common mode voltages of both differential stages are the same and the input signal of both differential stages is the same.

(12) The noise power of the circuit of FIG. 1 is smaller compared to a conventional differential pair with the same current consumption. Alternatively, a significant power reduction with the same noise performance is possible.

(13) The noise power of a differential pair of MOS transistors is calculated from

(14) $v_N^2=2*\left(\frac{8*k*T}{3*{\mathrm{gm}}_1}\right).Math.f$
The gm in weak inversion is

(15) $\mathrm{gm}=\frac{I_D}{n.Math.V_t},\mathrm{where}{V}_t=\frac{k.Math.T}{q}.$
By replacing gm in the noise power formula we get

(16) ${\mathrm{Vn}}^2=2.Math.\frac{8.Math.k.Math.T.Math.n.Math.V_t}{3.Math.I_D}.Math.f.$
Therefore, it can be seen that the only way to improve the noise performance with conventional means is increasing the bias current.

(17) The noise efficiency factor NEF of the circuit of FIG. 1 is calculated according to

(18) $\mathrm{NEF}=\sqrt{\frac{{\mathrm{Vn}}^2.Math.I_{\mathrm{tot}}}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{2.Math.8.Math.k.Math.T.Math.n.Math.V_t}{3.Math.I_D}\frac{2.Math.I_D}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{8.Math.n}{3}}$

(19) The four output currents according to FIG. 1 are calculated according to

(20) $I_1=\frac{+{\mathrm{Vin}}_1.Math.{\mathrm{gm}}_{M1}+{\mathrm{Vin}}_1.Math.2.Math.{\mathrm{gm}}_{M3}}{4}$$I_2=\frac{+{\mathrm{Vin}}_1.Math.{\mathrm{gm}}_{M1}-{\mathrm{Vin}}_1.Math.2.Math.{\mathrm{gm}}_{M3}}{4}$$I_3=\frac{-{\mathrm{Vin}}_1.Math.{\mathrm{gm}}_{M1}-{\mathrm{Vin}}_1.Math.2.Math.{\mathrm{gm}}_{M3}}{4}$$I_4=\frac{-{\mathrm{Vin}}_1.Math.{\mathrm{gm}}_{M1}+{\mathrm{Vin}}_1.Math.2.Math.{\mathrm{gm}}_{M3}}{4}$

(21) The output of this circuit is
I.sub.OUT=2.Math.I.sub.12.Math.I.sub.3.

(22) So the gm of the circuit is
gm=gm.sub.M1+2gm.sub.M3.

(23) FIG. 2 shows another exemplary embodiment of the amplifier arrangement according to the proposed principle. The circuit arrangement is based on the one of FIG. 1 and is not described again in this respect. However, further to the circuit of FIG. 1, the embodiment of FIG. 2 is of a complementary structure. Thus, the structure of FIG. 1 is provided again on top of the one already present, but in a manner of axis mirroring. All the additional transistors provided in FIG. 2 are of opposite conductivity type compared to the ones already present in FIG. 1. Thus, PMOS and NMOS transistors are combined.

(24) The amplifier arrangement of FIG. 2 further comprises a complementary first differential stage comprising two transistors M2, M2 having opposite conductivity type compared to the transistors M1, M1 of the first differential stage, and comprises a complementary second differential stage comprising two pairs of two transistors M4, M4 each having opposite conductivity type compared to the transistors M3, M3 of the second differential stage.

(25) Thus, at least one current branch is formed connecting ground to supply potential and comprising a current source, a transistor of the first differential stage, a transistor of the second differential stage, a transistor of the complementary second differential stage, a transistor of the complementary first differential stage and another current source, series connected in the order of appearance.

(26) When using a complementary structure as shown in FIG. 2, the input related noise is

(27) $v_N^2=2*\left(\frac{8*k*T}{3*\left({\mathrm{gm}}_1+{\mathrm{gm}}_2\right)}\right).Math.f$
With the same current flowing through an NMOS and a PMOS structure we get two times that gm of a differential stage. Thus, for the same noise performance the current consumption is half of the differential stage of FIG. 1.

(28) The noise efficiency factor is

(29) $\mathrm{NEF}=\sqrt{\frac{{\mathrm{Vn}}^2.Math.I_{\mathrm{tot}}}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{2.Math.8.Math.k.Math.T.Math.n.Math.V_t}{2.Math.3.Math.I_D}\frac{2.Math.I_D}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{4.Math.n}{3}}$
By combining the complementary differential pair with the current reuse differential pair as proposed in FIG. 2, the complementary current reuse differential pair as shown in FIG. 2 is achieved. The four output currents are in this example

(30) $I_1=\frac{+{\mathrm{Vin}}_1.Math.\left({\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}\right)+{\mathrm{Vin}}_1.Math.2.Math.\left({\mathrm{gm}}_{M3}+{\mathrm{gm}}_{M4}\right)}{4}$$I_2=\frac{+{\mathrm{Vin}}_1.Math.\left({\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}\right)-{\mathrm{Vin}}_1.Math.2.Math.\left({\mathrm{gm}}_{M3}+{\mathrm{gm}}_{M4}\right)}{4}$$I_3=\frac{-{\mathrm{Vin}}_1.Math.\left({\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}\right)-{\mathrm{Vin}}_1.Math.2.Math.\left({\mathrm{gm}}_{M3}+{\mathrm{gm}}_{M4}\right)}{4}$$I_4=\frac{-{\mathrm{Vin}}_1.Math.\left({\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}\right)+{\mathrm{Vin}}_1.Math.2.Math.\left({\mathrm{gm}}_{M3}+{\mathrm{gm}}_{M4}\right)}{4}$

(31) The output of the circuit of FIG. 2 is
I.sub.OUT=2.Math.I.sub.12.Math.I.sub.3.

(32) So the gm of this circuit is
gm=gm.sub.M1+gm.sub.M2+2gm.sub.M3+2gm.sub.M4.

(33) This results in a noise power of

(34) ${\mathrm{Vn}}^2=2.Math.\frac{8.Math.k.Math.T}{3.Math.\left({\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}+2{\mathrm{gm}}_{M3}+2{\mathrm{gm}}_{M4}\right)}.Math.f.$

(35) By choosing
gm.sub.M1=gm.sub.M2=2gm.sub.M3=2gm.sub.M4,
the noise power gets

(36) 0${\mathrm{Vn}}^2=2.Math.\frac{8.Math.k.Math.T}{3.Math.4.Math.{\mathrm{gm}}_{M1}}.Math.f=\frac{4.Math.k.Math.T}{3.Math.{\mathrm{gm}}_{M1}}.Math.f.$

(37) Thus for the same noise performance the current consumption is of the regular differential stage. The noise efficiency factor in this case is

(38) $\mathrm{NEF}=\sqrt{\frac{{\mathrm{Vn}}^2.Math.I_{\mathrm{tot}}}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{2.Math.8.Math.k.Math.T.Math.n.Math.V_t}{4.Math.3.Math.I_D}\frac{2.Math.I_D}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{2.Math.n}{3}}$

(39) If, according to another embodiment shown in FIG. 3, three differential pairs are cascaded in the complementary manner starting from FIG. 2, the resulting threefold cascade has the following output current:
I.sub.OUT=3.Math.I.sub.1+I.sub.2I.sub.3+I.sub.4I.sub.53.Math.I.sub.6I.sub.7+I.sub.8.

(40) The gm and the noise power respectively are thus

(41) $\mathrm{gm}={\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}+2.Math.{\mathrm{gm}}_{M3}++2.Math.{\mathrm{gm}}_{M4}+4.Math.{\mathrm{gm}}_{M5}+4.Math.{\mathrm{gm}}_{M6}\mathrm{and}$${\mathrm{Vn}}^2=2.Math.\frac{8.Math.k.Math.T}{3.Math.\left({\mathrm{gm}}_{M1}+{\mathrm{gm}}_{M2}+2{\mathrm{gm}}_{M3}+2{\mathrm{gm}}_{M4}+4{\mathrm{gm}}_{M5}+4{\mathrm{gm}}_{M6}\right)}.Math.f.$
By choosing
gm.sub.M1=gm.sub.M2=2gm.sub.M3=2gm.sub.M4=4gm.sub.M5=4gm.sub.M5
the noise power gets

(42) ${\mathrm{Vn}}^2=\frac{8.Math.k.Math.T}{9.Math.{\mathrm{gm}}_{M1}}.Math.f$

(43) It is therefore to be concluded that for the same noise performance the current consumption is of the conventional differential stage and the noise efficiency factor is

(44) $\mathrm{NEF}=\sqrt{\frac{{\mathrm{Vn}}^2.Math.I_{\mathrm{tot}}}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{2.Math.8.Math.k.Math.T.Math.n.Math.V_t}{6.Math.3.Math.I_D}\frac{2.Math.I_D}{V_t.Math.4.Math.k.Math.T}}=\sqrt{\frac{4.Math.n}{9}}.$

(45) FIG. 4 shows a simplified version of the circuit of FIG. 3 and another exemplary embodiment of an amplifier arrangement according to the proposed principle. The circuit of FIG. 4 has three cascaded differential stages similar to FIG. 3 but, similar to FIG. 1 does not comprise a complementary section that is axis mirrored. The circuit of FIG. 3 is further simplified by combining current branches that have the same structure and the same signals, resulting in some transistors of the third differential stage having the double channel width than other transistors of the same stage.

(46) The output current of this circuit is
I.sub.OUT=3.Math.I.sub.1+I.sub.2I.sub.33.Math.I.sub.4.

(47) Another exemplary embodiment of the proposed principle is shown in FIG. 5. The example of FIG. 5 is based on the structure of FIG. 2 and further developed to obtain a transconductance amplifier OTA. The current outputs are fed into two push-pull current mirrors PP1, PP2 that are shown in FIG. 5 on both sides of the complementary two differential stages shown in the center. Also as in FIG. 2 the differential inputs of all differential stages are connected directly in parallel to form the common differential amplifier input where the differential input signal +VIN, VIN can be fed in.

(48) The differential voltage output is formed at the output sides of the two push pull current mirror stages. There, the differential output voltage +VOUT, VOUT can be tapped of.

(49) Due to the principle of having different threshold voltage transistors for the differential stages of the amplifier, the same common mode voltage can be used for the whole amplifier arrangement and this is defined at the bias current branch on the very left of the embodiment of FIG. 5.

(50) The circuit of FIG. 5 provides a fully differential operational transconductance amplifier OTA with complementary cascaded twofold input stage including the current mirrors PP1, PP2 for a full swing output. The current mirrors PP1, PP2 have the ratio 1:N defined by the ratio of the current mirror transistors respectively.

(51) FIG. 6 shows another exemplary embodiment of an amplifier arrangement according to the proposed principle. The arrangement is based on the embodiment of FIG. 1 but contrary to that the embodiment of FIG. 6 implements a combination of bipolar transistors and MOS transistors. As to that, the first differential stage DS1 is realized using two NPN transistors instead of two MOS transistors M1, M1. Accordingly, instead of connecting the source terminals as in FIG. 1 the emitter terminals of the transistors M1, M1 are directly connected together and via the current source ID to ground.

(52) The second differential stage DS2 comprising the two differential pairs each comprising two MOS transistors M3, M3 is equal to the one shown in FIG. 1 and therefore not described again here.

(53) Also the functionality of the circuit of FIG. 6 basically corresponds to the one of FIG. 1. Combining bipolar and MOS transistors gives the corresponding functionality as using MOS transistors with different threshold voltage. Thus similar to FIG. 1 with this embodiment shown in FIG. 6 all input terminals of all differential pairs of all differential stages can be directly connected together in a parallel fashion on the input side of the amplifier arrangement.

(54) The generation of different threshold voltages can be done by the person skilled in the art using different transistor designs. For example using different gate oxide thicknesses or different doping or different threshold implant results in the desired effect.

(55) Alternatively the generation of different threshold voltages can be done using dual gate technology with floating gate. Also, the generation of different threshold voltages can be done using different bulk voltages.

(56) Alternative to the embodiments shown above, it is possible to connect one or more gate terminals of the MOS transistors involved to a bias voltage which is constant instead of applying the input voltage. Thus the basic effect of the proposed principle can still be achieved.

(57) Alternative to the implementation shown in FIG. 5, the load of the differential pair that can be applied to any of the circuits shown above can be selected from the following: Current mirror, current source, resistor, cascode or folded cascode.