SYSTEMS AND METHODS FOR CMOS-INTEGRATED JUNCTION FIELD EFFECT TRANSISTORS FOR DENSE AND LOW-NOISE BIOELECTRONIC PLATFORMS

Abstract

A complementary metal oxide semiconductor (CMOS)-integrated junction field effect transistor (JFET) has reduced scale and reduced noise. An exemplary JFET has a substrate layer of one dopant type with a gate layer of that dopant type disposed on the substrate, a depletion channel of a second dopant type disposed on the first gate layer, and a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor. The second gate layer can separate the depletion channel from the surface, and the depletion channel separates the first gate layer from the second gate layer.

Claims

1. An integrated junction field effect transistor formed as a complementary metal oxide semiconductor, comprising: a substrate layer of a first dopant type; an isolation well of a second dopant type disposed above the substrate; a first gate layer of the first dopant type disposed above the isolation well; a depletion channel of the second dopant type disposed above the first gate layer; and a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer.

2. The transistor as claimed in claim 1, wherein the isolation well of the second dopant type is disposed between and separating the substrate layer and the first gate layer.

3. The transistor as claimed in claim 1, further comprising a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel.

4. The transistor as claimed in claim 3, wherein the transistor is free of shallow trench isolation between the second gate layer and each of the source and drain contacts.

5. The transistor as claimed in claim 3, further including shallow trench isolation between the second gate layer and each of the source and drain contacts.

6. The transistor as claimed in claim 1, wherein the first dopant type is P-type and the second dopant type is N-type.

7. The transistor as claimed in claim 1, wherein the first dopant type is N-type and the second open type is P-type.

8. A plurality of transistors as claimed in claim 1, configured as an array.

9. A method of making a junction field effect transistor using a complementary metal oxide semiconductor (CMOS) process, comprising: providing a substrate layer of a first dopant type; forming an isolation well of the second dopant type above the substrate; forming a first gate layer of the first dopant type above the isolation well; forming a depletion channel of the second dopant type above the first gate layer; and forming a second gate layer of the first dopant type above the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer.

10. A method of making the transistor as claimed in claim 9, wherein the isolation well of the second dopant type is disposed between and separating the substrate layer and the first gate layer.

11. A method of making the transistor as claimed in claim 9, further comprising a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel.

12. A method of making the transistor as claimed in claim 9, wherein the transistor is free of shallow trench isolation between the second gate layer and each of the source and drain contacts.

13. A method of making the transistor as claimed in claim 9, wherein the transistor is formed using a 180 nm process.

14. A method of making the transistor as claimed in claim 9, wherein the first dopant type is P-type and the second dopant type is N-type.

15. A method of making the transistor as claimed in claim 9, wherein the first dopant type is N-type and the second open type is P-type.

16. A method of making the plurality of transistors as claimed in claim 9, configured as an array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated and constitute part of this disclosure, illustrate some embodiments of the disclosed subject matter.

[0016] FIG. 1 is a diagram illustrating an exemplary JFETJC device structure.

[0017] FIG. 2 is a diagram illustrating an exemplary JFETJC noise spectrum.

[0018] FIG. 3 is a diagram illustrating an exemplary Modified JFET device structure according to the disclosed subject matter.

[0019] FIG. 4 is a diagram illustrating an exemplary Modified JFET noise spectrum according to the disclosed subject matter.

[0020] FIG. 5 is a diagram illustrating an exemplary JFET noise spectrum, as compared with an exemplary JFETJC noise spectrum.

[0021] FIG. 6 is a diagram illustrating an exemplary JFET-input CMOS OTA.

[0022] FIG. 7 is a diagram illustrating an exemplary current integrating amplifier utilizing JFET-CMOS OTA.

[0023] FIG. 8 is a diagram illustrating an exemplary method of making a junction field effect transistor according to the disclosed subject matter.

DETAILED DESCRIPTION

[0024] Junction field-effect transistors can provide low gate leakage current, low white voltage noise, and low flicker noise. One integrated-circuit alternative can be a MOS transistor, which can have negligible gate current and increased white noise, but an increased flicker voltage noise.

[0025] According to one aspect of the disclosed subject matter, a low-noise CMOS-integrated n-channel JFET device is provided, with current noise up to 410.sup.18 A.sup.2/Hz at f=1 Hz with =1.03 (1/f.sup.). An exemplary JFET device can be implemented, for example and without limitation, in an IBM 0.18 m CMOS technology. Certain CMOS JFET designs can be configured for high-voltage operation up to 8 volts between device terminals, but can have unsuitable noise performance due at least in part to the presence of shallow trench isolation (STI) in the vicinity of the JFET channel. In an exemplary JFET of the disclosed subject matter, without any process modifications, the STI can be removed from the junction regions. As illustrated herein, such a modification can decrease the drain current flicker noise power by a factor of 100 or more.

[0026] For purpose of comparison to the disclosed subject matter, a conventional JFET structure, known as JFETJC, is shown in FIG. 1. The transistors use two additional mask levels (PI 103, which defines the n-type triple well, and JC, which defines the JFET channel 106 and p-type inner well 104) to construct a full n-channel JFET in IBM's 0.18 m process. As shown in FIG. 1, this device has STI regions 109 in the vicinity of the channel. These silicon dioxide interfaces near the channel can produce charge trapping, which can degrade the device flicker noise performance. The measured noise performance of this device is shown in FIG. 2 for a width of 320 m and length of 500 nm.

[0027] Referring to FIG. 3, an exemplary JFET structure will be described. In accordance with the disclosed subject matter, shallow trench isolation (STI) 309 can be removed from the devices with the addition of a blocking layer, for example and embodied herein as a polysilicon (PC) layer 310, to replace the STI. As embodied herein, PC can act as a blocking layer, thereby breaking the conductive salicide that can be present to reduce the diffusion contact resistances. PC can also block the dopant implant between the source gate and drain of the transistor, as shown for example in FIG. 3. The flicker noise spectrum of the exemplary JFET device is shown in FIG. 4 at the same device geometry and biasing conditions.

[0028] The drain current flicker noise can be reduced by a factor of 100 or more in the exemplary JFET, as shown in FIG. 5. Although the blocking layer described herein is a PC blocking layer, any layer that effectively isolates the source, gate and drain surface conduction and breaks the salicide can be utilized, including for example and without limitation an OP mask which can function as a salicide block, for example when combined with BP2ND, a n+ and p+ dopant block mask.

[0029] According to another aspect of the disclosed subject matter, JFET devices described herein can allow for the design of a low-noise JFET-input, complementary metal oxide semiconductor (CMOS) operational transconductance amplifier (OTA), as shown for example in FIG. 6. FIG. 6 shows an exemplary folded cadcode OTA using JFET devices for the inputs 601 and 601b. Transistors 602, 603a, and 603b can supply the device bias current, and transistors 604a through 604d can act as an active load. Transistors 605 and 605b can function as the cascode devices, which can increase the output impedance of the amplifier, thereby increasing the gain. The Vdd voltage 606 can be raised to account for the depletion mode functioning of the JFET, as with the JFETJC. The JFET-CMOS OTA can form the basic building block for a number of circuits that can benefit from the JFET input stage. Without limitation to the OTA designs described herein, the JFET-CMOS devices can be used to decrease noise and capacitance for any OTA design. For example, the JFET-CMOS OTA can be used as an amplifier in a variety of small-signal current and voltage measurements.

[0030] A JFET-CMOS OTA can provide reduced flicker noise and input capacitance when compared with other CMOS OTAs. This reduced noise and capacitance can be suitable for low-noise transimpedance amplifier (TIA) applications.

[0031] According to another aspect of the disclosed subject matter, a low-noise TIA utilizing JFET-CMOS OTAs described herein is shown for example in FIG. 7. C.sub.par 701 and R.sub.par 702 can represent parasitic capacitance and resistance associated with the physical structure of the connected current mode sensor. I.sub.sig can represent the signal current of the sensor which can vary based at least in part on the device function. V.sub.bias 704 can be a designer-set voltage, which can be chosen to allow for suitable functioning of the sensor based on that device's operating region. Op amp 705 can represent the JFET-input CMOS OTA building block. C.sub.F 706 can represent the feedback capacitance of the TIA, which can set the gain of the amplifier. The value of C.sub.F 706 can also vary based on the value of I.sub.sig 703. Typical values for C.sub.F 706 can be application-specific and thus can vary from about 10 fF to 50 pF. Such an integrating amplifier design can have applications in the measurement of biological and solid state nanopore sensors, nanogap sensors, and other current output sensors that utilize low-noise current measurement. The use of an integrated amplifier can allow for close integration with the sensors, reducing parasitic capacitances and electromagnetic interference. Arrays of these amplifiers can also be integrated on the same substrate.

[0032] Nanopore sensors can operate using detection of current changes in the picoamp regime. The current can indicate the blockade of the electrolytic conduction through the pore by the translocation of single molecules. Such techniques can be used to study many types of biomolecules, including DNA, RNA, and proteins. Such techniques can also be used for nanopore sequencing of DNA.

[0033] Nanogap sensors can also benefit from low-noise TIAs created with JFET input devices. Nanogap sensors can use electrochemical detection through repeated oxidation and reduction of analytes, and currents in the femtoampere range can be typical. These amplifiers can have voltage-clamp applications in electrophysiology.

[0034] According to another aspect of the disclosed subject matter, a method for reducing noise in a JFET implemented in CMOS-technology is shown for example in FIG. 8. As shown in FIG. 8, at 801, a substrate of a first dopant type can be provided and, at 802, can have a second dopant type well deposited thereon. The well can be doped with the first dopant type to form the back gate contacts at 803. The back gate bottom of the first dopant type and channel of the second dopant type can be formed, along with the source and drain contacts at 804. The top gate can be formed at 805, for example, using the first dopant. Formation of the top gate can include deposition of the blocking layer as described herein.

[0035] The foregoing merely illustrates the principles of the disclosed subject matter. Various modifications and alterations to the described embodiments will be apparent to those skilled in the art in view of the teachings herein. It will thus be appreciated that those skilled in the art will be able to devise numerous techniques which, although not explicitly described herein, embody the principles of the disclosed subject matter and are thus within its spirit and scope.