Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas

Abstract

A HEMT device comprising a M-plane III-Nitride material substrate, a p-doped epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said p-doped epitaxial layer, the recess having a plane wall parallel to a polar plane of the III-Nitride material; a carrier carrying layer formed on said plane wall of the recess; a carrier supply layer formed on said at least one carrier carrying layer, such that a 2DEG region is formed in the carrier carrying layer at the interface with the carrier supply layer along said plane wall of the recess; a doped source region formed at the surface of said p-doped epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region; a gate insulating layer formed on the channel region; and a gate contact layer formed on the gate insulating layer.

Claims

1. A method for making a HEMT device, the method comprising: providing a III-Nitride material substrate having a top plane surface that is not parallel to a C-plane of the III-Nitride material substrate; growing a p-doped epitaxial layer of III-Nitride material on said top surface of said substrate; etching in said p-doped epitaxial layer a recess having at least one plane wall that is not parallel to the surface of the substrate; said at least one plane wall being parallel to a polar plane of the III-Nitride material of the p-doped epitaxial layer; forming a carrier carrying layer on said at least one plane wall of the recess; forming on at least a portion of said carrier carrying layer a carrier supply layer such that a 2DEG region is formed in the carrier carrying layer at the interface with the carrier supply layer along said at least one plane wall of the recess; forming a doped source region at the surface of said p-doped epitaxial layer, such that the doped source region is separated from said 2DEG region by a channel region; forming a gate insulating layer on the channel region; and forming a gate contact layer on the gate insulating layer.

2. The method of claim 1, comprising arranging said p-doped epitaxial layer and said 2DEG region such that in the off-state HEMT the carriers in said p-doped epitaxial layer, said carrier carrying layer and said 2DEG region deplete each other, leaving behind a net effective charge that sums to zero, thus generating a uniform electric field distribution across the 2DEG region.

3. The method of claim 1, wherein said channel region extends parallel to the surface of the substrate.

4. The method of claim 1, wherein said channel region extends parallel to said at least one plane wall of the recess.

5. The method of claim 4, said at least one carrier supply layer and said at least one carrier carrying layer are arranged on said at least one plane wall of the recess such that a further 2DEG region is formed along the channel region.

6. The method of claim 1, wherein said at least one plane wall of the recess is parallel to the C-plane of the III-Nitride material.

7. The method of claim 6, wherein at least one plane wall of the recess is perpendicular to the surface of the substrate.

8. The method of claim 7, wherein the surface of the substrate is parallel to a M-plane of the III-Nitride material of the p-doped epitaxial layer.

9. The method of claim 7, wherein the surface of the substrate is parallel to the A-plane of the III-Nitride material.

10. The method of claim 1, wherein the III-Nitride material substrate is GaN.

11. The method of claim 10, wherein the III-Nitride material of the p-doped epitaxial layer is GaN.

12. The method of claim 11, wherein the carrier supply layer comprises one of an epitaxial single crystal AlGaN, an epitaxial GaN/AlGaN and an epitaxial AlN/AlGaN, and the carrier carrying layer comprises unintentionally doped epitaxial single crystal GaN.

13. The method of claim 1, comprising forming a spacer layer formed between the carrier carrying layer and the carrier supply layer.

14. The method of claim 13, wherein the spacer layer comprises AlN.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention(s) may be better understood by referring to the following figures. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.

(2) FIG. 1A illustrates a cross-section of a portion of a prior art high voltage 2DEG lateral HEMT.

(3) FIGS. 1B and 1C illustrate a cross-section of a portion of a prior art high voltage super junction lateral MOSFET and the electric field distribution in the super junction.

(4) FIG. 2 illustrates a cross-section of a portion of a prior art high voltage vertical FET.

(5) FIGS. 3a and 3B illustrate a wafer of a C-plane substrate of a III-Nitride material as well as a 2DEG formed on said C-plane substrate.

(6) FIG. 4 is a projection view of a crystal of a III-Nitride material.

(7) FIGS. 5A and 5B illustrate a wafer of a M-plane substrate of a III-Nitride material as well as a 2DEG formed on said M-plane substrate according to embodiments of the present disclosure.

(8) FIGS. 6A and 6B illustrate a cross-section of a portion of a high voltage super junction vertical HEMT according to an embodiment of the present disclosure, and the electric field distribution in the super junction.

(9) FIG. 6C illustrates a cross-section of a portion of a high voltage super junction vertical HEMT according to an embodiment of the present disclosure.

(10) FIGS. 7A and 7B illustrate a cross-section of a portion of a high voltage super junction vertical trench HEMT according to embodiments of the present disclosure.

(11) FIGS. 8A and 8B illustrate a cross-section of a portion of a high voltage super junction vertical trench HEMT according to embodiments of the present disclosure.

(12) FIG. 9 illustrates a method of manufacturing a high voltage super junction vertical trench HEMT according to embodiments of the present disclosure.

DETAILED DESCRIPTION

(13) FIG. 3a illustrates a wafer of a C-plane substrate 16 of a III-Nitride material, for example GaN. The crystalline structure of the III-Nitride material is such that its C-plane is polar; i.e. exhibits noticeable spontaneous and piezoelectric polarization effects in a direction perpendicular to its surface. As illustrated in FIG. 3B, the resulting polarization field 60 can result in a two-dimensional carrier confinement, also known as 2DEG, 62 along the surface of substrate 16 if a barrier layer or carrier supplying layer 18 is formed on top of said surface.

(14) FIG. 4 is a projection view of a crystal of a III-Nitride material such as GaN, showing in particular that the III-Nitride material comprises two non-polar planes: the M-plane and the A-plane, which are perpendicular to each other and also perpendicular to the polar, C-plane.

(15) According to an embodiment of the present disclosure, the III-Nitride substrate is preferably configured such that the surface of the substrate is parallel to the M-plane (M-plane substrate) or the A-plane of the III-Nitride material (A-plane substrate). As disclosed hereafter, such configuration allows forming in the substrate vertical trenches (trenches normal to the surface) having trench walls parallel to the C-plane of the III-Nitride material. This allows forming a dense 2DEG along the trench walls.

(16) However, according to embodiments of the present disclosure, the III-Nitride substrate can also be configured such that the surface of the substrate makes an angle (different from 90 degree) with respect to the M-plane or the A-plane of the III-Nitride material. Such configuration allows forming in the substrate vertical trenches having trench walls not normal to the C-plane of the III-Nitride material, which allows forming along the trench walls a 2DEG of reduced density due to the angle between the trench walls and the C-plane.

(17) FIG. 5A illustrates a wafer of a M-plane III-Nitride wafer 63 according to an embodiment of the present disclosure. The crystalline structure of the III/Nitride wafer 63 is such that its M-plane is non-polar; the polarization field 66 of the III-Nitride wafer 64 being internal and parallel to the surface of the III-Nitride wafer 63.

(18) FIG. 5B illustrates a portion of a cross section of wafer 63. According to an embodiment of the present disclosure, the III-Nitride wafer 63 comprises a free standing bulk III-Nitride material substrate 64. According to the present disclosure, a p-doped epitaxial layer 65 of the same III-Nitride material as substrate 64 is grown (e.g. by homoepitaxial process) on the surface of substrate 64. According to an embodiment of the present disclosure, layer 65 can be a single crystal GaN layer. According to the present disclosure, P-species can be incorporated in layer 65 during the growth of layer 65, similar to what is for example disclosed in the reference: Understanding The Breakdown Characteristics of Lateral GaN-Based HEMTs, How2Power Today Newsletter, by M. A. Briere. P-species can include Magnesium. Incorporation in-situ of the p-type dopant can be advantageous because the high temperature of the epitaxial growth process facilitates the activation of the dopant atoms. The epitaxial growth of layer 65 on a bulk substrate 64 of a same material ensures that epitaxial layer 65 has a similar crystallographic arrangement as III-Nitride substrate 64.

(19) FIG. 5B also shows a plurality of recesses 68 etched in the p-doped epitaxial layer 65. According to an embodiment of the present disclosure, each recess 68 comprises at least one plane wall 70 that is perpendicular to the surface of the III-Nitride substrate 64, and that is parallel to the C-plane of the III-Nitride material of layer 65. The polarization field 66 present at the surface of plane wall 70 is perpendicular to the surface of plane wall 70. According to an embodiment of the present disclosure, the polarization field 66 present at the surface of plane wall 70 can result in a two-dimensional carrier confinement, or 2DEG, in the III-Nitride substrate 65 along the surface of plane wall 70 if a carrier supply layer is formed on the surface of plane wall 70. The recess/trench 68 can be formed by one of the methods used to form high aspect ratio trenches such as reactive ion etching. During the etching process the masking layer is preferably a hard mask layer, such as silicon nitride or a stack of photoresist on top of a hard masking layer or any other alternatives that will enable the definition of the trench area.

(20) According to an alternative embodiment of the present disclosure, each recess 68 can comprise a plane wall 70 that is not normal to the surface of the III-Nitride substrate 64, and that makes an angle with respect to the C-plane of the III-Nitride material. The polarization field 66 present at the surface of plane wall 70 is then not perpendicular to the surface of plane wall 70, which results in 2DEG of reduced density in the III-Nitride substrate 65 along the surface of plane wall 70 if a carrier supply layer is formed on the surface of plane wall 70.

(21) FIG. 6A illustrates a cross-section of a portion of a high voltage super junction vertical HEMT 75 according to an embodiment of the present disclosure. III-Nitride wafer 63 comprises a free standing bulk III-Nitride material substrate 64 and a p-doped epitaxial layer 65 of III-Nitride material grown on substrate 64. For clarity, the polarization field 66 of layer 65 is not illustrated in the present figure. According to an embodiment of the present disclosure, the polarization field 66 is perpendicular to the surface of plane wall 70 as shown in FIG. 5B. According to an embodiment of the present disclosure, the surface of III-Nitride substrate 64 follows a plane that is not parallel to the C-plane of the III-Nitride material. For example, III-Nitride substrate 64 can be an n+ M-plane free standing GaN substrate. As outlined above, the epitaxial growth of p-doped layer 65 on a bulk substrate of a same material ensures that epitaxial layer 65 has a similar crystallographic arrangement as III-Nitride substrate 64.

(22) According to an embodiment of the present disclosure as shown in FIG. 6A, HEMT 75 comprises at least one recess 68 etched in epitaxial layer 65. According to an embodiment of the present disclosure, recess 68 can be a vertical trench that extends through epitaxial layer 65 and stops at the interface between epitaxial layer 65 and III-Nitride substrate 64, as shown in solid lines in FIG. 6A. According to an embodiment of the present disclosure, recess 68 can be a trench that extends through epitaxial layer 65 and penetrates III-Nitride substrate 64, as shown in dashed lines with the reference 77 in FIG. 6A. According to an embodiment of the present disclosure, recess 68 can be a trench that extends into epitaxial layer 65 without reaching III-Nitride substrate 64, as shown in dashed lines with the reference 79 in FIG. 6A.

(23) According to an embodiment of the present disclosure, recess 68 comprises at least one plane wall 70 that is not parallel to the surface of the III-Nitride substrate 64. According to an embodiment of the present disclosure, plane wall 70 is parallel to a polar plane of the III-Nitride material. Where III-Nitride substrate 64 is an M-plane substrate and recess 68 is a vertical trench, plane wall 70 can be parallel to the C-plane of the material of III-Nitride substrate 64 and epitaxial layer 65.

(24) According to an embodiment of the present disclosure, a carrier carrying layer 73 is grown on at least a portion of plane wall 70 of recess 68. According to an embodiment of the present disclosure, carrier carrying layer 73 can be made of unintentionally doped material. For example, where the III-Nitride substrate 64 is an n+ M-plane free standing GaN substrate, and epitaxial layer 65 a p-doped M-plane epitaxial layer, carrier carrying layer 73 can be an unintentionally doped GaN epitaxial layer that has a similar M-plan crystallographic arrangement as III-Nitride substrate 64 and epitaxial layer 65. The grown UID GaN can have an effective doping of n-type carriers with concentration of the order of 110.sup.16 cm.sup.3. Advantageously, carrier carrying layer 73 can have a defect density lower than in epitaxial layer 65.

(25) According to an embodiment of the present disclosure, a carrier supply layer 74 is grown on at least a portion of carrier carrying layer 73 such that a 2DEG region 72 is formed in the carrier carrying layer 73 at the interface with the carrier supply layer 74, along the surface of plane wall 70. According to an embodiment of the present disclosure, carrier supply layer 74 can be an epitaxial single crystal AlGaN, an epitaxial single crystal GaN/AlGaN or an epitaxial single crystal AlN/AlGaN. Carrier carrying layer 73 and carrier supply layer 74 can be grown by epitaxy. Aluminum mole fraction level can range from 10% to 45% for AlGaN.

(26) In the embodiment illustrated in FIG. 6A, carrier supply layer 73 covers completely plane wall 70 and carrier supply layer 74 covers completely carrier supply layer 73, so that 2DEG region 72 extends along the entire plane wall 70. According to an embodiment of the present disclosure, a passivation layer 80 (for example Si3N4) can be formed on carrier supply layer 74.

(27) As shown in FIG. 6A, according to an embodiment of the present disclosure HEMT 75 comprises a doped source region 82 formed at the surface of epitaxial layer 65, for example by doping a region of the surface of epitaxial layer 65 extending parallel to the surface of substrate 64, such that the doped source region 82 is separated from the 2DEG region 72 by a channel region 84 that extends parallel to the surface of substrate 64 in the top of epitaxial layer 65 and carrier carrying layer 73. According to an embodiment of the present disclosure, HEMT 75 comprises a gate insulating layer 86 formed on the channel region 84 of the epitaxial layer 65, and a gate contact layer 88 formed on the gate insulating layer 86. According to an embodiment of the present disclosure, the gate insulating layer 86 and gate contact layer 88 cover a portion of the source region 82 and a portion of carrier supply layer 74. According to an embodiment of the present disclosure, HEMT 75 comprises a drain contact region 89 on the bottom surface of substrate 76.

(28) According to an embodiment of the present disclosure, at least a portion of the drift region of HEMT 75 comprises 2DEG region 72. According to an embodiment of the present disclosure, p-doped epitaxial layer 65 forms the P-doped stripe, or column, of a super junction and 2DEG region 72, along with carrier carrying layer 73, form the N-doped stripe, or column, of the super junction. According to an embodiment of the present disclosure, the effective n-type charge of the super junction is the total charge of both the UID carrier carrying layer 73 and the 2DEG layer 72 formed at the heterointerface between the UID carrier carrying layer 73 and the carrier supply layer 74.

(29) According to an embodiment of the present disclosure, p-doped epitaxial layer 65 and 2DEG region 72 are arranged such that, in the off-state HEMT, the charges introduced by the p-doped epitaxial layer 65, the carrier carrying layer 73 and the 2DEG region 72 generate a uniform electric field distribution across the 2DEG region. Preferably, the charge density of 2DEG region 72 is adjusted such that the total charge of both the carrier carrying layer 73 and the 2DEG region 72 result in an effective integrated charge equal to that introduced by p-doped epitaxial layer 65.

(30) According to an embodiment of the present disclosure, HEMT 75 operates as follows: during the on-state operation, a gate voltage (VG) is applied to the gate contact layer 88 by a gate electrode, where VG>pinch off voltage (Vp) of the device. A channel is formed under the gate contact layer 88 in channel region 84 if VG is sufficiently larger than Vp. The channel formed in channel region 84 under the gate contact layer 88 provides a low resistive path for carriers to flow from the source region 82 to the 2DEG region 72. The initial current flow in HEMT 75 is lateral, under the gate contact layer 88, then vertical in the 2DEG region 72 where carriers flow with high mobility towards substrate 76, and finally flow out of the drain contact region 89.

(31) During the off-state, a gate voltage is applied to the gate electrode where VG<Vp (more negative than the pinch off voltage). No channel is formed between the source region 82 and the 2DEG region 72. The positive drain voltage across the drift region is then supported by 2DEG region 72, depleted by p-doped region 65. As outlined above the charge carriers, in the p-doped region 65 on one hand and 2DEG region 72 and charge carrying layer 73 on the other hand, deplete by drifting under the electric field towards their respective contacts, leaving behind bound ion charges of opposite polarities. According to an embodiment of the present disclosure, the opposite bound ion charges are equal in magnitude and closely spaced, and the net effective charge sum to a net zero value and result in a flat electric field distribution as illustrated in FIG. 6B. The super junction in HEMT 75 maintains a high breakdown voltage despite 2DEG region 72 by depleting 2DEG region 72 with p-doped region 65 before the critical electric field of HEMT 75 is reached. According to an embodiment of the present disclosure, doping of region 65 is a function of the width of the p column, which will be determined by the subsequent etch process.

(32) According to an embodiment of the present disclosure, HEMT 75 can be formed as detailed above but without the charge carrying layer 73, so that 2DEG region 72 is formed in the p-doped region 65 at the interface with the charge-supplying layer 74. In such embodiment, p-doped region 65 and charge-supplying layer 74 are arranged such that the charges introduced by p-doped epitaxial layer 65 and 2DEG region 72 in the off-state HEMT generate a uniform electric field distribution across the 2DEG region.

(33) According to an embodiment of the present disclosure, the super junction in HEMT 75 results in a lower on-state resistance since the structure enables the use of higher 2DEG density without impacting the Breakdown voltage (to a first order approximation) and also due to the use of a shorter drift region. Further, the flat electric field allows having a smaller drift region length which allows having a thinner Epitaxial layer 65 which allows having higher throughput of the Epi reactor, lower specific R.sub.on and lower cost.

(34) FIG. 6C illustrates a cross-section of a portion of a high voltage super junction vertical HEMT 91 according to an embodiment of the present disclosure, essentially identical to high voltage vertical HEMT 75 of FIG. 6A, but wherein in addition a spacer layer 93 was grown between carrier supply layer 74 and the carrier carrying layer 73 for the purpose of enhancing the mobility of the 2DEG electrons in carrier carrying layer 73, the carrier supply layer 74 being subsequently grown on the spacer layer. The spacer layer 93 can for example be made of AlN if the carrier supply layer 74 is made of AlGaN, for example to prevent alloy disorder effect at the interface between the carrier supply layer 74 and the carrier carrying layer 73.

(35) FIG. 7A illustrates a cross-section of a portion of a high voltage super junction vertical HEMT, or trench HEMT, 90 according to an embodiment of the present disclosure, made in a III-Nitride wafer 63 that comprises a free standing bulk III-Nitride material substrate 64 and a p-doped epitaxial layer 65 of III-Nitride material grown on substrate 64 as described previously in relation with FIG. 6A. According to an embodiment of the present disclosure, HEMT 90 comprises at least one recess 68 etched in p-doped epitaxial layer 65 as described previously in relation with FIG. 6A. For clarity, the polarization field 66 in wafer 63 is not illustrated in the present figure. According to an embodiment of the present disclosure, the polarization field 66 is perpendicular to the surface of plane wall 70 as shown in FIG. 5B.

(36) According to an embodiment of the present disclosure, a carrier carrying layer 73 is grown on plane wall 70 of recess 68, and a carrier supply layer 74 is formed on a portion of carrier carrying layer 73 such that a 2DEG region 72 is formed in carrier carrying layer 73 along said portion of carrier carrying layer 73.

(37) According to an embodiment of the present disclosure, carrier carrying layer 73 can be unintentionally doped epitaxial GaN and carrier supply layer 74 can be an epitaxial single crystal AlGaN, an epitaxial single crystal GaN/AlGaN or an epitaxial single crystal AlN/AlGaN.

(38) According to an embodiment of the present disclosure, HEMT 90 comprises a doped source region 92 formed at the top of p-doped epitaxial layer 65 and carrier carrying layer 73, and extending parallel to the surface of substrate 64 up to the edge carrier carrying layer 73. According to an embodiment of the present disclosure, HEMT 90 comprises a gate insulating layer 94 formed on the portion of carrier carrying layer 73 not covered by carrier supply layer 74. The insulating layer can also be covering a top surface of carrier supply layer 74 in recess 68. According to an embodiment of the present disclosure, HEMT 90 comprises a gate region 96 formed in recess 68 on the gate insulating layer 94, thus forming a vertical channel region 98 in the portion of carrier carrying layer 73 that comprises no 2DEG region 72. According to an embodiment of the present disclosure, HEMT 90 comprises a drain contact region 89 on the bottom surface of substrate 64. At least a portion of the drift region of HEMT 90 comprises 2DEG region 72.

(39) According to an embodiment of the present disclosure, HEMT 90 operates substantially as HEMT 75, except that in on-state operation a vertical channel is formed along the gate region 96 in channel region 98 if VG (voltage of the gate) is sufficiently larger than Vp (pinch off voltage of HEMT 90), which provides a low resistive path for carriers to flow from the source region 92 to the 2DEG region 72. The current flow in HEMT 90 is vertical along the gate region 96, then vertical in the 2DEG region 72 where carriers flow with high mobility towards substrate 64, and finally flow out of the drain contact region 89.

(40) During the off-state, a gate voltage is applied to the gate electrode where VG<Vp (more negative than the pinch off voltage). No channel is formed between the source region 92 and the 2DEG region 72. The charges from p-doped region 65 deplete 2DEG 72 and the positive drain voltage across the drift is then supported by a depleted 2DEG region. According to an embodiment of the present disclosure, the super junction formed by p-doped region 65, carrier carrying layer 73 and 2DEG region 72 is designed to support the full drain voltage of HEMT 90 in off state.

(41) FIG. 7B illustrates a cross-section of a portion of a high voltage super junction vertical HEMT 97 according to an embodiment of the present disclosure, essentially identical to high voltage vertical HEMT 90 of FIG. 7A, but wherein in addition a spacer layer 95 similar to the one described in relation with FIG. 6C was formed prior to the carrier supply layer 74 on the carrier carrying layer 73, the carrier supply layer 74 being subsequently grown on the spacer layer 95.

(42) According to an embodiment of the present disclosure, the following process flow can be used to manufacture one of HEMTs 75, 90, 91, or 97:

(43) A n+ M-plane free standing GaN substrate 64 is provided, that acts as a highly doped drain region and provides a template to grow a layer of a p-doped GaN layer 65 on which the rest of the device structure is implemented. Because the p-doped GaN layer 65 is grown on top of the n+ M-plane GaN substrate 64, it has a similar m-plan crystallographic arrangement.

(44) At least one trench 68 is then etched, for example perpendicular to the substrate plane, in the p-doped GaN layer 65, and extends vertically from the surface of layer 65 down to the n+ substrate 64. This trench might or might not extend deep enough to reach the n+ substrate 64. Depending on device optimization, the trench might penetrate the n+ substrate 64, or stop at the n+ substrate/UID interface or even stop before reaching that interface. The trench has at least one sidewall 70.

(45) Within trench 68, which can be formed by one of the known methods to form high aspect ratio trenches such as reactive ion etching, a carrier carrying layer 73 that can be unintentionally doped GaN is grown is grown on sidewall 70. Then a III-Nitride layer 74, that will ultimately have the function of forming a vertical heteroepitaxial junction, is grown on carrier carrying layer 73. The composition and growth conditions of these heteroepitaxial layers are provided to set the correct conditions for both spontaneous and piezoelectric polarization in a way similar to that of the current supplying layer (typically AlGaN barrier) set the spontaneous and piezoelectric polarization in the conventional lateral HEMT structure of FIG. 1.

(46) According to embodiments of the present disclosure, heteroepitaxial junction layer 74 can be composed of any number of layers. For example, the growth of layer 74 can involve only the regrowth of an AlGaN layer to form a heterostructure with layer 73. In another embodiment a spacer layer, for example of AlN, can be grown between layers 73 and 74.

(47) According to embodiments of the present disclosure, heteroepitaxial junction layer(s) can be any combination of layers, or a single layer of III-Nitride materials, that will result in a vertically oriented heteroepitaxial junction with high quality interface and least defect density and that will enable the formation of the required vertical 2DEG region 72 at an heteroepitaxial interface along sidewall 70.

(48) Regardless of which layer or layers will be used in the step of forming the heteroepitaxial junction layer(s), the end result is to achieve high quality regrown material with low defect density, high mobility of 2DEG and sufficiently high 2DEG density. For example, a 2DEG density of 5e12 to 1e13/cm2 can be considered as sufficiently high.

(49) Further, the doping and thicknesses of layers 73 and 74 and layer 65 are chosen such that the charges introduced by p-doped epitaxial layer 65, carrier carrying layer 73 and 2DEG region 72 in the off-state HEMT generate a uniform electric field distribution across the 2DEG region.

(50) After the growth of the III-Nitride heteroepitaxial junction layer(s) is completed, a deposition or a regrowth of a suitable passivation layer 80 to terminate the regrown layers can be done, as illustrated in FIG. 6A. PECVD, LPCVD or MOCVD Nitride (Si3N4) are all suitable candidates for the passivation step of forming passivation layer 80, however, the disclosure should not be limited to any of these materials and any appropriate passivation material that will have high immunity to current collapse (drain lag) issues will be suitable.

(51) Thereafter a low Ohmic contact region is formed to implement source contact 82 or 92. A masked high dose ion implantation of donor type species such as Silicon followed by an RTA step can be used for source contact formation. Next, an insulating material is deposited or grown on the surface of p-doped epitaxial layer 65 or on a portion of sidewall 70 to form the gate dielectric 86 or 94. The insulating gate process is then followed by the deposition/evaporation with an appropriate gate material (or gate stack) 88 or 96. Back-end of line processes which include intermetallic dielectric deposition and metal evaporation or sputtering processes are done next to implement a low resistive source, drain interconnect network. It should be noted that in this vertical structure the drain metal is deposited at the back side of the wafer. To reduce the drain parasitic resistance, the n+m plan substrate 64 can be thinned to an appropriate thickness before depositing the backside drain metal 89.

(52) FIG. 8A illustrates a cross-section of a portion of a high voltage super junction vertical trench HEMT 100 according to an embodiment of the present disclosure. HEMT 100 is substantially identical to HEMT 90 described in relation with FIG. 7A, except that instead of comprising a carrier supply layer 74 grown only along a lower portion carrier carrying layer 73 along plane wall 70, HEMT 100 comprises a carrier supply layer 74 grown along the full height of carrier carrying layer 73 such that a further 2DEG region 104 is formed in carrier carrying layer 73 in the channel region 98 between source 92 and 2DEG region 72.

(53) According to an embodiment of the present disclosure, carrier supply layer 74 comprises a surface recess 106 in which gate insulating layer 94 and gate region 96 are formed so as to have a vertical channel region 98 as detailed in relation with FIG. 7A. It is noted that, due to the further 2DEG region 104 in the channel region 98, HEMT 100 operates in a depletion mode instead of in an enhancement mode as HEMT 90.

(54) FIG. 8B illustrates a cross-section of a portion of a high voltage vertical HEMT 103 according to an embodiment of the present disclosure, essentially identical to high voltage vertical HEMT 100 of FIG. 8A, but wherein in addition a spacer layer 107 (similar to the spacer layer 95 described previously) was formed on the surface of carrier carrying layer 73 prior to the carrier supply layer 74, the carrier supply layer 74 being subsequently grown on the spacer layer 107.

(55) FIG. 9 illustrates a method of manufacturing a high voltage super junction vertical trench HEMT according to embodiments of the present disclosure. The method comprises:

(56) providing (200) a III-Nitride material substrate (e.g. 64), the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material;

(57) growing (202) a p-doped epitaxial layer (e.g. 65) of III-Nitride material on said substrate;

(58) etching (204) in said p-doped epitaxial layer a recess (e.g. 68) having at least one plane wall (e.g. 70) that is not parallel to the surface of the substrate; said at least one plane wall being parallel to a polar plane of the III-Nitride material;

(59) forming (206) a carrier carrying layer (e.g. 73) on said at least one plane wall of the recess;

(60) forming (208) on at least a portion of said carrier carrying layer a carrier supply layer (e.g. 74) such that a 2DEG region (e.g. 72) is formed in the carrier carrying layer at the interface with the carrier supply layer along said at least one plane wall of the recess;

(61) forming (210) a doped source region (e.g. 82, 92) at the surface of said p-doped epitaxial layer, such that the doped source region is separated from said 2DEG region by a channel region (e.g. 84, 98);

(62) forming (212) a gate insulating layer on the channel region; and

(63) forming (214) a gate contact layer on the gate insulating layer.

(64) It is noted that a super junction HEMT according to the present disclosure improves greatly the scalability to high currents carrying capability as compared to the known, lateral, HEMTs as a result of cell pitch reduction. Indeed, scaling to higher currents capability in lateral GaN HEMTs is a non-trivial issue due to the coupling of current capability, defect density and blocking capability. It follows that a large area device is not capable of supporting high breakdown voltage that a smaller area device according to embodiments of the present disclosure is able to support, with identical design rules/technology.

(65) It is noted that a super junction HEMT according to embodiments of the present disclosure will be suitable for High Voltage GaN device applications including Electrical Vehicles, Trucks, Traction application, HV transmission lines and naval applications where high efficient power switches are required. The total available market of discrete power devices is expected to reach $20 Billion by 2020. The HV market in which HV GaN HEMT can target is estimated at $8 Billion by 2020. The insertion of GaN based power devices in the aforementioned applications is of significant interest to car manufacturers, as well as energy and defense industries, due to the superior material properties of GaN HEMTs. Further, GaN based power devices are considered to be the main candidate to lead future roadmaps of energy efficient products. HEMTs according to the present disclosure are particularly useful in applications that require 1300V blocking capability, for example for the electrification of next generation vehicles. The global requirement for CO2 emission reduction and the drive in the U.S. to reduce dependence on foreign oil are driving the market pull for energy efficient semiconductor devices that are superior in performance to the existing Silicon device which will enable operations at higher temperature that are not addressed by smaller band-gap (Eg=1.1 eV) of silicon based power devices.

(66) The foregoing description of the preferred embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. Similarly, any process steps described might be interchangeable with other steps in order to achieve the same result. The embodiment was chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated.

(67) For example, an embodiment of the present disclosure comprises a HEMT device comprising a M-plane III-Nitride material substrate, a p-doped epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said p-doped epitaxial layer, the recess having a plane wall parallel to a polar plane of the III-Nitride material; a carrier carrying layer formed on said plane wall of the recess; a carrier supply layer formed on said at least one carrier carrying layer, such that a 2DEG region is formed in the carrier carrying layer at the interface with the carrier supply layer along said plane wall of the recess; a doped source region formed at the surface of said p-doped epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region; a gate insulating layer formed on the channel region; and a gate contact layer formed on the gate insulating layer.

(68) For example, the super junction HEMTs illustrated in relation with FIGS. 6A and 7A are normally-off device. However, embodiments of the present disclosure also comprise normally on (depletion mode) HEMTs.

(69) Further, the embodiments disclosed above comprise a super junction HEMT, but the present disclosure relates more generally to any semiconductor device having a superjunction drift region between two active regions, the superjunction drift region comprising at least a P-doped region extending between the two active regions, and a N-doped region extending between the two active regions adjacent the P-doped region, wherein the P-doped region and the N-doped region deplete each other at least partially; and wherein the N-doped region comprises a 2DEG region.

(70) Further, the embodiments disclosed above comprise a super junction vertical HEMT using a 2DEG region as the N-doped region or column of the super junction, but the present disclosure relates more generally to any vertical semiconductor device having a superjunction drift region between two active regions, the superjunction drift region comprising at least a P-doped region extending between the two active regions, and a N-doped region extending between the two active regions adjacent the P-doped region, wherein the P-doped region and the N-doped region deplete each other at least partially; and wherein the N-doped region does not necessarily comprise a 2DEG region. Such embodiments could be illustrated by FIG. 6A, wherein layers 73 and 74 would be replaced by a single N-doped layer grown on wall 70, and wherein substrate 64 would not necessarily be a plane that is not parallel to the C-plane of the III-Nitride material. Such embodiments could alternatively comprise a vertical diode.

(71) It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents. Reference to an element in the singular is not intended to mean one and only one unless explicitly so stated, but rather means one or more. Moreover, no element, component, nor method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the following claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase means for . . . .

(72) It should be understood that the figures illustrated in the attachments, which highlight the functionality and advantages of the present invention, are presented for example purposes only. The architecture of the present invention is sufficiently flexible and configurable, such that it may be utilized (and navigated) in ways other than that shown in the accompanying figures.

(73) Furthermore, the purpose of the foregoing Abstract is to enable the U.S. Patent and Trademark Office and the public generally, and especially the scientists, engineers and practitioners in the art who are not familiar with patent or legal terms or phraseology, to determine quickly from a cursory inspection the nature and essence of the technical disclosure of the application. The Abstract is not intended to be limiting as to the scope of the present invention in any way. It is also to be understood that the steps and processes recited in the claims need not be performed in the order presented.

(74) Also, it is noted that the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function.

(75) The various features of the invention described herein can be implemented in different systems without departing from the invention. It should be noted that the foregoing embodiments are merely examples and are not to be construed as limiting the invention. The description of the embodiments is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.