MAJORITY CURRENT ASSISTED RADIATION DETECTOR DEVICE

Abstract

The invention relates to a majority current assisted detector device, comprising a semiconductor layer of a first conductivity type epitaxially grown on a semiconductor substrate, at least two control regions of the first conductivity type, at least two detection regions of a second conductivity type opposite to the first conductivity type, and a source for generating a majority carrier current in the semiconductor layer between the two control regions, the majority current being associated with an electrical field. The detection regions surround the control regions, thereby forming at least two taps. The device is configured for backside illumination and further comprises a well of the first conductivity type between the two detection regions for insulating the detection regions. The well comprises pixel circuitry elements.

Claims

1. A current-assisted photonic demodulator for detecting an electromagnetic radiation comprising: i. a semiconductor layer on which an impinging electromagnetic radiation can generate pairs of majority and minority carriers therein and which is doped with a dopant of a first conductivity type, ii. at least two control regions (MIX0, MIX1) formed in the semiconductor layer, being doped with a dopant of the first conductivity type; iii. a source, electrically connected to the two control regions, for generating a majority carrier current in the semiconductor layer between the two control regions (MIX0, MIX1), the majority carrier current being associated with an electrical field; iv. at least two detection regions (DET0, DET1) formed in the semiconductor layer and being doped with a dopant of a second conductivity type opposite to the first conductivity type, for forming a junction and collecting generated minority carriers, the minority carriers being directed towards one of the two detection regions (DET0, DET1) under the influence of the electrical field associated with the majority carrier current; v. the two detection regions (DET0, DET1) surround the two control regions (MIX0, respectively, MIX1) in a plane parallel to the semiconductor layer, for forming at least two taps, consisting, each, of a control region and a detection region; vi. the concentration of dopants of the first conductivity type in the semiconductor layer provides an electrical insulation between the detection regions (DET0, DET1) by avoiding leakage of minority carriers from the detection regions (DET0, DET1); the detector device, wherein: the thickness of a semiconductor substrate on which the semiconductor layer is formed is configured for Back Side Illumination; the semiconductor layer is an epitaxial layer; the detector device further comprises a semiconductor region of the first conductivity type formed in the semiconductor layer (40) and located between the two detection regions (DET0, DET1) for insulating the detection regions DET0, DET1), the semiconductor region being a well or a deep well and comprising pixel circuitry elements.

2. The detector device of claim 1, wherein the semiconductor layer is an epitaxial layer p.sup. doped.

3. The detector device of claim 1, wherein the semiconductor layer is an epitaxial layer n.sup. doped.

4. The detector device according to claim 1, wherein the semiconductor layer is formed on a semiconductor substrate doped with a dopant of the first conductivity type, wherein the dopant concentration of the semiconductor substrate is higher than the dopant concentration of the semiconductor layer.

5. The detector device according to claim 1, wherein the detection regions (DET0, DET1), comprises a well doped with a dopant of a conductivity type opposite to the first conductivity type.

6. The detector of claim 5, wherein the detection regions (DET0, DET1) further comprise an ohmic contact formed in the semiconductor layer on top of said well of said opposite conductivity type.

7. The detector device according to claim 1, wherein the control regions (MIX0, MIX1) comprise a well doped with a dopant of first conductivity type.

8. The detector device according to claim 7, wherein the control regions (MIX0, MIX1) further comprise an ohmic contact formed in the semiconductor layer on top of said well of said first conductivity type.

9. The detector device according to claim 7, further comprising a deep well, doped with a dopant of first conductivity type, formed in the semiconductor layer below the well of the control regions (MIX0, MIX1) for providing a strong field between the control regions (MIX0, MIX1).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention shall be better understood in light of the following description and the accompanying drawings.

[0022] FIG. 1 illustrates the basic operational principle of a TOF system;

[0023] FIG. 2A shows a top view of a device according to prior art, FIG. 2B and FIG. 2C show a cross-section of the device of FIG. 2A with two different current conditions;

[0024] FIG. 3 shows a top view of a pixel according to prior art, wherein the control regions surround the detection regions;

[0025] FIG. 4 shows a top view of a first embodiment of a detector device according to the present invention;

[0026] FIG. 5 shows a cross-section of the detector device of FIG. 4 along the line A-A;

[0027] FIG. 6 shows a cross-section of a detector device according to another embodiment of the invention;

[0028] FIG. 7 shows a cross-section of a detector device according to a further embodiment of the invention, wherein the illumination is a Back-Side-Illumination.

[0029] FIG. 8 illustrates the differences between the FSI and BSI embodiments of the invention.

[0030] Advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawing.

DESCRIPTION OF THE INVENTION

[0031] The invention will be explained with reference to p-type epitaxial layer and substrate, but the present invention includes within its scope a complementary device whereby p and n regions become n and p regions respectively. A skilled person can make such modification without departing from the spirit of the invention.

[0032] It should also be understood that the terms n, p, n+, p+, p.sup. and p.sup., n-well, p-well, deep n-well and deep p-well are well known by the one skilled in the art. The terms n, p, n.sup.+, p.sup.+, p.sup. and p.sup. refer to ranges of doping levels in semiconductor materials well known by the one skilled in the art.

[0033] The terms n and p refer to n-doped and p-doped regions, usually arsenic and boron doped regions, respectively. n.sup.+, p.sup.+ refer to highly doped shallow contact regions for NWELL and PWELL respectively. p.sup. refers to lowly doped p type region such as a PWELL and p.sup. refers to very lowly doped p type region close to intrinsic concentration at least 2 orders of magnitude lower than p.sup.. In this case, p.sup. can be an epitaxial highly resistive or high ohmic layer with a resistivity of about 550-10 kOhm.Math.cm. For example, based to this values for p.sup., a p.sup. concentration can correspond to a resistivity of about 15 Ohm.Math.cm-100 Ohm.Math.cm and a p.sup.++ can correspond to a resistivity of about 0.01-1 Ohm.Math.cm.

[0034] Standard semiconductor materials used for CMOS baseline applications, such as logic, are epitaxial layers with a resistivity of 15 Ohm.Math.cm and substrates with a resistivity of 0.001 Ohm.Math.cm.

[0035] For RF and power high voltage applications, the resistivity of epitaxial layer is about 50 Ohm.Math.cm to 120 Ohm.Math.cm with a thickness of 4 m.

[0036] For imagers, such as the CAPD, epitaxial layer are commonly used, with a thickness of 10 to 23 m and with a resistivity of 500 Ohm.Math.cm to 10 k Ohm.Math.cm, and with substrate otherwise known as bulk with a resistivity of 0.01 Ohmc.Math.cm to 1 Ohm.Math.cm.

[0037] The present invention relates to embodiments regarding both Front Side Illumination (FSI) and Back Side Illumination (BSI) devices. Front Side Illumination and Back Side Illumination devices are defined by referring to the location of the circuitry on the chip compared to the impinging light. By FSI, it is meant a device where the light impinges on the same side than the circuitry. With FSI, light falls on the front side of the circuitry, and passes through the readout circuitry and interconnects before it is collected in the photodetector.

[0038] On the contrary, by BSI, it is meant a device where the light impinges on the other side, where the circuitry is not located. The main idea behind the fact of using BSI structure is that no light is lost while passing through the circuitry.

[0039] FIG. 3 shows a top view of a first embodiment of a detector device according to the present invention. In FIG. 3, the detector device comprises four taps, formed in a semiconductor layer 40. Each tap comprises a control region MIX0, MIX1 surrounded by a detection region DET0, DET1, respectively. The detection regions may be rectangular shaped as represented in FIG. 3, but not only. A source 41 injects current in control region MIX0 and drains current in control region MIX1. This source generates a majority carrier current in the semiconductor layer 40 between the control regions MIX0, MIX1, the majority current being associated with an electrical field. In the configuration presented in FIG. 3, the majority carriers are holes h.sup.+ and the minority carriers are electrons e.sup.. Line A-A in FIG. 4 shows where the cross-sections are made for FIG. 5.

[0040] In FIG. 4, the detector device is depicted as a square. It is important to mention that the control mix electrode is an island encapsulated by the detector electrode ring so that another potential geometry can advantageously be implemented such as a circle or a polygone but this is not limited thereto.

[0041] In FIG. 5, the majority hole current is shown by solid lines and its direction is represented by arrows. When an electromagnetic radiation 43, e.g. photons, impinges the layer 40, some electron-hole pairs are generated in the layer 40. The electron-hole pairs are separated by the electrical field that is present and which is associated with the flowing majority hole current. The minority carriers 42 move towards the detection region which is closer to the region where the majority carriers are drained, i.e. DET0 here. DET1 could also be activated according to the potentials applied on MIX0 and MIX1. Movements of electrons are due to drift based on the present electrical field associated with the flowing majority current.

[0042] The control regions MIX0, MIX1 comprise at least a PWELL 28, 31. They may comprise three distinct regions, a p.sup.+, a PWELL and a deep PWELL. A highly doped semiconductor contact 27, 30, e.g. a p.sup.+ contact, may be formed above the PWELL 28, 31. The fact of highly doping this contact creates an ohmic contact used for injecting the majority current via the source 41. A deep PWELL 29, 32 may also be provided below the PWELL. The purpose of the deep PWELL is to extend the controlling electrode deeper into the layer 40 so that it provides a good control of the epitaxial layer potential and enhances the lateral field between the two MIX contacts.

[0043] The detection regions DET0, DET1 may comprise at least a NWELL 24, 26 forming a p-n junction with the semiconductor layer 40 for collecting generated minority carriers 42. The detection regions DET0, DET1 may comprise, but are not limited to, an n-type region that can be any combination of the following: N+ implant, NWELL or deep NWELL creating a pn junction photodetector such as N+/PSUB, NWELL/PSUB, DNWELL/PSUB photodiode with the semiconductor layer 40 for collecting generated minority carriers 42. The detection regions DET0, DET1 may also comprise a n+ contact 23, 25 formed above the NWELL 24, 26 for creating an ohmic contact with the circuitry 21, 22 and enabling for instance the reading of the minority carriers via a readout circuitry. The NWELL 24, 26 should be located close to the hole current source MIX0, MIX1 in order to increase the chance and the speed with which the electrons will diffuse into the NWELL 24, 26 through the detecting pn-junction and thus to increase the sensitivity of the detector. The NWELL should be able to capture the photo generated electrons captured by the lateral field between the two MIX electrodes and drifted towards the tap with the higher bias.

[0044] In prior art, as illustrated by FIG. 3, the p-type control regions 6, 8 surround the n-type detection region 5, 7 and are formed in a p-type layer. This means that the detection regions 5, 7 are electrically insulated by the surrounding control regions 6, 8 and the captured minority carriers cannot leak. Short-circuits cannot be formed between the detection regions. In the FSI (Front Side Illumination), the wafer material used for the CAPD implementation is usually an epitaxial layer doped p.sup., where the photodiodes and pixel circuitry is build. This p.sup. layer is lightly doped by boron to obtain a resistivity between 500 Ohm.Math.cm and 10 k Ohmc.Math.cm. A substrate can also be used. It usually an highly boron doped material p.sup.++ with a resistivity of 0.01-1 Ohm.Math.cm, on which the epitaxial silicon layer is built. Usually, for Infra Red (IR) application (850 nm), the substrate or wafer has an overall thickness of 750 m out of which the top 23 m is the high resistive or lowly doped epitaxial silicon layer where the photogenerated minority carriers (e) are created.

[0045] The thickness of the epitaxy layer is tuned to comply with the absorption of IR light in silicon which is in the order of 15-20 m. The minority carriers should be generated in the epitaxial layer and not in the substrate so that they can be collected by the detectors or the cathodes of the photodiode junctions. The recombination inside the highly doped substrate has to be avoided.

[0046] In the present invention, the location of p-type control regions MIX0, MIX1 and n-type detection regions DET0, DET1 is changed and the detection regions DET0, DET1 surround the control regions MIX0, MIX1. In the present invention, the control regions MIX0, MIX1 are islands encapsulated by the detection regions. This change enables the distance between the nodes to reduce without compromising on the power consumption by using the NWELL detector regions as isolation between the two MIX electrodes. Hence, the resistance between the two MIX contacts remains high and the pixel size is reduced. By interchanging the position of control and detection regions, the n-type detection regions DET0, DET1 are now closer, which increase the chance of short-circuits and leakage of captured minority carriers. The present invention proposes to adapt the conductivity of the semiconductor layer 40 in order to provide an electrical insulation between the detection regions DET0, DET1 for avoiding leakage of minority carriers. A resistivity of at least 50 Ohm.Math.cm allows sufficient isolation between the detection NWELL without significant impact on the power consumption as the PWELL MIX regions are encapsulated by the NWELL rings. The conductivity of the semiconductor layer 40 can be adapted for example by lightly doping the layer 40. The layer 40 may for example be doped p.sup. instead of p.sup. in the prior art. The fact of doping slightly more the layer 40 enables to increase slightly the concentration of holes in the layer and, thus, to decrease slightly the concentration of electrons in the layer 40. With a less resistive layer, the electron captured in the detection regions DET0, DET1 cannot leak anymore. The region around and between the detection regions DET0, DET1 should provide such an insulation.

[0047] The layer 40 may also comprise a semiconductor region, formed in the semiconductor layer and located between the detection regions. The layer 40 can contain a p-type implanted semiconductor region 45 that can be a shallow p+ layer, PWELL or deep PWELL between the detection elements DET0, DET1 to electrically isolate the two taps. A layer of shallow p+ or deeper PWELL can also be implemented between the NWELL nodes to isolate the two taps. This embodiment is not represented for the FSI case, but only BSI case, in FIG. 6, but it should be understood that this embodiment can be implemented in both FSI and BSI cases.

[0048] In a further embodiment presented in FIG. 6, the layer 40 may be formed on a substrate 44. The concentration of dopants in the substrate 44 may be higher than the one of the layer 40. For instance the substrate 44 may be a p.sup.++ layer whereas the layer 40 may be a p.sup. layer. This means that if the initial substrate 44 on which the device is built is p.sup.++, then a layer 40 lightly doped p.sup. should be formed above, prior building the control and detection regions MIX0, MIX1, DET0 and DET1. The conductivity of layer 40 between the detection regions DET0, DET1 should be adapted for providing electrical insulation and avoiding a leakage of minority carriers.

[0049] In the embodiments illustrated by FIGS. 5 and 6, the illumination 43 is a Front-Side-Illumination (FSI), i.e. the light impinges on the layer 40 on the same side as the circuitry 22, 21.

[0050] In a further embodiment presented in FIG. 7, the illumination 46 is a Back-Side-Illumination (BSI) and impinges on the substrate 44 on the other side of the chip.

[0051] In the BSI case, the epitaxial layer 40 is thinned down to a range of, for example, 5-100 um (preferably 5 to 30 um) depending on the illumination wavelength of the targeted application. The highly doped substrate layer 44, is replaced by a thin layer in the order of 1-3 um depending on the process flow selected. The doping of this shallow implanted layer 44 is of the same order of magnitude as the original SUB p++ layer 44 in the FSI case.

[0052] In the BSI case, the same wafer material is used so the same nomenclature for lowly doped p.sup., epitaxial silicon and highly doped p.sup.++ substrate can be applied.

[0053] The difference between the BSI and the FSI is that, in the BSI case, the majority of the highly doped p.sup.++ substrate is consumed by a back grinding step of the BSI processing. The backside of the wafer becomes the front side i.e. the optical area where the light is impinging. The majority of the substrate is back grinded to expose the lowly doped or highly resistivity epitaxy.

[0054] This change from FSI to BSI enables to place circuitry elements inside region 45 in between the taps for reducing the total size of the pixel 20, without affecting the fill factor of the device. The function of region 45 is to provide electrical isolation between the detectors and may contain circuitry. A shallow p+, PWELL or deep PWELL implant can be applied in region 45 located between the DET0, DET1 areas to isolate the two taps. Region 45 can be an electrically floating island or grounded in the embodiment of the invention where pixel circuitry is buried within. In case a PWELL or deep PWELL implants are applied, region 45 can accommodate circuitry elements (PIXEL circuitry in FIG. 8) and can be referred to as the circuit element region of the pixel.

[0055] In such a case, the resistivity of the p.sup. 40 layer can be a standard CMOS baseline doping; for instance 15 ohm.Math.cm. A p.sup. epitaxy layer of 550 Ohm.Math.cm to 10 k Ohm.Math.cm can also be used in conjunction with region 45 to isolate the two taps. The fact of implementing a Back-Side-Illumination enables also a more efficient light collection. The resulting images have less digital noise, and low-light performance can be improved.

[0056] In FIG. 6, the detector device is presented with a layer 40 and a substrate 44. The device could also be implemented with only one layer 40, as in FIG. 5, if the conductivity of the layer 40 is adapted for providing electrical insulation between the detection regions DET0 and DET1.

[0057] In FIG. 8, the differences between the devices for Front-Side-Illumination (Scheme A) and Back-Side-Illumination (Scheme B) are better represented. In the BSI case, the epitaxial layer is thinned down to a depth depending on the illumination wavelength of the targeted application, for example, 5-100 m and preferably 5 to 30 m for Infra-red illumination wavelength. The highly doped substrate layer 44 of FIG. 6 and FIG. 7 is replaced by a thin layer in the order of 1-3 m depending on the process flow selected. The doping of this shallow implanted layer 44 is of the same order of magnitude as the original SUB p++ layer 44 in the FSI case of FIG. 7. It should be understood that, in the FSI case, semiconductor regions 45 are not arranged for receiving pixel circuitry elements.