ISOLATED WELL CONTACT IN SEMICONDUCTOR DEVICES

Abstract

An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

Claims

1. An integrated circuit, comprising: a substrate of a first conductivity type: an isolated well within the substrate wherein the isolated well is of a second conductivity type opposite the first conductivity type; a device within the isolated well wherein the device contains a device diffusion of the first conductivity type; a well contact diffusion within the isolated well wherein the well contact diffusion is of the second conductivity type; and an isolation transistor gate over the isolated well between the device diffusion and the well contact diffusion to isolate the well contact diffusion from the device diffusion.

2. The integrated circuit of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

3. The integrated circuit of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

4. The integrated circuit of claim 1, wherein the device is a transistor and the device diffusion is a source or drain region.

5. The integrated circuit of claim 1, wherein the well contact diffusion is self-aligned to a first side of an isolation transistor gate and wherein the device diffusion is self-aligned to a second side of the isolation transistor gate.

6. The integrated circuit of claim 1, wherein an isolation transistor gate is electrically floating.

7. The integrated circuit of claim 1, wherein an isolation transistor gate is coupled to a fixed voltage node.

8. The integrated circuit of claim 1, wherein the isolation transistor gate is electrically connected to the isolated well.

9. An integrated circuit comprising: an isolated well of a second conductivity type in a substrate of a first conductivity type; a transistor gate dielectric on the isolated well and on the substrate; an isolation structure over the isolated well and a gate of a transistor over the isolated well, the gate comprising a transistor gate material and the isolation structure comprising the transistor gate material; dielectric sidewalls on the isolation structure and on the gate of the transistor; source and drain diffusions of the first conductivity type in the isolated well self-aligned to the dielectric sidewall spacers on the gate of the transistor, wherein one of the source and drain diffusions is self-aligned to the dielectric sidewall spacer on a first side of the isolation structure; and a well contact diffusion of the second conductivity type in the isolated well adjacent a second side of the isolation structure.

10. The integrated circuit of claim 9, wherein the first conductivity type is p-type and the second conductivity type is n-type.

11. The integrated circuit of claim 9, wherein the first conductivity type is n-type and the second conductivity type is p-type.

12. The integrated circuit of claim 9, further comprising: a premetal dielectric over the substrate; a contact plug through the premetal dielectric to the isolation structure; an interconnect geometry electrically connected to the contact plug, wherein the interconnect geometry is coupled to a fixed voltage node.

13. The integrated circuit of claim 12, wherein the isolated well is also coupled to the fixed voltage node.

14. The integrated circuit of claim 12, wherein the fixed voltage node is a ground terminal.

15. An integrated circuit comprising: an isolated well with a second conductivity type in a substrate with a first conductivity type; an isolation transistor gate adjacent to a well contact region within the isolated well; dielectric sidewall spacers on sidewalls of the isolation transistor gate; a device diffusion of the first conductivity type in the isolated well region adjacent to a first side of the isolation transistor gate; a well contact diffusion of the second conductivity type in the isolated well region adjacent to a second side of the isolation transistor gate.

16. The integrated circuit of claim 15, wherein the first conductivity type is p-type and the second conductivity type is n-type.

17. The integrated circuit of claim 15, wherein the first conductivity type is n-type and the second conductivity type is p-type.

18. The integrated circuit of claim 15, wherein the device is a transistor device and wherein a gate of the transistor device comprises the same material as the isolation transistor gate.

19. The integrated circuit of claim 15, wherein the well contact diffusion is self-aligned to the dielectric sidewall spacer on the second side of an isolation transistor gate and wherein the device diffusion implant is self-aligned to the dielectric sidewall spacer on the first side of the isolation transistor gate.

Description

DESCRIPTION OF THE VIEWS OF THE DRAWINGS

[0009] FIG. 1 (Prior art) is a cross-section of an integrated circuit with a well contact isolated from a device diffusion by shallow trench isolation.

[0010] FIG. 2 is a cross-section of an integrated circuit with a well contact isolated from device diffusion by an isolation transistor gate.

[0011] FIG. 3A through FIG. 3G are cross sections of the integrated circuit of FIG. 2 depicted in successive stages of fabrication.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0012] The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.

[0013] An embodiment integrated circuit with an improved isolated well contact that significantly reduces voltage drop when high bias is applied to the isolated well is illustrated in FIG. 2. Similar to FIG. 1, the transistor 110 is formed in an isolated well 104 of a second conductivity type (e.g., n-type) in substrate 102 of a first conductivity type (e.g., p-type). Transistor 110 includes a gate and source and drain regions 154. Shallow trench isolation (STI) geometries 108 electrically isolate the well 104 from the substrate 102 by blocking silicide 112 from shorting the well contact diffusion 146 of the second conductivity type (e.g., n-type) to the substrate contact diffusion 156 of the first conductivity type (e.g., p-type). Contact plugs 116 couple diffusions 156, 154, and 146 in the substrate 102 and well 104 to the first level of interconnect 126.

[0014] Instead of STI geometries 106 (FIG. 1) separating the isolated well contact diffusions 146 from the source and drain diffusions 154 of the transistor 110, isolation transistor gates 202 and 204 are employed. The isolation transistor gates, 202 and 204, block silicide 112 from shorting the well contact diffusions 146, to the transistor source and drain diffusions 154. The isolation transistor gates, 202 and 204, may be left electrically floating (unconnected to any other device elements) or may be tied to a fixed voltage node such as a ground terminal or the well 104 potential.

[0015] For purposes of illustration, the isolation transistor gates, 202 and 204, isolate the well contact diffusions 146 from the source and drain diffusions, 154, of a MOS transistor. Optionally the isolation transistor gates, 202 and 204, may isolate the well contact diffusions 146 from other types of devices formed in the isolated well 104 such as bipolar transistors, resistors, capacitors, memory cells, etc. Two well contact diffusions 146 are used for illustration but any number of well contact diffusions may be used.

[0016] As shown in FIG. 2, the cross sectional area 214 of the isolated well 104 under the isolation transistor gates, 202 and 204 is significantly larger than the cross sectional area 114 (FIG. 1) under the STI isolation. The increased cross sectional area 214 significantly reduces current crowding that causes the voltage drop when high bias is applied to the isolated well 104 and the device 110 draws significant current.

[0017] The major steps in an integrated circuit process flow that forms an integrated circuit with the improved isolated well contact is illustrated in the cross sections in FIGS. 3A-3G. This process flow provides an improved isolated well contact with no additional processing steps and no additional cost.

[0018] FIG. 3A shows a partially processed integrated circuit in which an isolated well 104 is formed in a single crystal substrate 102 of opposite conductivity type. Shallow trench isolation (STI) geometries 108 prevent silicide from shorting the isolated well 104 to the substrate. For purposes of illustration an isolated n-type well 104 is formed in a p-type substrate 102. An isolated p-type well formed in an n-type substrate could also be used.

[0019] Referring now to FIG. 3B, a transistor gate dielectric 107 is formed on the n-type well 104 and the substrate 102 and gate material 109 such as polysilicon is deposited on the transistor gate dielectric 107. A transistor gate photoresist pattern with a transistor gate photo resist geometry 111 to form the gate of the transistor and with isolation transistor gate photo resist geometries 113 to form the isolation transistor gates 202 and 204 is formed on the gate material 109.

[0020] The gate material 109 is etched using resist geometries 111 and 113 to form the gate of the transistor 110 and to form the isolation transistor gates 202 and 204. The resist geometries 111 and 113 are then removed. The resulting gate of transistor 110 and isolation transistor gates 202 and 204 are shown in FIG. 3C.

[0021] In FIG. 3D a PMOS extension photo resist pattern 130 is formed on the integrated circuit and p-type dopant 132 is implanted to form the source and drain extensions 134 self-aligned to the gate of the PMOS transistor 110.

[0022] Sidewall spacers 140 are formed on the gate of the PMOS transistor 110 and on isolation transistor gates, 202 and 204, as shown in FIG. 3E. The sidewall spacers 140 may be formed of a dielectric material such as silicon dioxide and silicon nitride. A NMOS transistor source and drain (NSD) photo resist pattern 142 is formed on the integrated circuit and n-type dopant 144 is implanted to form the source and drains of NMOS transistors elsewhere in the circuit and to form contact diffusions 146 to the n-type well 104. The NSD pattern partially covers the isolation transistor gates 202 and 204 and covers the source and drain extensions 134 adjacent to the gate of the PMOS transistor 110. The NSD dopant is implanted to form well diffusions 146 self-aligned to the dielectric sidewall spacer 140 on the isolation transistor gates 202 and 204.

[0023] In FIG. 3F a PMOS source and drain (PSD) photo resist pattern 150 is formed on the integrated circuit and p-type dopant 152 is implanted self-aligned to the sidewall spacers 140 on the gate of the PMOS transistor 110 to form the PMOS transistor source and drain diffusions 154. The p-type dopant 152 is also implanted into the p-type substrate 102 to form the p-type substrate contact diffusion 156.

[0024] As illustrated in FIG. 3G, silicide 112 is formed in the usual manner on exposed silicon surfaces: on top of the gate of the PMOS transistor 110, on top of the isolation transistor gates 202 and 204, on top of the p-type substrate contact 156, on top of the nwell 104 contact 146, and on top of the PMOS transistor source and drain diffusions 154. The isolation transistor gates block silicide 112 from shorting the transistor source and drain diffusions 154 to the nwell contact diffusions 146.

[0025] Additional processing to form the premetal dielectric (PMD) 120 (FIG. 2), the contact plugs 116, and the first level of interconnect 126 may be performed on the integrated circuit in FIG. 3G to form the integrated circuit shown in FIG. 2. Additional processing may be performed on the integrated circuit in FIG. 2 to add additional levels of dielectric and interconnect to complete the integrated circuit.

[0026] The embodiment improved isolated well contact provides a lower resistance path between the well contact and devices in the well. The lower resistance path reduces the voltage drop between the isolated well contact and devices formed in the well thus avoiding degraded device performance.

[0027] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.