SEMICONDUCTOR STRUCTURE

Abstract

A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from Al.sub.xGa.sub.1-xN (0<x<1) while the stress control layer is made from Al.sub.xIn.sub.yGa.sub.1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

Claims

1. A semiconductor structure comprising: a first conductivity type semiconductor layer; a light emitting layer comprises a multiple quantum well (MQW) structure, wherein the MQW structure comprises a plurality of well layers and a plurality of barrier layers stacked alternately; a super lattice layer disposed between the light emitting layer and the first conductivity type semiconductor layer; a second conductivity type semiconductor layer; an aluminum-containing GaN based carrier blocking layer disposed between the light emitting layer and the second conductivity type semiconductor layer; and an indium-containing GaN based stress control layer disposed between the light emitting layer and the aluminum-containing GaN based carrier blocking layer, wherein a level of indium in the indium-containing GaN based stress control layer is equal to or smaller than a level of indium in well layers of the MQW structure.

2. The semiconductor structure as claimed in claim 1, wherein the indium-containing GaN based stress control layer further contains aluminum.

3. The semiconductor structure as claimed in claim 1, wherein the indium-containing GaN based stress control layer is doped with a first conductivity type dopant and a second conductivity type dopant.

4. The semiconductor structure as claimed in claim 3, wherein both doped concentrations of the first conductivity type dopant and the second conductivity type dopant in the indium-containing GaN based stress control layer are smaller than 10.sup.19 cm.sup.3.

5. The semiconductor structure as claimed in claim 3, wherein the first conductivity type dopant is silicon and the second conductivity type dopant is magnesium.

6. The semiconductor structure as claimed in claim 1, further comprising an aluminum-containing GaN based carrier blocking layer disposed between the first conductivity type semiconductor layer and the super lattice layer.

7. The semiconductor structure as claimed in claim 1, wherein the second conductivity type semiconductor layer is doped with a second conductivity type dopant at a concentration higher than 510.sup.19 cm.sup.3.

8. A semiconductor structure comprising: a first conductivity type semiconductor layer; a light emitting layer comprises a multiple quantum well (MQW) structure, wherein the MQW structure comprises a plurality of well layers and a plurality of barrier layers stacked alternately; a second conductivity type semiconductor layer; a GaN based carrier blocking layer containing aluminum, disposed between the light emitting layer and the second conductivity type semiconductor layer; and a GaN based stress control layer containing indium and aluminum, disposed between the light emitting layer and the GaN based carrier blocking layer, wherein a level of aluminum in the GaN based stress control layer is smaller than or equal to a level of aluminum in the GaN based carrier blocking layer.

9. The semiconductor structure as claimed in claim 8, wherein a level of indium in the GaN based stress control layer is equal to or smaller than a level of indium in well layers of the MQW structure.

10. The semiconductor structure as claimed in claim 8, wherein the GaN based stress control layer is doped with a first conductivity type dopant and a second conductivity type dopant.

11. The semiconductor structure as claimed in claim 8, further comprising a super lattice layer disposed between the light emitting layer and the first conductivity type semiconductor layer.

12. The semiconductor structure as claimed in claim 11, further comprising an aluminum-containing GaN based carrier blocking layer disposed between the first conductivity type semiconductor layer and the super lattice layer.

13. The semiconductor structure as claimed in claim 10, wherein the first conductivity type dopant is silicon and the second conductivity type dopant is magnesium, and both doped concentrations of the first conductivity type dopant and the second conductivity type dopant in the GaN based stress control layer are smaller than 10.sup.19 cm.sup.3.

14. The semiconductor structure as claimed in claim 8, wherein the second conductivity type semiconductor layer is doped with a second conductivity type dopant at a concentration higher than 510.sup.19 cm.sup.3.

15. The semiconductor structure as claimed in claim 8, further comprising an aluminum-containing GaN based carrier blocking layer disposed between the first conductivity type semiconductor layer and the light emitting layer.

16. A semiconductor structure comprising: a first conductivity type semiconductor layer; a light emitting layer comprises a multiple quantum well (MQW) structure, wherein the MQW structure comprises a plurality of well layers and a plurality of barrier layers stacked alternately; a super lattice layer disposed between the light emitting layer and the first conductivity type semiconductor layer; a second conductivity type semiconductor layer; a GaN based carrier blocking layer containing aluminum, disposed between the light emitting layer and the second conductivity type semiconductor layer; and a GaN based stress control layer containing indium and aluminum, disposed between the light emitting layer and the GaN based carrier blocking layer, wherein a level of aluminum in the GaN based stress control layer is smaller than or equal to a level of aluminum in the GaN based carrier blocking layer, wherein a level of indium in the GaN based stress control layer is equal to or smaller than a level of indium in well layers of the MQW structure.

17. The semiconductor structure as claimed in claim 16, wherein the GaN based stress control layer is doped with a first conductivity type dopant and a second conductivity type dopant.

18. The semiconductor structure as claimed in claim 16, further comprising an aluminum-containing GaN based carrier blocking layer disposed between the first conductivity type semiconductor layer and the super lattice layer.

19. The semiconductor structure as claimed in claim 17, wherein the first conductivity type dopant is silicon and the second conductivity type dopant is magnesium, and both doped concentrations of the first conductivity type dopant and the second conductivity type dopant in the GaN based stress control layer are smaller than 10.sup.19 cm.sup.3.

20. The semiconductor structure as claimed in claim 16, wherein the second conductivity type semiconductor layer is doped with a second conductivity type dopant at a concentration higher than 510.sup.19 cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings, wherein

[0016] FIG. 1 is a schematic drawing showing a cross section of an embodiment of a nitride semiconductor structure according to the present invention;

[0017] FIG. 2 is a schematic drawing showing a cross section of an embodiment of a semiconductor light emitting device including a nitride semiconductor structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0018] In the following embodiments, when it is mentioned that a layer of something (or membrane) or a structure is disposed over or under a substrate, another layer of something (or membrane), or another structure, that means the two structures, the layers of something (or membranes), the layer of something and the substrate, or the structure and the substrate can be directly or indirectly connected. The indirect connection means there is at least one intermediate layer disposed therebetween.

[0019] Referring to FIG. 1, a nitride semiconductor structure of the present invention mainly includes a light emitting layer 5, a p-type carrier blocking layer 7 and a stress control layer 6 disposed between the light emitting layer 5 and the p-type carrier blocking layer 7. The light emitting layer 5 is in a multiple quantum well (MQW) having a plurality of well layers 51 and barrier layers 52 interleaved with each other. One well layer 51 is interposed between the two barrier layers 52. The p-type carrier blocking layer 7 is made from Al.sub.xGa.sub.1-xN (0<x<1) while the stress control layer 6 is made from Al.sub.xIn.sub.yGa.sub.1-x-yN (0<x<1, 0<y<1, 0<x+y<1).

[0020] In the above embodiment, the barrier layer 52 is doped with an n-type dopant at a concentration ranging from 10.sup.1610.sup.18 cm.sup.3. A p-type semiconductor layer 8 is disposed over the p-type carrier blocking layer 7 and is doped with a p-type dopant at a concentration higher than 510.sup.19 cm.sup.3. The thickness of the p-type semiconductor layer 8 is smaller than 30 nm. An n-type semiconductor layer 3 is disposed between the light emitting layer 5 and a substrate 1. Moreover, in this embodiment, there is an n-type carrier blocking layer 4 disposed between the light emitting layer 5 and the n-type semiconductor layer 3. The n-type carrier blocking layer 4 is made from Al.sub.xGa.sub.1-xN (0<x<1). A super lattice layer 9 is disposed between the light emitting layer 5 and the n-type carrier blocking layer 4 to reduce lattice mismatch and dislocation density between the light emitting layer 5 and the n-type carrier blocking layer 4.

[0021] In this embodiment, the stress control layer 6 is doped with a p-type dopant at a concentration smaller than 10.sup.19 cm.sup.3 and an n-type dopant at a concentration smaller than 10.sup.19 cm.sup.3. The preferred p-type dopant is magnesium while the optimal n-type dopant is silicon. The p-type dopant is used as a receptor to increase the effective hole concentration while the n-type dopant is a donor for improving crystallization of the gallium nitride (GaN) based semiconductor layers. By doping the p-type dopant and the n-type dopant at the same time, good electro-optical properties are produced. The thickness of the above stress control layer 6 is ranging from 2 nm to 15 nm. The preferred thickness of the stress control layer 6 is smaller than the thickness of the well layer 51 of the multiple quantum well (MQW) structure.

[0022] While in use, the n-type semiconductor layer 3 is made from Si-doped gallium nitride while materials for the p-type semiconductor layer 8 are Mg-doped gallium nitride. The preferred MQW structure of the light emitting layer 5 is composed of InGaN well layers 51 and GaN barrier layers 52. As to the stress control layer 6 made from Al.sub.xIn.sub.yGa.sub.1-x-yN, it is located between the p-type carrier blocking layer 7 and the light emitting layer 5.

[0023] By control of the amount of indium in the stress control layer 6 to make the amount of indium in the stress control layer 6 become equal or lower than the well layers 51 of the MQW structure, the stress control layer 6 whose energy gap is larger than the well layer 51 is formed. Thus carriers are confined in the well layers 51 of the MQW structure to increase electron-hole recombination rate and further improve internal quantum efficiency. Therefore the light emitting efficiency of the semiconductor light emitting device is significantly improved.

[0024] In addition, the Al.sub.xIn.sub.yGa.sub.1-x-yN stress control layer 6 of the present invention is not only used as a buffer layer between the p-type carrier blocking layer 7 and the light emitting layer 5, it's also able to improve crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer 7 and the light emitting layer 5 as well as reduce effects of compressive stress on the well layer 51 because that the band gap of InGaN containing indium is smaller than that of GaN while the band gap of AlGaN containing aluminum is larger than that of GaN. Thus electron and hole accumulation occurs in the well layer 51. Both electrons and holes are confined in adjacent well layer 51 so as to increase the internal quantum efficiency. Furthermore, the reduction of the compressive stress also enhances interface properties between the adjacent GaN barrier layer 52 and the InGaN well layer 51 and improves carrier loss at the interface. Thus the internal quantum efficiency is increased.

[0025] The nitride semiconductor structure is applied to semiconductor light emitting devices. Referring to FIG. 2, a cross section of a semiconductor light emitting device including the nitride semiconductor structure of an embodiment according to the present invention is revealed. The semiconductor light emitting device includes at least: a substrate 1, an n-type semiconductor layer 3 disposed over the substrate 1 and made from Si-doped GaN, a light emitting layer 5 disposed over the n-type semiconductor layer 3 and having a multiple quantum well structure, a stress control layer 6 disposed over the light emitting layer 5, a p-type carrier blocking layer 7 disposed over the stress control layer 6 and made from Al.sub.xGa.sub.1-xN (0<x<1), a p-type semiconductor layer 8 disposed over the p-type carrier blocking layer 7 and made from Mg-doped GaN, an n-type electrode 31 disposed on and in ohmic contact with the n-type semiconductor layer 3, and a p-type electrode 81 disposed at and in ohmic contact with the p-type semiconductor layer 8.

[0026] The multiple quantum well structure of the light emitting layer is formed by a plurality of well layers 51 and a plurality of barrier layers 52 stacked alternately. Each well layer 51 is disposed between two barrier layers 52. The well layer 51 and the barrier layer 52 are respectively made from InGaN and GaN. Thereby electrons and holes are more easily to be confined in the well layer 51 so that the electron-hole recombination rate increased and the internal quantum efficiency is improved.

[0027] The stress control layer 6 is made from Al.sub.xIn.sub.yGa.sub.1-x-yN while x and y satisfy following conditions: 0<x<1, 0<y<1, and 0<x+y<1. In this embodiment, the stress control layer 6 is doped with a p-type dopant (Mg is preferred) at a concentration smaller than 10.sup.19 cm.sup.3 and an n-type dopant (Si is preferred) at a concentration smaller than 10.sup.19 cm.sup.3. The thickness of the stress control layer 6 is ranging from 2 nm to 15 nm and this thickness is smaller than the thickness of the well layer 51. Moreover, aluminum ions in the p-type carrier blocking layer 7 are going to diffuse into the stress control layer 6 so that the amount of indium in the stress control layer 6 is equal to or smaller than the well layer 51 of the MQW structure. Thus the stress control layer 6 whose band gap is larger than that of the well layer 51 is formed. Therefore carriers are restricted in the well layers 51 of the MQW structure to increase the electron-hole recombination rate and improve the internal quantum efficiency.

[0028] The n-type electrode 31 and the p-type electrode 81 are used together to provide electric power and are made from (but not limited to) the following materials: titanium, aluminum, gold, chromium, nickel, platinum, and their alloys. The manufacturing processes are well-known to people skilled in the art.

[0029] Moreover, the semiconductor light emitting device further includes an n-type carrier blocking layer 4 and a buffer layer 2. The n-type carrier blocking layer 4 is disposed between the light emitting layer 5 and the n-type semiconductor layer 3 while the buffer layer 2 is disposed between the n-type semiconductor layer 3 and the substrate 1. The n-type carrier blocking layer 4 is made from material Al.sub.xGa.sub.1-xN (0<x<1) so that carriers are confined in the well layers 51. Thus the electron-hole recombination rate is increased, the light emitting efficiency is improved, and the brightness of the semiconductor light emitting device is further enhanced. The buffer layer 2 is made from Al.sub.xGa.sub.1-xN (0<x<1) and is used for solving the dislocation problem caused by lattice mismatch between the substrate 1 and the n-type semiconductor layer 3.

[0030] In summary, according to the above embodiments, the Al.sub.xIn.sub.yGa.sub.1-x-yN stress control layer 6 of the semiconductor light emitting device not only solves the problem of crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer 7 and the light emitting layer 5 for increasing the yield rate. It also reduces effects of compressive stress on the InGaN well layer 51 caused by material differences. Thus electrons and holes accumulate and confined more effectively in the well layer 51 so as to increase the internal quantum efficiency. Moreover, the reduction of the compressive stress also enhances interface properties between the adjacent barrier layers 52 and the well layers 51 and improves carrier loss at the interface. Therefore the internal quantum efficiency is increased and the semiconductor light emitting device gets a better light emitting efficiency.

[0031] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and representative devices shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.