METHOD OF FORMING A COMPOSITE SUBSTRATE

Abstract

In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a.sub.substrate. The III-nitride layer has a bulk lattice constant a.sub.layer. In some embodiments, [(|a.sub.substratea.sub.layer|)/a.sub.substrate]*100% is no more than 1%.

Claims

1. A method comprising: growing a III-nitride layer with a bulk lattice constant a.sub.layer on a non-III-nitride growth substrate with an in-plane lattice constant a.sub.substrate such that [(|a.sub.substratea.sub.layer|)/a.sub.substrate]*100% is no more than 1%; providing a composite substrate comprising the III-nitride layer bonded to a host substrate; and growing a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region on the III-nitride layer of the composite substrate.

2. The method of claim 1 wherein growing a III-nitride layer comprises growing the III-nitride layer such that a group V face of the III-nitride layer is the growth surface and a group III face of the III-nitride layer is disposed on the non-III-nitride growth substrate.

3. The method of claim 2 wherein growing a semiconductor structure comprises growing the semiconductor structure on the group III face of the III-nitride layer.

4. The method of claim 1 wherein the non-III-nitride growth substrate is ScAlMgO.sub.4 and the III-nitride layer is InGaN.

5. The method of claim 1 wherein the non-III-nitride growth substrate is RAO.sub.3(MO).sub.n, where R is selected from Sc, In, Y, and the lanthanides; A is selected from Fe (III), Ga, and Al; M is selected from Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer 1.

6. The method of claim 1 wherein the III-nitride layer is one of InGaN and AlInGaN.

7. The method of claim 1 wherein the III-nitride layer is In.sub.xGa.sub.1-xN, where 0.06x0.48.

8. The method of claim 1 wherein the composite substrate comprises a non-III-nitride bonding layer disposed between the III-nitride layer and the host substrate.

9. The method of claim 8 wherein the III-nitride layer is InGaN, the bonding layer is SiO.sub.x, and the host substrate is sapphire.

10. The method of claim 1 further comprising removing a portion of the composite substrate after growing a semiconductor structure.

11. The method of claim 1 further comprising forming a metal n-contact on the n-type region and a metal p-contact on the p-type region, the metal n- and p-contacts formed on a surface of the semiconductor structure opposite the composite substrate.

12. The method of claim 1 further comprising forming a metal n-contact on the n-type region and a metal p-contact on the p-type region, the metal n- and p-contacts formed on opposite surfaces of the semiconductor structure.

13. The method of claim 1 wherein growing a III-nitride layer comprises forming a zone of weakness in the growth substrate or at an interface between the growth substrate and the III-nitride layer.

14. The method of claim 13 wherein the zone of weakness comprises a region implanted with one of H atoms and N atoms.

15. The method of claim 13 wherein the zone of weakness comprises a plurality of micron scale crystal defects or voids created by irradiation with focused laser beams.

16. The method of claim 1 further comprising positioning a wavelength converting material in a path of light emitted by the light emitting layer.

17. The method of claim 15 wherein the wavelength converting material comprises quantum dots.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 illustrates a prior art composite substrate.

[0013] FIG. 2 illustrates a III-nitride seed layer grown on a substrate.

[0014] FIG. 3 illustrates a III-nitride seed layer bonded to a host substrate.

[0015] FIG. 4 illustrates a composite substrate including a III-nitride seed layer.

[0016] FIG. 5 illustrates a III-nitride device structure grown on the composite substrate of FIG. 4.

[0017] FIG. 6 illustrates a thin film flip chip light emitting device.

[0018] FIG. 7 illustrates a vertical light emitting device.

DETAILED DESCRIPTION

[0019] In the composite substrate illustrated in FIG. 1, when a strained III-nitride seed layer is released from the growth substrate and caused to relax, typically there is so much strain in the seed layer that a planar seed layer buckles. Trenches may be formed in the seed layer to divide the seed layer into islands smaller than the buckling wavelength. The islands relax without buckling, but forming the trenches requires additional processing steps. In addition, the step of growing a III-nitride structure on islands of seed layers requires either coalescing the III-nitride film over multiple islands, which is time consuming, or growing individual islands of III-nitride material, which reduces flexibility in device design.

[0020] In addition, bonding the seed layer twice, first to an intermediate substrate, then to the host substrate, in order to form a composite substrate where the III-nitride material is grown on the gallium face of the seed layer, requires additional processing steps and increases the likelihood of contamination of the seed layer, which may reduce yields or cause device failure.

[0021] In embodiments of the invention, a composite substrate includes a III-nitride seed layer attached to a host through an optional bonding layer. The seed layer is grown on a substrate which is lattice matched (or nearly so) to the desired III-nitride seed layer and of the same hexagonal symmetry as the III-nitride seed layer. Since the substrate is lattice matched, strain in the seed layer is reduced or eliminated, thereby improving the crystalline quality of the seed layer and any layers epitaxially deposited upon it. In some embodiments, the seed layer is grown on the substrate with the nitrogen face exposed, such that only one bonding step is required to form a composite substrate where a III-nitride structure may be grown on the gallium face of the seed layer.

[0022] FIG. 2 illustrates a seed layer 32 grown on a growth substrate 30 according to embodiments of the invention. A semiconductor layer may be characterized by a bulk lattice constant and an in-plane lattice constant. The bulk lattice constant is the lattice constant of a theoretical, fully-relaxed layer of the same composition as the semiconductor layer. The in-plane lattice constant is the lattice constant of the semiconductor layer as grown. If the semiconductor layer is strained, the bulk lattice constant is different from the in-plane lattice constant. Growth substrate 30 may be a non-III-nitride material with an in-plane lattice constant within 1% of the bulk lattice constant of the deposited seed layer 32 in some embodiments, and within 0.5% of the bulk lattice constant of the deposited seed layer 32 in some embodiments. In other words, [(|a.sub.substratea.sub.seed|)/a.sub.substrate]*100% is no more than 1% in some embodiments, and no more than 0.5% in some embodiments. For purposes of embodiments of the present invention, the bulk lattice constant of a ternary or quaternary AlInGaN layer may be estimated according Vegard's law, which for Al.sub.xIn.sub.yGa.sub.zN may be expressed as a.sub.AlInGaN=X(a.sub.AlN)+y(a.sub.InN)+z(a.sub.GaN), where the variable a refers to the bulk a-lattice constant of each binary material and x+y+z=1. AlN has a bulk lattice constant of 3.111 , InN has a bulk lattice constant of 3.544 , and GaN has a bulk lattice constant of 3.1885 .

[0023] In some embodiments, growth substrate 30 has similar or the same hexagonal basal plane symmetry as the seed layer 32. In some embodiments, growth substrate 30 is substantially impervious to attack by the chemical and thermal environment experienced during the deposition of the seed layer 32. In some embodiments, growth substrate 30 has an in-plane coefficient of thermal expansion within 30% of that of the deposited seed layer 32. In some embodiments, growth substrate 30 may or may not be transparent to near-UV radiation. In some embodiments, growth substrate 30 is a single crystal or substantially single crystal material.

[0024] In some embodiments, growth substrate 30 is a material of general composition RAO.sub.3(MO).sub.n, where R is a trivalent cation, often selected from Sc, In, Y, and the lanthanides (atomic number 57-71); A is also a trivalent cation, often selected from Fe (III), Ga, and Al; M is a divalent cation, often selected from Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer 1. In some embodiments, n9 and in some embodiments, n3. In some embodiments, RAMO.sub.4 (i.e., n=1) compounds are of the YbFe.sub.2O.sub.4 structure type, and RAO.sub.3(MO).sub.n (n2) compounds are of the InFeO.sub.3(ZnO).sub.n structure type.

[0025] Examples of suitable materials for growth substrate 30 and a lattice-matched InGaN seed layer 32 are listed below:

TABLE-US-00001 Lattice constant y in lattice-matched Material a () Appearance Al.sub.xIn.sub.yGa.sub.1xyN, x = 0 InFeZn.sub.2O.sub.5 3.309 Brown 0.34 InFeZn.sub.8O.sub.11 3.276 Brown 0.25 ScGaMgO.sub.4 3.272 Transparent 0.24 ScAlMgO.sub.4 3.236 Transparent 0.14 InAlMgO.sub.4 3.29 Transparent 0.29 ScAlMnO.sub.4 3.26 Transparent 0.20 InFeMnO.sub.4 3.356 Brown 0.48 InAlMnO.sub.4 3.319 Black 0.37 InAlCoO.sub.4 3.301 Black 0.32 InGaFeO.sub.4 3.313 Black 0.36

[0026] These and related substrate materials are described in detail by Kimizuka and Mohri in Structural Classification of RAO.sub.3(MO).sub.n. Compounds (R=Sc, In, Y, or Lanthanides; A=Fe(III), Ga, Cr, or Al; M=Divalent Cation; n=1-11), published in Journal of Solid State Chemistry 78, 98 (1989), which is incorporated herein by reference.

[0027] In some embodiments, seed layer 32 is grown on a surface of growth substrate 30 that is miscut or angled relative to a major crystallographic plane of the substrate. In some embodiments, the surface of growth substrate 30 on which seed layer 32 is grown may be oriented between 10 and +10 degrees away from the basal (0001) plane. In some embodiments, miscuts between 0.15 and +0.15 degrees tilted from the (0001) plane may result in large atomic terraces on the substrate surface that may desirably reduce the number of defects formed at terrace edges.

[0028] Seed layer 32 may be deposited on growth substrate 30 by any of the means known in the art, including, for example, MOCVD, hydride vapor phase epitaxy (HVPE), or MBE. Perfect lattice matching between the seed layer 32 and the growth substrate 30 is not necessary, although a lattice match within 0.1% may permit the deposition of high-quality seed layers 32 at least 50 m thick. Seed layer 32 may have a thickness between 100 nm and 5 m in some embodiments, and between 100 nm and 500 nm in some embodiments.

[0029] Seed layer 32 is grown on substrate 30 such that the nitrogen-face of the seed layer is the growth surface and the gallium-face of the seed layer is adjacent the substrate 30 surface. The surface of substrate 30 may be treated prior to deposition of the seed layer, for example to improve the surface or for any other purpose, for example by exposing the substrate for two minutes to a gaseous mixture of NH.sub.3 and N.sub.2 in a ration of 2:1 at a temperature of 900 C. and a pressure of 200 mbar.

[0030] Seed layer 32 may be any material on which a III-nitride device structure may be grown. Seed layer 32 is often a ternary (such as InGaN or AlGaN) or quaternary (such as AlInGaN) alloy of III-nitride or other III-V material. The fraction of InN in an InGaN seed layer 32 may be between 6% and 48% in some embodiments. The Al.sub.xIn.sub.yGa.sub.zN alloy with x0 has a range of energy gaps which produce light across the entire visible radiation spectrum. Consequently, all of the possible alloy compositions can be useful in light-emitting devices such as LEDs.

[0031] In some embodiments, a zone of weakness 34 is disposed within the growth substrate 30 or at the substrate/seed layer interface. The zone of weakness may be provided before or after the growth of the seed layer. In some embodiments, zone of weakness 34 is formed by implanting H or N, alone or in combination with other ions, in sufficient concentration such that, upon application of heat, the ions will form microcavities within the growth substrate 30. For example, H may be implanted with a dose of 10.sup.17 cm.sup.2 with an accelerating voltage of 120 keV. In some embodiments, a zone of weakness 34 is formed by exposing the wafer with a pattern of tightly focused, pulsed laser beams of sufficient intensity and photon energy to create a plurality of micron-scale crystal defects or voids in the crystalline structure. The pattern of crystal damage may be generated by rastering one or more laser beams across the wafer or the use of diffractive optics to generate a large number of spots from a single high power laser such as an excimer laser. The laser beams may be strongly converging with a short sub-microsecond pulse, and may create highly localized damage.

[0032] As illustrated in FIG. 3, a bonding layer 36 may be provided by depositing a film of SiO.sub.x, SiO.sub.2, or SiN.sub.x on the seed layer 32 by any of the means known in the art such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). The SiO.sub.2 film may have a thickness of 10 nm to 10 m in some embodiments and 200 nm to 1 m in some embodiments. The SiO.sub.2 film may optionally be planarized by chemo-mechanical polishing with, for example, a slurry of colloidal silica.

[0033] Seed layer 32 is bonded to a host substrate 38 through bonding layer 36, for example by pressing the growth substrate 30 and host substrate 38 together at elevated temperature and/or pressure. Host substrate 38 may be any suitable material, including but not limited to single crystal or polycrystalline sapphire, sintered AlN, Si, SiC, GaAs, single crystal or ceramic Y.sub.3Al.sub.5O.sub.12, which may or may not be doped with activating dopants such as Ce such that it is wavelength converting, and metals such as Mo.

[0034] As illustrated in FIG. 4, the substrate is removed from seed layer 32 by any suitable method. In structures including a zone of weakness, the growth substrate 30 may be removed at the zone of weakness, for example by heating to activate the implanted layer described above. In some embodiments, a structure including a zone of weakness of implanted H atoms is heated to a temperature of 600 C. (the temperature may be higher or lower, depending on the implant species and dose), whereupon the H atoms collect into microcavities which cause the zone of weakness to mechanically fracture. An advantage of providing a zone of weakness 34 to remove the growth substrate 30 from seed layer 32 is that the remaining portion of the substrate may be polished and used again as a growth substrate.

[0035] Other methods of removing growth substrate 30 include mechanical methods such as mechanical grinding, applying a rotational force between the substrate and the seed layer, attaching an adhesive-coated plastic film to the substrate and a second adhesive-coated plastic film to the structure including the seed layer and pulling the substrate and seed layer apart, using a sharp blade to break the interface between the substrate and the seed layer, using a pulse of sonic energy or inhomogeneous temperature distribution to break the interface between the substrate and the seed layer, applying one or more laser pulses focused to a small point (<1 mm.sup.2) at the interfacial plane creating a shockwave that initiates fracture, and applying a temperature gradient across the surface normal of the seed layer and substrate (for example, higher temperature applied to one face of the seed layer, and lower temperature applied to one face of the substrate), such that the thermally induced stress in the plane of the seed layer/substrate interface is sufficient to cause fracture of that interface.

[0036] In some embodiments, growth substrate 30 is transparent, allowing seed layer 32 to be removed by laser lift-off, where a laser beam is directed through the substrate. The layer of III-nitride material grown first on growth substrate 30 absorbs the laser light and melts, releasing seed layer 32 from the substrate. Laser lift-off may be facilitated by an optional layer of narrower-energy-gap alloy semiconductor interposing the seed layer 32 and the growth substrate 30. The composition of the narrower-energy-gap layer may be selected such that it absorbs more of the incident laser light than the seed layer 32, which may reduce the incident flux required and producing less distributed damage throughout the seed layer 32.

[0037] In some embodiments, all or a part of growth substrate 30, such as a portion of growth substrate 30 remaining after activating an implanted layer to detach the substrate from the seed layer, is removed by etching, such as wet chemical etching. For example, ScMgAlO.sub.4 is readily attacked by aqueous mixtures of H.sub.3PO.sub.4 and H.sub.2O.sub.2, H.sub.2SO.sub.4:H.sub.2O.sub.2:H.sub.2O, and aqueous mixtures of HF, as reported by C. D. Brandle, et al. in Dry and Wet Etching of ScMgAlO.sub.4 published in Solid-State Electronics, 42, 467 (1998), which is incorporated herein by reference. In some embodiments, all or part of growth substrate 30 is removed by reactive ion etching using a gaseous mixture of Cl.sub.2 and Ar at an applied power of 800 Watts.

[0038] In some embodiments, seed layer 32 is bonded to host substrate 38 through bonding layer 36 such that the group III or gallium face of the wurtzite crystal is the top surface 32a of seed layer 32, the surface available for growing III-nitride or other semiconductor material. The group V or nitrogen face of the wurtzite crystal is the bottom surface 32b of seed layer, the surface adjacent to bonding layer 36.

[0039] A semiconductor device structure 22 may be grown on seed layer 32 of the composite substrate, as illustrated in FIG. 5. Though in the examples below the semiconductor device structure is a III-nitride LED that emits visible or UV light other device such as electronic and optoelectronic devices such as laser diodes, high electron mobility transistors, and heterojunction bipolar transistors may be formed on the substrates described herein.

[0040] As illustrated in FIG. 5, a semiconductor structure 22 is grown over seed layer 32. The semiconductor structure 22 includes a light emitting or active region 23 sandwiched between n- and p-type regions 21 and 25. An n-type region 21 is typically grown first and may include multiple layers of different compositions and dopant concentration including, for example, preparation layers such as buffer layers or nucleation layers, which may be n-type or not intentionally doped, and n- or even p-type device layers designed for particular optical or electrical properties desirable for the light emitting region to efficiently emit light. The n-type region 21 is between 1 and 20 m thick in some embodiments and between 1 and 5 m thick in some embodiments. A light emitting or active region 23 is grown over the n-type region 21. Examples of suitable light emitting regions 23 include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by barrier layers. The active region 23 is between 1 nm and 5 m thick in some embodiments, between 2 nm and 1 m thick in some embodiments, and between 5 nm and 100 nm thick in some embodiments. A p-type region 25 is grown over the light emitting region 23. Like the n-type region 21, the p-type region 25 may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers. The p-type region 25 is between 100 nm and 2 m thick in some embodiments and between 20 nm and 400 nm thick in some embodiments.

[0041] In some embodiments, the light emitting layer or layers in the light emitting region 23 have a composition that is nearly lattice matched to the seed layer (which is in turn lattice-matched to the growth substrate 30). Strain in a light emitting layer is defined as [(|a.sub.bulka.sub.in-plane|)/a.sub.bulk]*100% , where awn, is the lattice constant of a layer of the same composition as the light emitting layer when fully relaxed, which is estimated according to Vegard's law, and a.sub.in-plane is the lattice constant of the light emitting layer as grown in the device. Strain in at least one of the light emitting layers is less than 1% in some embodiments, less than 0.5% in some embodiments, and less than 0.1% in some embodiments. In one embodiment, ScMgAlO.sub.4 is the growth substrate 30 and the n-type, light-emitting, and p-type layers are formed of In.sub.0.13Ga.sub.0.87N, In.sub.0.16Ga.sub.0.84N, and In.sub.0.12Ga.sub.0.88N respectively. The seed layer is the same composition as the n-type region, In.sub.0.13Ga.sub.0.87N.

[0042] The structure illustrated in FIG. 5 may be processed into any suitable device design, including but not limited to the thin film flip chip device illustrated in FIG. 6 and the vertical device illustrated in FIG. 7.

[0043] In the device illustrated in FIG. 6, p-contact metal 26 is disposed on the p-type region 25, then portions of the p-type region 25 and active region 23 are etched away to expose an n-type layer for metallization. The p-contacts 26 and n-contacts 24 are on the same side of the device. P-contacts 26 are electrically isolated from n-contacts 24 by gaps 27, which may be filled with an electrically insulating material such as a dielectric. As illustrated in FIG. 6, p-contacts 26 may be disposed between multiple n-contact regions 24, though this is not necessary. In some embodiments either or both the n-contact 24 and the p-contact 26 are reflective and the device is mounted such that light is extracted through the top of the device in the orientation illustrated in FIG. 6. In some embodiments, the contacts may be limited in extent or made transparent, and the device may be mounted such that light is extracted through the surface on which the contacts are formed. The semiconductor structure is attached to a mount 28. All or part of the composite substrate on which semiconductor structure 22 is grown may be removed, as illustrated in FIG. 3, or may remain part of the device. For example, host substrate 38 and bonding layer 36 may be removed, and seed layer 32 may remain part of the device. In some embodiments, the semiconductor layer exposed by removing all or part of the composite substrate is patterned or roughened, which may improve light extraction from the device.

[0044] In the vertical injection LED illustrated in FIG. 7, an n-contact is formed on one side of the semiconductor structure 22, and a p-contact is formed on the other side of the semiconductor structure. For example, the p-contact 26 may be formed on the p-type region 25 and the device may be attached to mount 28 through p-contact 26. All or a portion of the composite substrate may be removed and an n-contact 24 may be formed on a surface of the n-type region 21 exposed by removing all or a portion of the composite substrate. Electrical contact to the n-contact may be made with a wire bond as illustrated in FIG. 7 or a metal bridge.

[0045] The LED may be combined with one or more wavelength converting materials such as phosphors, quantum dots, or dyes to create white light or monochromatic light of other colors. All or only a portion of the light emitted by the LED may be converted by the wavelength converting materials. Unconverted light emitted by the LED may be part of the final spectrum of light, though it need not be. Examples of common combinations include a blue-emitting LED combined with a yellow-emitting phosphor, a blue-emitting LED combined with green- and red-emitting phosphors, a UV-emitting LED combined with blue- and yellow-emitting phosphors, and a UV-emitting LED combined with blue-, green-, and red-emitting phosphors. Wavelength converting materials emitting other colors of light may be added to tailor the spectrum of light emitted from the device.

[0046] The wavelength converting element may be, for example, a pre-formed ceramic phosphor layer that is glued or bonded to the LED or spaced apart from the LED, or a powder phosphor or quantum dots disposed in an organic encapsulant that is stenciled, screen printed, sprayed, sedimented, evaporated, sputtered, or otherwise dispensed over the LED.

[0047] Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.