Electric apparatus

Abstract

Provided is an electric apparatus including a reception unit (for example, hardware key) for receiving an instruction relating to functions of the electric apparatus and having operation states of a power conserving state in which power required for performing the functions thereof is limited and a normal state in which the power is not limited, wherein the reception unit may receive an instruction indicating a return to the normal state in the power conserving state and receive an instruction which is to be originally received in the normal state. When the reception unit receives the instruction, signals at different levels are output depending on the operation state and based on the signal to be output, a return signal relating to the return to the normal state or an execution signal relating to the execution of a function corresponding to the instruction received by the receiving signal is output.

Claims

1. An electric equipment including a reception unit configured to receive an instruction relating to functions of the electric equipment by an operation of a user and having operation states of a power conserving state in which power required for performing the functions thereof is limited and a normal state in which the power is not limited, the electric equipment comprising: a signal output unit configured to output signals of different levels depending on the operation state when the reception unit receives the instruction from the user; and a control signal unit configured to selectively output a return signal relating to a return to the normal state or an execution signal relating to an execution of a function corresponding to the instruction received by the reception unit, based on the signal output from the signal output unit.

2. The electric equipment according to claim 1, wherein the signal output unit has two terminals configured to output signals to the control signal unit, and the control signal unit outputs the return signal or the execution signal, based on a signal level relating to any one of the two terminals which are defined by the operation state.

3. The electric equipment according to claim 1, wherein the control signal unit includes: a return signal unit which has two input terminals corresponding to the terminals of the signal output unit, and is configured to output the return signal; and an execution signal unit configured to output the execution signal, wherein the return signal unit outputs the return signal based on the signal level of one input terminal of the two input terminals, and the execution signal unit outputs the execution signal based on the signal level of the other input terminal.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 is a functional block diagram illustrating a configuration of main components of a multi-function peripheral according to an embodiment of the present invention.

(2) FIG. 2 is a functional block diagram illustrating a configuration of main components of a control unit in the multi-function peripheral according to the embodiment of the present invention.

(3) FIG. 3 is an explanatory diagram describing a connection relation between a CPLD, a south bridge, and an SOC in the multi-function peripheral according to the embodiment of the present invention.

(4) FIG. 4 is a flow chart describing an instruction reception of a home key in the multi-function peripheral according to the embodiment of the present invention.

DETAILED DESCRIPTION

(5) Hereinafter, a case in which an electric apparatus according to an embodiment of the present invention is applied to a multi-function peripheral will be described in detail, by way of example, with reference to the accompanying drawings. The multi-function peripheral has a function of a scanner, a facsimile, a printer and the like.

(6) The multi-function peripheral according to the embodiment of the present invention has operation modes (operation states) of a power conserving mode (power conserving state) and a standby mode (normal state). In the power conserving mode, a supply of power to parts relating to the execution of functions of the multi-function peripheral is limited and thus power consumption is reduced. Further, in the standby mode, power is supplied to the parts in which the supply of power was limited, such that prescribed functions may be immediately performed according to an instruction from a user.

(7) FIG. 1 is a functional block diagram illustrating a configuration of main components of a multi-function peripheral 100 according to an embodiment of the present invention. The multi-function peripheral 100 includes a control unit 1, an image input unit 2, an image processing unit 3, an image output unit 4, an operation panel 5, a display unit 6, a storage unit 7 and the like.

(8) The image input unit 2 includes a light source irradiating light to a manuscript for reading, an image sensor such as a charge coupled device (CCD), or the like, and optically reads image data of the manuscript. Further, the image input unit 2 forms an image reflected from the manuscript set at a prescribed read position on the image sensor to output analog data of red-green-blue (RGB).

(9) The image processing unit 3 generates, for example, digital type image data based on the analog data input from the image input unit 2 or reads the image data stored in the storage unit 7, performs processing depending on each form of images, and then generates image data to be output (printed). The image data for outputting generated by the image processing unit 3 is output to the image output unit 4.

(10) The image output unit 4 prints an image on a recording medium such as recording paper, an OHP film, or the like based on the image data output from the image processing unit 3. The image output unit 4 includes a photosensitive drum, a charger for charging the photosensitive drum to a prescribed potential, a laser writing device which emits a laser beam depending on the image data received from an outside to generate an electrostatic latent image on the photosensitive drum, a developing device which supplies a toner to the electrostatic latent image formed on a surface of the photosensitive drum to develop the image, a transfer unit which transfers a toner image formed on the surface of the photosensitive drum onto the recording medium, and forms the image on the recording medium by an electro-photographic method.

(11) Further, in the multi-function peripheral 100, the operation panel 5 is provided with hardware keys, such as a function key for switching functions such as facsimile, copy, printing, mail, and the like, a start key, a cancel key, an enter key for fixing a received instruction, and a home key for returning a display screen of the display unit 6 to a home screen receiving a selection of any one of functions of the multifunction peripheral 100.

(12) The display unit 6 includes, for example, an LCD, an electroluminescence (EL) panel, or the like and displays an image to be output (printed) on a prescribed recording paper through the image output unit 4. Further, the display unit 6 displays information to be notified to the user, such as a state of the multi-function peripheral 100, a job processing situation, an image of a manuscript read by the image input unit 2, and a confirmation of an operation content of the operation panel 5 and the like.

(13) The storage unit 7 includes, for example, a non-volatile storage medium such as a flash memory, an EEPROM, an HDD, a magneto-resistive memory (MRAM), a ferroelectric RAM (FeRAM), an OUM or the like.

(14) FIG. 2 is a functional block diagram illustrating a configuration of main components of the control unit 1 in the multi-function peripheral 100 according to the embodiment of the present invention.

(15) The control unit 1 includes an instruction control unit 11, a complex programmable logic device (CPLD) 16, and a system memory 17. The instruction control unit 11 has a system on chip (SOC) 13 in which a south bridge (SB) 12, a CPU 14, and a north bridge (NB) 15 are integrated as a single chip. Further, the system memory 17 includes a ROM 18 and a RAM 19.

(16) The instruction control unit 11, the CPLD 16, and the SOC 13 play a role of the control signal unit, the signal output unit, and the execution signal unit described in the claims, respectively.

(17) FIG. 3 is an explanatory diagram describing a connection relation between the CPLD 16, the south bridge 12, and the SOC 13 in the multi-function peripheral 100 according to the embodiment of the present invention.

(18) The CPLD 16 is a programmable logic unit which is an electrical circuit having a structure capable of being modified by programming and is connected to the image input unit 2, the image output unit 4, the storage unit 7, the operation panel 5 and the like. The CPLD 16 is equipped with wirings connected to these circuits and is connected thereto through a PCI bus N.

(19) The CPLD 16, in particular, allows the control unit 1 to perform a sequence control. For example, the CPLD 16 controls mode shifting based on the prescribed signal from the south bridge 12 and performs a change in a connection destination of a signal, a signal output, and the like in accordance with each mode.

(20) In detail, the CPLD 16 includes an input terminal 161 for receiving a signal output from the operation panel 5 and output terminals 162 and 163 for outputting a signal to the south bridge 12. When a prescribed signal is input from the operation panel 5 through the input terminal 161, the CPLD 16 outputs signals at different levels to the south bridge 12 through the output terminals 162 and 163 based on whether a current operation mode is the standby mode or the power conserving mode.

(21) The south bridge 12 plays a role of a so-called chip set for controlling a flow of signals within the control unit 1. Further, the south bridge 12 serves to connect the PCI bus N with an ISA bus.

(22) The south bridge 12 (return signal unit), in particular, outputs a signal which is to be a trigger of the mode shifting. For example, the south bridge 12 outputs a WAKE_CNT signal which is a trigger signal in the return from the power conserving mode to the standby mode.

(23) Specifically, the south bridge 12 has an input terminal 121 and an input terminal 122 each corresponding to the output terminal 162 and the output terminal 163 of the CPLD 16, and has an output terminal 123 for outputting a signal to the SOC 13 and an output terminal 124 for outputting a signal to a power supply circuit (for example, DCDC) of hardware relating to each above-described function. The WAKE_CNT signal is output to the power supply circuit through the output terminal 124.

(24) The north bridge 15 has a function as a memory controller and a graphic processing unit (GPU) and similar to the south bridge 12, plays a role of a so-called chip set for controlling the flow of signals within the control unit 1. Further, the north bridge 15 serves to connect the CPU 14 with the PCI bus N.

(25) The ROM 18 is basically pre-stored with various control programs, fixed data among parameters for operation, and the like, and the RAM 19 temporarily stores data and reads the data independent of a storage order, a storage position or the like. Further, the RAM 19 stores, for example, programs read from the ROM 18, various data generated by running the programs, parameters appropriately changed at the time of running and the like.

(26) The CPU 14 loads and runs a control program pre-stored in the ROM 18 onto the RAM 19 to control various types of the above-described hardware and operates the overall apparatus as the multi-function peripheral 100 according to the present invention.

(27) Further, the CPU 14 detects the signal input to SOC13 through the output terminal 123 of the south bridge 12, and outputs an instruction signal HM_BACK_CNT to the display unit 6 (OS) to return the display screen of the display unit 6 to the home screen through the north bridge 15 based on the detected result.

(28) In the multi-function peripheral 100 having the above-described configuration according to the embodiment of the present invention, when any one of the hardware keys provided in the operation panel 5 is operated by the user, the operated hardware key receives the operation as other instructions depending on the current operation mode.

(29) In other words, the multi-function peripheral 100 according to the embodiment of the present invention is configured to allow the hardware key of the operation panel 5 to perform other functions depending on the operation mode. Hereinafter, the home key 51 will be described as an example of the hardware key with reference to FIG. 3.

(30) Before the user performs an operation for pushing the home key 51, the home key 51 outputs a HM_KEY=1 signal. Meanwhile, when the user performs an operation for pushing the home key 51, a HM_KEY=0 signal is output (wherein 1=H/0=L). In this case, a 0 signal is input to the input terminal 161 of the CPLD 16.

(31) When the HM_KEY=0 signal is input, that is, when the home key 51 is operated by the user, the CPLD 16 outputs different levels of signals to the south bridge 12 based on whether the current operation mode is the standby mode or the power conserving mode. Hereinafter, based on the standby mode and the power conserving mode it will be described separately.

(32) <Standby Mode>

(33) When the HM_KEY=0 signal is input, the CPLD 16 outputs signals of WAKE_N=Z and HM_BACK=1 to the south bridge 12 through the output terminals 162 and 163, respectively, at the time when the multi-function peripheral 100 is currently in the standby mode (Z is high impedance).

(34) Next, the signals of the WAKE_N=Z and HM_BACK=1 from the CPLD 16 are input to the input terminals 121 and 122 of the south bridge 12, respectively.

(35) In this case, the CPU 14 monitors the input terminal 122 of the south bridge 12 through the north bridge 15. Meanwhile, when the CPU 14 detects the input of the HM_BACK=1 signal to the input terminal 122, issues an instruction to output the HM_BACK_CNT signal and return the display screen of the display unit 6 to the home screen. Then, the display screen of the display unit 6 is shifted to become the home screen.

(36) <Power Conserving Mode>

(37) Meanwhile, when the HM_KEY=0 signal is input, the CPLD 16 outputs signals of WAKE_N=0 and HM_BACK=0 to the south bridge 12 through the output terminals 162 and 163, respectively, at the time when the multi-function peripheral 100 is currently in the power conserving mode.

(38) Next, the signals of the WAKE_N=0 and HM_BACK=0 from the CPLD 16 are input to the input terminals 121 and 122 of the south bridge 12, respectively.

(39) As described above, when the WAKE_N=0 signal is input to the input terminal 121, the south bridge 12 outputs the WAKE_CNT signal through the output terminal 124. For example, the WAKE_CNT signal is output to the CPLD 16. When the WAKE_CNT signal is input, the CPLD 16 outputs a signal indicating a instruction to power on the power supply circuit of the hardware relating to each function as described above.

(40) Meanwhile, the user holds the home key 51 down, and therefore the time from when the HM_KEY=0 signal is informed to the south bridge 12 until the WAKE_CNT signal is output is several s, and a speed at which the user may subsequently hold the home key 51 down is about several 10 ms. Therefore, there is no risk of a malfunction due to a subsequent pushing of the home key 51 by a user.

(41) As described above, in the multi-function peripheral 100 according to the embodiment of the present invention, the hardware key of the operation panel 5 receives the instruction to be originally received in the standby mode and receives the instruction to return from the power conserving mode to the standby mode in the power conserving mode. Therefore, there is no need to separately provide the hardware key for receiving the instruction indicating a return to the standby mode.

(42) FIG. 4 is a flow chart describing the instruction reception of the home key 51 in the multi-function peripheral 100 according to the embodiment of the present invention.

(43) When the user performs an operation for pushing the home key 51, the home key 51 receives the operation (step S101) and the HM_KEY=0 signal is output (wherein 1=H/0=L).

(44) Thereby, when the 0 signal is input to the input terminal 161 of the CPLD 16, and the multi-function peripheral 100 is currently in the standby mode (YES in step S102), the CPLD 16 outputs the signals of the WAKE_N=Z and HM_BACK=1 to the south bridge 12 through the output terminals 162 and 163, respectively (step S103). The signals of the WAKE_N=Z and HM_BACK=1 from the CPLD 16 are input to the input terminals 121 and 122 of the south bridge 12, respectively.

(45) During monitoring the input terminal 122 of the south bridge 12, when the CPU 14 detects the input of the HM_BACK=0 signal (NO in step S104), the CPU 14 processes the signal as an invalidation (step S105) and returns the processing to S104 again.

(46) Meanwhile, during monitoring the input terminal 122 of the south bridge 12, when the CPU 14 detects the input of the HM_BACK=1 signal (YES in step S104), the CPU 14 issues an instruction to output the HM_BACK_CNT signal to the OS and return the display screen of the display unit 6 to the home screen (step S106).

(47) Depending on the instruction from the CPU 14, the OS shifts the display screen which is being displayed on the display unit 6 to the home screen (step S107).

(48) Meanwhile, when the multi-function peripheral 100 is in the power conserving mode (NO in step S102) at the time when a 0 signal is input to the input terminal 161 of the CPLD 16, the CPLD 16 outputs the signals of the WAKE_N=0 and HM_BACK=0 to the south bridge 12 through the output terminals 162 and 163, respectively (step S108). The signals of the WAKE_N=0 and HM_BACK=0 from the CPLD 16 are input to the input terminals 121 and 122 of the south bridge 12, respectively.

(49) In this case, the CPU14 monitors the signal input to the input terminal 121. For example, when the WAKE_N=1 signal is input to the input terminal 121 (NO in step S109), the CPU14 processes the signal as an invalidation (step S110) and returns the processing to step S109 again.

(50) Meanwhile, when the WAKE_N=0 signal is input to the input terminal 121 (YES in step S109), the south bridge 12 outputs the WAKE_CNT signal which is the return signal indicating the return from the power conserving mode to the standby mode through the output terminal 124 (step S111).

(51) The WAKE_CNT signal is output to the CPLD 16, and as described above, the CPLD 16 outputs the signal indicating the instruction to power on the power supply circuit of the hardware relating to each function (step S112).

(52) Next, the processing is performed similar to the initial starting, and thus operation mode returns to the standby mode state prior to being shifted to the power conserving mode (step S113).

(53) As described above, although the home key 51 as the hardware key of the operation panel 5 is described by way of example, the present invention is not limited thereto, and therefore any one of the hardware keys such as a numeric pad, a start key, a stop key, and the like may be used.

(54) As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalence of such metes and bounds thereof are therefore intended to be embraced by the claims.