Phase shorting switch

Abstract

An analog-to-digital converter (ADC) may include capability to sense and/or compensate for undesired effects when receiving input from a microphone. For example, a sense node may be provided between differential inputs, and that sense node separated from the differential inputs by two or more switches. The sense node may allow for a measurement of an average voltage of the differential inputs. The average voltage may be obtained activating the switches to sample the sampling capacitors coupled to the differential inputs. That average voltage may be used as common mode (CM) data. A controller may receive the CM data, along with differential mode (DM) data, and use the CM and DM data to determine undesired effects, such as DC or AC mismatch at the microphone interface. The controller may then generate a signal for applying compensation to the differential inputs to reduce or eliminate the undesired effects.

Claims

1. A method for compensating common mode and differential mode mismatches for an analog-to-digital converter (ADC), comprising: receiving digital common mode (CM) data and differential mode (DM) data; and generating a control signal for output to a digital-to-analog converter (DAC) such that the digital-to-analog converter (DAC) provides compensation in the analog-to-digital converter (ADC) for least one of common mode and differential mode mismatches based, at least in part, on the received digital common mode (CM) data and differential mode (DM) data.

2. The method of claim 1, wherein the step of receiving the common mode (CM) data comprises receiving a DC average voltage level between differential input nodes of the analog-to-digital converter (ADC), wherein the DC average voltage level is received from a common mode (CM) sense node coupled to the differential input nodes by switches.

3. The method of claim 2, further comprising the step of activating the switches to sample sampling capacitors coupled to the differential input nodes, wherein the switches are activated to obtain the DC average voltage level.

4. The method of claim 1, wherein the step of receiving the differential mode (DM) data comprises receiving a difference between differential input nodes, wherein the difference is received from a quantizer of the analog-to-digital converter (ADC).

5. The method of claim 1, wherein the step of generating the control signal comprises the steps of: determining a configuration of a microphone coupled to differential input nodes of the analog-to-digital converter (ADC); and determining common mode and differential mode mismatches in the analog-to-digital converter (ADC), wherein the step of generating the control signal comprises generating the control signal based, at least in part, on the determined configuration of the microphone and the determined common mode and differential mode mismatches.

6. The method of claim 1, wherein the analog-to-digital converter (ADC) comprises a switched-capacitor ADC.

7. The method of claim 1, wherein the analog-to-digital converter (ADC) comprises a continuous-time ADC.

8. An apparatus, comprising: a controller configured to operate an analog-to-digital converter (ADC) by performing steps comprising: receiving digital common mode (CM) data and differential mode (DM) data; and generating a control signal for output to a digital-to-analog converter (DAC) such that the digital-to-analog converter (DAC) provides compensation in the analog-to-digital converter (ADC) for a mismatch of at least one of common mode and differential mode based, at least in part, on the received digital common mode (CM) data and differential mode (DM) data.

9. The apparatus of claim 8, wherein the step of receiving the common mode (CM) data comprises receiving a DC average voltage level between differential input nodes, wherein the DC average voltage level is received from a common mode (CM) sense node coupled to the differential input nodes by switches.

10. The apparatus of claim 9, wherein the controller is further configured to perform the step of activating the switches to sample sampling capacitors coupled to the differential input nodes, wherein the switches are activated to obtain the DC average voltage level.

11. The apparatus of claim 8, wherein the step of receiving the differential mode (DM) data comprises receiving a difference between differential input nodes, wherein the different is received from a quantizer of the analog-to-digital converter (ADC).

12. The apparatus of claim 8, wherein the step of generating the control signal comprises the steps of: determining a configuration of a microphone coupled to differential input nodes of the analog-to-digital converter (ADC); and determining undesired effects in the analog-to-digital converter (ADC), wherein the step of generating the control signal comprises generating the control signal based, at least in part, on the configuration of the microphone and the undesired effects.

13. The apparatus of claim 8, wherein the controller is configured to control a switched capacitor analog-to-digital converter (ADC).

14. The apparatus of claim 8, wherein the controller is configured to control a continuous-time analog-to-digital converter (ADC).

15. A method for sensing an average of differential input voltages at two input nodes in a common-mode insensitive switched-capacitor system, comprising: providing differential inputs to the switched-capacitor system, wherein at least two sampling capacitors are coupled to each of the two input nodes; and operating two or more switches to sample the at least two sampling capacitors such that an average voltage of the differential inputs is generated at an output node.

16. The method of claim 15, further comprising converting an analog value of the average voltage to a digital value for feedback to a controller of the switched-capacitor system.

17. The method of claim 15, further comprising compensating for undesired effects at the differential inputs based, at least in part, on the average voltage generated at the output node.

18. An apparatus, comprising: a differential input comprising a first input node and a second input node; at least two sampling capacitors comprising a first capacitor coupled to the first input node and a second capacitor coupled to the second input node; at least two switches comprising a first switch coupled to the first capacitor and a second switch coupled to the second capacitor and coupled to the first switch; and a controller coupled to the at least two switches, wherein the controller is configured to perform steps comprising operating the at least two switches to sample the at least two sampling capacitors such that an average voltage of the differential inputs is generated at an output node between the first switch and the second switch.

19. The apparatus of claim 18, further comprising an analog-to-digital converter (ADC) coupled to the output node and coupled to the controller, wherein the ADC is configured to provide common mode (CM) data to the controller based on the average voltage.

20. The apparatus of claim 18, further comprising a digital-to-analog converter (DAC), wherein the controller is further configured to operate the DAC to compensate for mismatch at the differential input based, at least in part, on the average voltage generated at the output node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a more complete understanding of the disclosed system and methods, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.

(2) FIG. 1A is a block diagram illustrating a microphone coupled to an analog-to-digital converter (ADC) in a fully-differential AC-coupled configuration.

(3) FIG. 1B is a block diagram illustrating a microphone coupled to an analog-to-digital converter (ADC) in a pseudo-differential AC-coupled configuration.

(4) FIG. 1C is a block diagram illustrating a microphone coupled to an analog-to-digital converter (ADC) in a fully-differential DC-coupled configuration.

(5) FIG. 1D is a block diagram illustrating a microphone coupled to an analog-to-digital converter (ADC) in a pseudo-differential DC-coupled configuration.

(6) FIG. 1E is a graph illustrating a modulator digital output code in an analog-to-digital converter (ADC).

(7) FIG. 1F is a graph illustrating a modulator digital output code in an analog-to-digital converter (ADC) with fully-differential inputs having mismatched common mode (CM) values.

(8) FIG. 1G is a graph illustrating a modulator digital output code in an analog-to-digital converter (ADC) with fully-differential inputs having mismatched differential mode (DM) values.

(9) FIG. 2 is a flow chart illustrating a method of detecting and adjusting operation of an analog-to-digital converter (ADC) to match a microphone topology according to one embodiment of the disclosure.

(10) FIG. 3 is a block diagram illustrating a portion of an analog-to-digital converter (ADC) with two processing paths for processing analog signals according to one embodiment of the disclosure.

(11) FIG. 4 is a flow chart illustrating a method of converting analog signals to digital signals in an analog-to-digital converter (ADC) with two processing paths according to one embodiment of the disclosure.

(12) FIG. 5 is a circuit schematic illustrating a portion of an analog-to-digital converter with two processing paths according to one embodiment of the disclosure.

(13) FIG. 6 is a circuit schematic illustrating digital-to-analog converters (DACs) from the feedback path of the analog-to-digital converter (ADC) according to one embodiment of the disclosure.

(14) FIG. 7 is a table showing example outputs from a 5-bit analog-to-digital converter (ADC) configured according to one embodiment of the disclosure.

(15) FIG. 8 is an illustration showing an electronic device with an analog-to-digital converter (ADC) capable of operating microphones of different topologies according to one embodiment of the disclosure.

(16) FIG. 9 is a circuit schematic illustrating front-end switches for an analog-to-digital converter (ADC) with shoring phase switches configured to provide a sense node according to one embodiment of the disclosure.

(17) FIG. 10 is a circuit schematic illustrating interface detection and compensation for an analog-to-digital converter (ADC) according to one embodiment of the disclosure.

(18) FIG. 11 is a flow chart illustrating an example method for determining microphone configuration and applying mismatch compensation according to one embodiment of the disclosure.

(19) FIG. 12 is a flow chart illustrating an example method for compensating undesired effects in an analog-to-digital converter (ADC) according to one embodiment of the disclosure.

(20) FIG. 13 is a flow chart illustrating an example method for sensing common mode (CM) data in an analog-to-digital converter (ADC) according to one embodiment of the disclosure.

DETAILED DESCRIPTION

(21) FIG. 2 is a flow chart illustrating a method of detecting and adjusting operation of an analog-to-digital converter (ADC) to match a microphone topology according to one embodiment of the disclosure. A method 200 begins at block 202 with monitoring an output of an analog-to-digital converter (ADC) that is receiving analog input from a microphone. The monitored output may be, for example, a digital output or a pseudo-digital output from the ADC. Then, at block 204, a coupling configuration of the microphone may be determined based on the monitored output of the ADC at block 202. The determination may be made based on instantaneous values at the ADC output or the determination may be made by evaluating the ADC output over a certain period of time. Next, at block 206, the operation of the analog-to-digital converter (ADC) may be adjusted based on the determined coupling configuration of the microphone. The method 200 may be performed by a controller coupled to the analog-to-digital converter or a controller integrated with the analog-to-digital converter.

(22) One method of processing the analog signal from a microphone in an ADC to determine microphone configuration as described in FIG. 2 is to process the microphone input signals in two processing paths. A first processing path may process a difference between differential input signals, and a second processing path may process an average value of the differential input signals. FIG. 3 is a block diagram illustrating a portion of an analog-to-digital converter (ADC) with two processing paths for processing analog signals according to one embodiment of the disclosure. An analog-to-digital converter (ADC) 300 may include a first input node 302 and a second input node 304. The input nodes 302 and 304 may be configured to couple to a microphone 310 to receive, as a differential or pseudo-differential input, an analog signal generated by the microphone 310 indicative of sounds in an environment around the microphone 310. Although only portions of the ADC 300 are illustrated in FIG. 3, such as loop filter components, additional components not shown in FIG. 3 may be present in an ADC.

(23) The ADC 300 may process the input received at input nodes 302 and 304 to generate digital output D.sub.out at output node 308. Processing may occur through two processing paths 312 and 322. A differential processing path 322 may process a difference between the differential signal at input nodes 302 and 304. A common mode processing path 312 may process an average value of the differential inputs at input nodes 302 and 304. In one embodiment, the common mode processing path 312 may generate a difference between the average value of the differential inputs and an ideal common mode voltage V.sub.CMI received at an input node 306. Outputs of the processing paths 312 and 322 may be provided to combiner 332, which generates at least one digital output signal D.sub.out at output node 308.

(24) A method for processing an analog differential signal through an ADC configured with two processing paths as illustrated in FIG. 3 is described with reference to FIG. 4. FIG. 4 is a flow chart illustrating a method of converting analog signals to digital signals in an analog-to-digital converter (ADC) with two processing paths according to one embodiment of the disclosure. A method 400 begins at block 402 with receiving a first input and a second input of an analog differential signal for conversion to a digital signal. Then, at block 404, a difference between the first input and the second input is processed in a first processing loop, such as the differential processing path 322 of FIG. 3. Next, at block 406, an average of the first input and the second input is processed in a second processing path, such as in common mode processing path 312 of FIG. 3. The processing of blocks 404 and 406 may occur simultaneously. In other embodiments, the processing of blocks 404 and 406 may occur in serial fashion for individual samples taken from the first input and the second input. Then, at block 408, the output of the difference processing of block 404 and the average processing of block 406 may be combined, such as in combiner 332 of FIG. 3, to produce the digital signal. The digital signal produced by combining the outputs of the processing paths corresponds to a digital representation of the analog differential signal. When a microphone is coupled to the first input and the second input, this digital signal is a digital representation of sounds in an environment around the microphone.

(25) One embodiment for implementing an analog-to-digital converter (ADC) with two processing paths implements the two processing paths as delta-sigma modulators as shown in FIG. 5. FIG. 5 is a circuit schematic illustrating a portion of an analog-to-digital converter with two processing paths according to one embodiment of the disclosure. An analog-to-digital converter (ADC) 500 supports a universal microphone topology, which supports microphone topologies such as AC-coupled, DC-coupled, fully-differential, and pseudo-differential microphones. The first processing path 322 and the second processing path 312 include loop filters 522 and 512 and quantizers 524 and 514, respectively. The processing paths 312 and 322 output to combiner 332, which generates a pseudo-digital signal at output nodes 308A and 308B. The pseudo-digital signal at nodes 308A and 308B are provided through a feedback path 540 to inputs of the processing paths 312 and 322, respectively. The feedback path 540 includes digital-to-analog converters (DACs) 542 and 544. Outputs of the DACs 542 and 544 may be coupled to first and second inputs of the differential processing path 322, respectively. Further, the output of the DACs 542 and 544 may be averaged for input to the common mode processing path 312. Each of the processing paths 312 and 322 thus is a functional ADC loop coupled to the same front-end and back-end. However, each of the processing paths 312 and 322 processes different aspects of the input signal received at input nodes 302 and 304.

(26) The input nodes 302 and 304 couple a differential signal to two front-end summing nodes V.sub.xn, V.sub.xp and into the differential-mode (DM) loop filter 522. The input nodes 302 and 304 also couple an average of the differential signal to the common-mode (CM) loop filter 512. The common mode loop filter also receives an ideal CM voltage V.sub.CMI from input node 306, which may indicate a desired common mode voltage selected to match a desired input at amplifiers (not shown) within the loop filters 512 and 522. Thus, a differential error signal passes through the DM loop filter 522, and a common-mode error signal passes through the CM loop filter 512. The loop filters 512 and 522 may include, for example, integrators that contain operational amplifiers. Those operational amplifiers may be designed to operate in certain ranges that match the ideal common mode voltage V.sub.CMI received at node 306. The output of the loop filters 512 and 522 are quantized in quantizers 514 and 524, respectively, to generate digital outputs D.sub.CM and D.sub.DM. The D.sub.CM digital output may contain a digital representation of an error signal based on comparing the average value of the inputs with the ideal common mode voltage V.sub.CMI; the D.sub.DM digital output may contain a digital representation of an error signal based on the differential input at input nodes 302 and 304. After quantization, the CM and DM digital outputs, D.sub.CM and D.sub.DM, are combined at combiner 332, such as by using a decoder to generate pseudo digital data, which carries CM and DM information. The pseudo-digital data may be output as D.sub.p and D.sub.n signals at nodes 308A and 308B, in which D.sub.p contains (D.sub.CM+D.sub.DM/2) information, and D.sub.n contains (D.sub.CMD.sub.DM/2) information. The combiner may include an amplifier 532 and summation blocks 534 and 536 to generate the output D.sub.p and D.sub.n signals from the output of paths 312 and 322.

(27) The pseudo-digital data (D.sub.n, D.sub.p) may be coupled to DACs 544 and 542, respectively, in feedback path 540. In one embodiment, the DACs 544 and 542 may be implemented as current-steering DACs. FIG. 6 is a circuit schematic illustrating digital-to-analog converters (DACs) from the feedback path of the analog-to-digital converter (ADC) according to one embodiment of the disclosure. In the DACs 542 and 544, the pseudo-digital output D.sub.p controls the switches of the current DAC in DAC.sub.p 542 and D.sub.n controls the switches of DAC.sub.n 544.

(28) Operation of the ADC 500 of FIG. 5 may be explained with reference to FIG. 7, which is a table showing example outputs of the ADC 500 when configured as a 5-bit ADC. For the AC-coupled fully-differential microphone topology, the DC values of V.sub.in and V.sub.ip may be set to V.sub.CMI internally and the CM error may be zero. As a result, DAC 542 output value I.sub.p may sweep from 32*I.sub.DAC to +32*I.sub.DAC, and DAC 544 output value I.sub.n may sweep from +32*I.sub.DAC to 32*I.sub.DAC resulting in an opposite code on D.sub.n and D.sub.p. For the DC-coupled fully-differential topology, if the DC value of the inputs at nodes 302 and 304 is matched with V.sub.CMI at node 306, there will not be any common-mode error signal, and the output will be similar to that of the AC-coupled FD case. For the DC-coupled fully-differential topology, if the DC value of the inputs at nodes 304 and 304 is not matched with V.sub.CMI at node 306 (such that there is a CM error), then the CM loop filter 512 may adjust I.sub.p and I.sub.n values to offset that CM error. Then, the output again will be similar to that of the AC-coupled FD case. Thus, if a controller, such as controller 550 of FIG. 5, detects an average of D.sub.n and D.sub.p digital output codes is zero, then the controller may determine that the microphone topology is fully-differential. The controller may further discriminate between the AC-coupled and DC-coupled variations of the fully-differential topology by receiving additional information. For example, the controller may receive a programmed signal from a memory or a fuse. In another example, the controller may determine an amount of current drawn from the V.sub.CMI input node 306.

(29) For the AC-coupled pseudo-differential topology, DC values of V.sub.ip and V.sub.in may be set internally to match V.sub.CMI received at input node 306. Then, the D.sub.p and I.sub.p values may be similar to that of the AC-coupled FD case, but different in that the I.sub.n value will be zero (D.sub.n=[10000], which is the mid code), because there is no AC signal at node 304 for V.sub.in and its DC value is set by a V.sub.cm generator block (not shown). Thus, if a controller, such as controller 550 of FIG. 5, detects a D.sub.n value of [10000], then the controller may determine that the microphone topology is AC-coupled pseudo-differential.

(30) For the DC-coupled pseudo-differential topology, D.sub.p and I.sub.p values will be similar to that for the AC-coupled pseudo-differential topology (assuming the DC value on V.sub.ip matches V.sub.CMI), but I.sub.p will max out at +32*I.sub.DAC to set the DC value of the V.sub.xn node, resulting in an output value D.sub.n=[11111]. Thus, if a controller, such as controller 550 of FIG. 5, detects a D.sub.n value of [11111], then the controller may determine that the microphone topology is DC-coupled pseudo-differential topology.

(31) A controller may use a digital detection algorithm to detect the microphone topology by monitoring the data pattern on D.sub.p and D.sub.n and based on that distinguish the various topologies. In some embodiments, additional information may be provided to the controller to assist in the determination. After determining the microphone topology, the controller may adjust operation of the ADC based on the determined topology. For example, when the topology is pseudo-differential AC-coupled, the controller 550 may shut down DAC 544. Alternatively, a few units of the DAC 544 may remain switched on for determining mismatches. As another example, when the topology is pseudo-differential DC-coupled, the controller may shut down NMOS side current of DAC 544 to reduce power consumption. In some embodiments, the controller may wait to adjust operation of the DAC until a stable condition is achieved within the ADC. The stable condition may be reached after a certain amount of time has elapsed from start-up of the ADC or a signal first appearing at the input of the ADC. Alternatively, the stable condition may be reached when the output of the DAC reaches an expected signal. The controller 550 described herein may be integrated with the DAC or external to the DAC.

(32) The DAC configurations described above as a universal and/or adaptive DAC for various microphone topologies may be implemented in an electronic device having microphones (or other analog input devices interacting with digital components). FIG. 8 is an illustration showing an electronic device with an analog-to-digital converter (ADC) capable of operating microphones of different topologies according to one embodiment of the disclosure. A mobile device 802 may be, for example, a cellular telephone. Mobile devices 802 may include multiple microphones, such as speech microphones 804A and 804B, proximity microphone 804C for noise cancelling, and/or headset microphone 806. Microphones may be either integrated with the electronic device 802, such as microphones 804A, 804B, and 804C, or may be external to the electronic device 802, such as with microphone 806. An ADC 810 of the electronic device 802 may be coupled to the microphones 804A, 804B, 804C, and/or 806 to process input signals from the microphones 804A, 804B, 804C, and/or 806. The ADC 810 may incorporate two processing loops, such as described with reference to FIG. 3, FIG. 4, FIG. 5, and FIG. 6. The ADC 810 may also incorporate monitoring and adjustment capabilities described with reference to FIG. 2 and FIG. 7. The universal nature of the ADC 810 in supporting different topologies benefits end users in that the end user does not need to be aware of the microphone topology and benefits manufacturers in that the manufacture may switch microphone suppliers during production of an electronic device without also needing to change the ADC 810. Further, when the microphone is an AC-coupled topology, the interface between the ADC 810 and the microphone does not require coupling capacitors, such as capacitors 112 and 114 of FIG. 1A and FIG. 1B. Thus, the use of an ADC as disclosed herein can reduce space occupied by the microphone and ADC interface in an electronic device. Additional embodiments of an ADC or portions of an ADC that may be implemented in an electronic device, such as mobile device 802, are described below.

(33) FIG. 5 illustrates, and the description referencing FIG. 5 describes, use of a feedback path 540 under operation by the controller 550 to apply signals to the differential nodes at V.sub.xp and V.sub.xn, which are coupled to differential input nodes 302 and 304. In some embodiments, digital-to-analog converters (DACs) of the feedback path 540 may be used as an auxiliary digital-to-analog converter (DAC) to provide compensation for common mode and differential mode mismatches. In some of these embodiments, the auxiliary DACs may be controlled based on a measurement from a common mode (CM) sense node. A CM sense node may be provided through two or more switches coupled between the differential inputs. One such embodiment is shown in FIG. 9 using shorting phase switches. FIG. 9 is a circuit schematic illustrating front-end switches for an analog-to-digital converter (ADC) with shorting phase switches configured to provide a sense node according to one embodiment of the disclosure. A circuit 900 includes two shorting switches 912 and 914, which may be operated, such as by a controller (not yet shown), to short two input sampling caps during a second clock phase of operation. A sense node 916 between the two shorting switches 912 and 914 may provide a common mode (CM) sense node.

(34) In particular, a voltage at the sense node 916 may provide data regarding an average voltage between the input nodes 902 and 904 during certain times of operation of the circuit 900. The shorting switches 912 and 914, along with any parasitic capacitance (not shown) between the switches 912 and 914, creates a switched-capacitor (SC) resistor. The SC resistor may have a large resistance value because the value is inversely proportional to the small parasitic cap value. The embodiment of FIG. 9 uses switches to create two large resistors for providing the CM sense node. When the switches 912 and 914 are made conductive, the middle node 916 stabilizes to a voltage level that is approximately the average of the input voltage at input nodes 902 and 904.

(35) Input from the sense node 916 may be provided to a controller to operate DACs in a feedback path of an ADC. One embodiment of an ADC implementing feedback based on a CM sense node along with interface detection hardware similar to that described with reference to FIG. 3 or FIG. 5 is shown in FIG. 10. FIG. 10 is a circuit schematic illustrating interface detection and compensation for an analog-to-digital converter (ADC) according to one embodiment of the disclosure. Although a particular ADC configuration is shown in FIG. 10, the sense node and/or controller described herein may be implemented in other ADC configurations, including switched-capacitor ADC circuits and continuous-time ADC circuits.

(36) An analog-to-digital converter (ADC) circuit 1000 includes a first set of shorting switches 1012 and 1014 coupled on a first side of sampling capacitors 1022 and 1024, respectively. The shorting switches 1012 and 1014 couple differential input nodes 1002 and 1004 to a sense node 1016. The circuit 1000 also includes a second set of shorting switches 1032 and 1034 coupled on a second side of sampling capacitors 1022 and 1024, respectively. The shorting switches 1032 and 1034 couple the differential input to a node 1036, and the node 1036 may be the common mode V.sub.cm voltage.

(37) The sense nodes 1016 may be measured and used to determine mismatch between an external common mode V.sub.cm,p and an internal common mode V.sub.cm,i. The external common mode V.sub.cm,p may be monitored by controlling the switches 1012 and 1014 to enter conducting mode to allow the sense node 1016 to equilibriate to an average voltage between the differential input nodes 1002 and 1004 external to the ADC 1000. A digital-to-analog converter (DAC) 1042 may measure the external common mode V.sub.cm,p values. The ADC 1042 may generate a common mode value D.sub.cm based on the V.sub.cm,i and V.sub.cm,p values. That common mode value D.sub.cm may be provided to a controller 1044. Mismatch between the V.sub.cm,i and V.sub.cm,p values create a differential signal that may appear at an output of the circuit 1000 or create noise in the output of the circuit 1000, such that the output of the circuit 1000 may be improved by detecting the mismatch and compensating for the mismatch.

(38) Compensation may be obtained through the feedback path 1060. The compensation may be provided through auxiliary DAC 1062 according to a digital code selected by the controller 1044 according to monitoring of the D.sub.cm and D.sub.main outputs. The differential input signal may be processed through ADC components 1050, such as through sampling capacitors 1022 and 1024, a comparator 1052, other loop filter components 1054, and a quantizer 1056 to generate a quantized output D.sub.main. The quantized output D.sub.main may be provided to the controller 1044 and used by the controller 1044 to generate a digital output D.sub.out of the circuit 1000. The controller 1044 may also use the quantized output D.sub.main to generate control signals for controlling the feedback path 1060. The feedback path 1060 may include an auxiliary DAC 1062. The feedback path 1060 may also include main DAC 1064, which receives the quantized output D.sub.main and feeds the D.sub.main value back to the ADC 1000. The controller 1044 may generate control signals for operating the auxiliary DAC 1062, which applies a signal to the internal CM sense nodes to compensate for CM mismatch.

(39) The controller 1044 may be configured to process the microphone interface configuration. The interface configuration may be determined, in part, from the quantizer 1056 output. The quantizer 1056 digital output code represents the differential-mode (DM) representation of the inputs. That is, after filtering quantization noise, the quantized output D.sub.main has V.sub.ipV.sub.in information, where V.sub.ip is an input at node 1002 and V.sub.in is an input at node 1004. The interface configuration may also be determined, in part, from the ADC 1042 output, which includes information from sense nodes 1016. By digitizing the sense node 1016 voltages, the controller 1044 may have the common-mode (CM) information, e.g. an indication of the value (V.sub.ip+V.sub.in)/2, regarding the differential input voltages at input nodes 1002 and 1004. Using this DM and CM information, the controller 1044 may determine the interface configuration (e.g., either fully-differential FD or pseudo-differential PD), and the controller 1044 may also determine possible DM or CM mismatch of the differential input signals at input nodes 1002 and 1004.

(40) The controller 1044 may determine the microphone is in pseudo-differential (PD) configuration when the DM output is at a mid-code centered output code and the CM data indicates an AC signal term appears at the sense node. If a pseudo-differential (PD) configuration is not detected, then the controller 1044 may determine that the microphone is operating in a fully-differential (FD) configuration. The controller 1044 may determine an AC mismatch is present when the CM data includes an AC signal term and the DM data has no code shift. The controller 1044 may determine a DC mismatch when the CM data does not indicate an AC signal term and the DM data has a code shift. The controller 1044 may determine an AC and DC mismatch is present when the CM data indicates an AC signal term and the DM data has a code shift. In any of these scenarios, the AC signal term on the CM input may be proportional to the input AC mismatch amplitude, and the code shift on the DM input may be proportional to the DC mismatch.

(41) One method for operation of the controller 1044 is shown in FIG. 11. FIG. 11 is a flow chart illustrating an example method for determining microphone configuration and applying mismatch compensation according to one embodiment of the disclosure. A method 1100 begins at block 1102 with determining a microphone configuration based on common mode (CM) data and differential mode (DM) data. The CM data may be received as a signal indicative of a voltage level at a CM sense node, such as in the signal D.sub.cm from ADC 1042 in FIG. 10. The DM data may be received as a signal from a quantizer in the differential mode path, such as the signal D.sub.main from the quantizer 1056 in FIG. 10. Then, the method 1100 continues to block 1104, to determine undesired effects within the ADC from the microphone input. For example, block 1104 may include determining the presence of an AC or DC mismatch between the differential input nodes and/or the between the internal and the external common mode. Next, at block 1106, the method 1100 may include controlling components of the ADC, such as an auxiliary DAC, to compensate for the undesired effects of block 1104. For example, the auxiliary DAC 1062 may be controlled to apply a signal to the differential input of the ADC to compensate for mismatches.

(42) The compensation of block 1106 may be applied to, for example, cancel a mismatched portion of input transferred charge. The total ADC input path charge for the differential inputs may be given by q.sub.i,p and q.sub.i,n as shown below:

(43) $q_{i,p}=C_i\left\{V_{\mathrm{DMi}}+\frac{V_{\mathrm{CMi}}+V_{\mathrm{DMi}}}{2}\right\}$$q_{i,n}=C_i\left\{-V_{\mathrm{DMi}}-\frac{V_{\mathrm{CMi}}+V_{\mathrm{DMi}}}{2}\right\}$
The DAC path charges of the differential inputs may be given by q.sub.dac,p and q.sub.dac,n as shown below:
q.sub.dac,p=C.sub.dac,main.Math.V.sub.refn,main(D.sub.main)+C.sub.dac,aux.Math.V.sub.refn,aux(D.sub.aux)
q.sub.dac,n=C.sub.dac,main.Math.V.sub.refp,main(D.sub.main)+C.sub.dac,aux.Math.V.sub.refp,aux(D.sub.aux)
An auxiliary DAC may be controlled to cancel the mismatched portion of the input transferred charge

(44) $\left(\frac{V_{\mathrm{CMi}}+V_{\mathrm{DMi}}}{2}\right).$
In one embodiment, the controller 1044 may generate a digital code value D.sub.aux for output to the auxiliary DAC 1062 that causes the auxiliary DAC 1062 to apply sufficient charge to cancel the mismatched portion of the input transferred charge.

(45) In some embodiments, the controller 1044 may take specific actions as part of the compensation step at block 1106. In the following examples, V.sub.CM refers to an external common mode, and V.sub.cm,i and V.sub.cm,p refer to the common mode at the inputs V.sub.in and V.sub.ip, respectively. For example, when D.sub.cm has only a DC term (that may be proportional to V.sub.cm,iV.sub.cm) and D.sub.main does not have a DC shift, the controller 1044 may determine the interface is fully differential (FD) with matched DC and AC values, and thus the generated D.sub.aux output may be neutral (such as set at a mid-code). As another example, when D.sub.cm has only a DC term (that may be proportional to V.sub.cm,iV.sub.cm+V.sub.cm,i/2) and D.sub.main has a DC shift (that may be proportional to V.sub.cm,i), the controller 1044 may determine the interface is fully differential (FD) and the input DC values are mismatched, and thus the generated D.sub.aux output may be selected to compensate the undesired charge proportional to V.sub.cm,i/2. As another example, when D.sub.cm has a DC term (that may be proportional to V.sub.cm,iV.sub.cm) and an AC term (that may be proportional to V.sub.dm,i) and D.sub.main does not have a DC shift, the controller 1044 may determine the interface is fully differential (FD) with matched DC input values but mismatched AC values, and thus the generated D.sub.aux output may be selected to compensate for the undesired charge proportional to V.sub.dm,i/2. As a further example, when D.sub.cm has a DC term (that may be proportional to V.sub.cm,iV.sub.cm+V.sub.cm,i/2) and an AC term (that may be proportional to V.sub.dm,i) and D.sub.main has a DC shift, the controller 1044 may determine the interface is fully differential (FD) with mismatched AC and DC values, and thus the generated D.sub.aux output may be selected to compensate the undesired charge proportional to (V.sub.cm,i+V.sub.dm,i)/2. As another example, when D.sub.cm has a DC term (that may be proportional to V.sub.cm,i/2V.sub.cm) and an AC term (that may be proportional to V.sub.dm,i/2), D.sub.main has no DC shift, D.sub.cm has a high DC term, and D.sub.cm has a high (e.g., >=V.sub.dm,i/2) AC term, the controller 1044 may determine the interface is pseudo differential (PD), and thus the generated D.sub.aux output may be selected to compensate the undesired charge proportional to V.sub.cm,i/2 to remove the DC shift on active block outputs.

(46) One example embodiment of determining undesired effects and applying compensation is described in more detail with reference to FIG. 12. FIG. 12 is a flow chart illustrating an example method for compensating undesired effects in an analog-to-digital converter (ADC) according to one embodiment of the disclosure. A method 1200 may begin at block 1202 with receiving common mode (CM) data and differential mode (DM) data. The received CM data and DM data may be, for example, an average of the differential input node voltages and a difference of the differential input node voltages, respectively. Then, at block 1204, undesired effects, such as common mode (CM) and/or differential mode (DM) mismatches may be determined. The CM mismatch and DM mismatch may be two unknowns calculated based, in part, on the received CM data and DM data from block 1202. Next, at block 1206, a control signal may be generated for output to a digital-to-analog converter (DAC), in which the control signal is selected such that the DAC provides compensation for at least some of the undesired effects determined at block 1204. For example, the DAC may be controlled to neutralize DC mismatch between the differential inputs.

(47) The CM data received at block 1202 may be received from a CM sense node within an ADC, such as the CM sense node 1016 of FIG. 10. One example method for obtaining the CM data is described in more detail with reference to FIG. 13. FIG. 13 is a flow chart illustrating an example method for sensing common mode (CM) data in an analog-to-digital converter (ADC) according to one embodiment of the disclosure. A method 1300 may begin at block 1302 with receiving a differential input through two input nodes coupled to two sampling capacitors of a switched capacitor circuit. For example, a differential input may be received at input nodes 1002 and 1004 coupled to sampling capacitors 1022 and 1024 of FIG. 10. Then, at block 1304, two or more switches may be controlled to sample the two sampling capacitors such that an average voltage is generated at an output node between the two or more switches. For example, switches 1012 and 1014 may be controlled to switch to a conducting state to sample an average voltage of sampling capacitors 1022 and 1024.

(48) The schematic flow chart diagrams of FIG. 2, FIG. 4, FIG. 11, FIG. 12, and FIG. 13 are generally set forth as a logical flow chart diagram. As such, the depicted order and labeled steps are indicative of aspects of the disclosed method. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. Additionally, the format and symbols employed are provided to explain the logical steps of the method and are understood not to limit the scope of the method. Although various arrow types and line types may be employed in the flow chart diagram, they are understood not to limit the scope of the corresponding method. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the method. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown.

(49) The operations described above as performed by a controller may be performed by any circuit configured to perform the described operations. Such a circuit may be an integrated circuit (IC) constructed on a semiconductor substrate and include logic circuitry, such as transistors configured as logic gates, and memory circuitry, such as transistors and capacitors configured as dynamic random access memory (DRAM), electronically programmable read-only memory (EPROM), or other memory devices. The logic circuitry may be configured through hard-wire connections or through programming by instructions contained in firmware. Further, the logic circuitry may be configured as a general purpose processor capable of executing instructions contained in software. If implemented in firmware and/or software, functions described above may be stored as one or more instructions or code on a computer-readable medium or in the memory circuitry. Examples include non-transitory computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise random access memory (RAM), read-only memory (ROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc includes compact discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks and Blu-ray discs. Generally, disks reproduce data magnetically, and discs reproduce data optically. Combinations of the above should also be included within the scope of computer-readable media.

(50) In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

(51) Although the present disclosure and certain representative advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. For example, although analog-to-digital converters (ADCs) are described throughout the detailed description, aspects of the invention may be applied to the design of other converters, such as digital-to-analog converters (DACs) and digital-to-digital converters, or other circuitry and components based on delta-sigma modulation. As another example, although microphone interfaces for analog-to-digital converters (ADCs) are described herein, the ADCs disclosed herein may be applied to any analog input device. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.