Mismatch and inter symbol interference (ISI) shaping using dynamic element matching

Abstract

The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of on and off transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.

Claims

1. A data converter comprising: a digital decoder configured to control a plurality of on and off transitions of an input signal such that an output signal does not contain inter symbol interference and mismatch error; and a transition shaper circuit wherein the transition shaper circuit is configured to select a sequence of on transitions that is formed by taking a first order difference of the input signal on each conversion cycle to which a constant value C is added.

2. The data converter of claim 1 wherein the decoder is configured to control the transitions such that the transitions are not correlated with the input signal.

3. The data converter of claim 1 wherein the decoder is adapted to select a plurality of elements that contribute to the output signal for a conversion cycle.

4. The data converter of claim 1 wherein the digital decoder is configured to select a maximum number of on transitions available for each conversion cycle when rate of change of the input signal is positive.

5. The data converter of claim 1 wherein the digital decoder is configured to select a minimum number of on transitions available for each conversion cycle when rate of change of the input signal is negative.

6. The data converter of claim 1 wherein the digital decoder is configured to select a minimum number of off transitions available for each conversion cycle when rate of change of the input signal is positive.

7. The data converter of claim 1 wherein the digital decoder is configured to select a maximum number of off transitions available for each conversion cycle when rate of change of the input signal is negative.

8. The data converter of claim 1 wherein the transition shaper circuit is configured to select a sequence of on transitions that is formed by taking a first order difference of the input signal on each cycle to which a constant value C is added and wherein the off transitions can be set to a constant C.

9. The data converter of claim 1 wherein the transition shaper circuit is configured to select a sequence of off transitions that is formed by taking a first order difference of the input signal on each cycle to which a constant value C is added.

10. The data converter of claim 1 wherein the transition shaper circuit is configured to select a sequence of off transitions that is formed by taking a first order difference of the input signal on each cycle to which a constant value C is added and wherein the on transitions can be set to a constant C.

11. The data converter of claim 1 wherein the transition shaper circuit comprises an ISI shaper module configured to determine a number of elements to turn on and off and a mismatch shaper module configured to determine which elements to turn on and off.

12. A Digital to Analog Converter comprising a data converter as claimed in claim 1.

13. A digital decoder for use in a data converter as claimed in claim 1, and configured to control a number of on and off transitions of an input signal such that an output signal does not contain inter symbol interference and mismatch error.

14. A data converter comprising: a digital decoder configured to control a plurality of on and off transitions of an input signal such that an output signal does not contain inter symbol interference and mismatch error; and a high pass filter adapted to supress errors at low frequencies around a band of interest.

15. A data converter comprising: a digital decoder configured to control a plurality of on and off transitions of an input signal such that an output signal does not contain inter symbol interference and mismatch error, wherein the digital decoder is configured to combine an ISI and Mismatch shaper with a second feedback loop to shape transition mismatch errors out of band.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be more clearly understood from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:

(2) FIG. 1 illustrates a DAC signal flow according to one embodiment of the invention,

(3) FIG. 2 illustrates Inter Symbol Interference (ISI) error for a single pulse;

(4) FIG. 3 illustrates graphical waveforms of ISI error;

(5) FIG. 4 illustrates transition mismatch error;

(6) FIG. 5 illustrates a flowchart of a decoder algorithm according to one embodiment;

(7) FIG. 6 illustrates a graphical representation of available on and off transitions;

(8) FIGS. 7(a) and 7(b) illustrates two circuits that can be used to select the appropriate number of transitions (T.sub.n);

(9) FIG. 8 illustrates a signal flow diagram for combining both ISI and Mismatch shaper design; and

(10) FIG. 9 illustrates an extended mismatch and ISI shaping loop to incorporate ISI error shaping and transition mismatch error shaping.

DETAILED DESCRIPTION OF THE DRAWINGS

(11) FIG. 1 shows a signal flow for a Digital to Analog Converter (DAC) in a noise shaping converter, 10. The output x[k] of the noise shaper 10 is mapped to a set of M 1-bit signals as given by Equation (1), where d.sub.i denotes the i.sup.th 1-bit signal, indexed from 1 to M where M is the number of elements in the DAC. Each element in the DAC is assigned a weight w.sub.i, which are then summed to form the output of the DAC y[k] as given by Equation (2).

(12) $\begin{array}{cc}x\left[k\right]=\underset{i=1}{\overset{M}{.Math.}}{d}_i\left[k\right]d_i\left\{0,1\right\}& \left(1\right)\\ y\left[k\right]=\underset{i=1}{\overset{M}{.Math.}}{d}_i\left[k\right]w_i& \left(2\right)\end{array}$

(13) During each DAC conversion cycle, a decoder 11 selects the number of DAC elements to turn on. Each time an element is turned on it forms a pulse with an amplitude, w.sub.i these pulses are then summed 12 to form the final DAC output 13. In a discrete time DAC, only the settled value of the pulse amplitude is summed.

(14) In continuous time DACs however, the DAC output is formed by summing the integrated values of the element pulses. This means that the value of the pulse over the entire conversion cycle is important. If the DAC element is assumed to turn on and off instantly, then the resulting pulse will have edges that are infinitely sharp. In this case the value of the DAC pulse remains the same irrespective of whether the element was previously on or off. In a real system however, the DAC elements will have a finite rise time and fall time. This is illustrated in FIG. 2 where an error term is assigned to the rising and falling edges of the DAC. These error terms are used to represent the departure of the actual DAC pulse from the ideal DAC pulse. A difference in the magnitude of these errors will result in the value of the DAC pulse being dependant on whether the DAC element was on or off during the previous conversion cycle. This is illustrated in FIG. 3. The resulting error is commonly known as inter symbol interference (ISI) error, which leads to noise and distortion at the output 13 of the DAC.

(15) An additional source of error termed transition mismatch error can be attributed to the transitioning of the DAC elements. This error arises due to variations in the values of the rise and fall errors between elements, this transition mismatch error is illustrated in FIG. 4.

(16) In one embodiment there is provided a digital solution that removes the effects of ISI and mismatch error from the signal band. In one embodiment the solution is a module with a number of computer implemented instructions or an algorithm that can be implemented using standard digital logic. An advantage of the digital implementation is that the solution can be scaled more easily with shrinking geometry nodes, making it attractive for CMOS implementations. In addition, the technique does not have the associated drawbacks of analog solutions such as the requirement for linear switches and accurate capacitor sizes. In comparison to traditional layout techniques that aim to mitigate the ISI problem by ensuring the error on the elements is minimized; the scheme of the present invention has an advantage of allowing the DAC to select elements such that the associated errors are removed from the signal band. This means that the invention facilitates the DAC to accurately convert high resolution signals in the presence of both ISI and mismatch error.

(17) In addition, the solution does not require special manipulation of the DAC elements during fabrication which has the further advantage of making the layout task easier. The data converter of the invention does not require doubling the number of elements as is the case in dual return to zero (DRTZ) DACs. This provides a significant improvement in terms of DAC area and power consumed. The solution improves on other digital techniques used for shaping mismatch and ISI by directly controlling the number of elements that transition within a window of available transitions; this provides for more effective shaping of ISI and mismatch error leading to the proposed technique achieving higher performance when compared to other state of the art methods.

(18) The invention removes both the mismatch and ISI error that is present at the output of the DAC by shaping the errors out of band. This is achieved by implementing a decoder that controls both the number of elements that transition and which elements are selected during each DAC conversion cycle.

(19) In one embodiment the solution is a digital decoder that controls the DAC operation in four ways: 1. The decoder selects the number of elements that contribute to the DAC output for each conversion cycle. 2. The decoder selects which elements are turned on and off so that the mismatch on these elements is shaped out of band. 3. The decoder deterministically selects the number of elements that transition on each conversion cycle shaping the ISI error to the same performance as the modulator input. 4. The decoder controls which elements to turn on and off at each conversion cycle so that the transition mismatch error is shaped out of band.

(20) The flow chart in FIG. 5 illustrates the operation of the decoder. The decoder algorithm can be broken down into a number of processes: 1. Calculation of available transitionsIn step 20 an algorithm uses the mathematical equations (36) to calculate the available number of on and off transitions for each conversion cycle. By defining T.sub.n,max, T.sub.n,min, T.sub.f,max, and T.sub.f,min the algorithm can determine all the available on and off transitions.

(21) $\begin{array}{cc}{T}_{n,\max }\left[k\right]=\{\begin{array}{cc}M-x\left[k-1\right]& \mathrm{if}x\left[k\right]+x\left[k-1\right]>M\\ x\left[k\right]& \mathrm{if}x\left[k\right]+x\left[k-1\right]M\end{array}& \left(3\right)\\ T_{n,\min }\left[k\right]=\{\begin{array}{cc}x\left[k\right]-x\left[k-1\right]& \mathrm{if}x\left[k\right]>x\left[k-1\right]\\ 0& \mathrm{if}x\left[k\right]x\left[k-1\right]\end{array}& \left(4\right)\\ T_{f,\max }\left[k\right]=\{\begin{array}{cc}M-x\left[k\right]& \mathrm{if}x\left[k\right]+x\left[k-1\right]>M\\ x\left[k-1\right]& \mathrm{if}x\left[k\right]+x\left[k-1\right]M\end{array}& \left(5\right)\\ T_{f,\min }\left[k\right]=\{\begin{array}{cc}x\left[k-1\right]-x\left[k\right]& \mathrm{if}x\left[k-1\right]>x\left[k\right]\\ 0& \mathrm{if}x\left[k-1\right]x\left[k\right]\end{array}& \left(6\right)\end{array}$ Where T.sub.n,max is the maximum number of on transitions, T.sub.n,min is the minimum number of on transitions, T.sub.f,max is the maximum number of off transitions and T.sub.f,min is the minimum number of off transitions. FIG. 6 is a graphical representation of the available on and off transitions. 2. Choosing the number of transitionsIn step 21, the algorithm is configured to deterministically select the number of transitions that occur during each conversion cycle of the DAC. The algorithm can be used to exert explicit control over either the on or off transitions resulting in the mitigation of the ISI error. In one embodiment the algorithm controls the number of on transitions denoted by T.sub.n that occur during each conversion cycle. The value T.sub.n will be chosen from the available transitions as defined in step 1. The decoder must choose T.sub.n such that the sequence of T.sub.n over time forms a signal that does not contain noise or distortion in the signal band. The decoder then generates a second signal R.sub.n by subtracting T.sub.n from the number of elements required to be on. This signal represents the number of elements that are to remain on during the conversion cycle. It should be noted that exerting control over either the on or off transitions in the above manner will result in the ISI error being shaped. A further embodiment of the algorithm could equally control the off transitions to shape ISI error. 3. Selection of elementsOn each cycle, the decoder splits the elements into two groups in step 22. The first group contains the elements that were off in the previous conversion cycle 23a. From this group the decoder selects T.sub.n of these elements to be turned on while keeping the remaining elements in the group off in step 24a. The second group contains the elements that were on during the previous DAC conversion cycle in step 23b. The decoder now selects R.sub.n of these elements to remain on and sets the remaining elements in the group to be off in 24b. The decoder then combines the output of both selections to form the final decoder output in step 25. It is important to note that while the decoder is restricted in the number of elements to turn on, and the number of elements to remain on, it has freedom in the choice of which elements within the group to select as long as the number of them selected is correct. To this extent the decoder can be combined with existing mismatch and transition error shaping algorithms. In this manner the decoder can be extended to provide suppression of mismatch and ISI error along with transition mismatch error.

(22) Generation of Transition Signal

(23) The function of the algorithm is to generate a sequence of on transitions that does not contain distortion or noise in the signal band. The decoder does this by seeking to maximize the number of on transitions when the rate of change of the signal is most positive and minimize the number of on transitions when the rate of change of the signal is most negative. To achieve this, the decoder must choose the number of on transitions from the set of available transitions. When the required number of on transitions is different from those available, the decoder will choose the closest value from the set of on transitions. The resulting error introduced into the sequence is fed back through a high pass filter. The objective of this filtering is to suppress the error at low frequencies around the band of interest.

(24) To generate the appropriate sequence of transitions, a circuit as proposed in FIG. 7(a) is used indicated generally by the reference numeral 30 configured to act as a transition shaper circuit. This transition shaper circuit 30 is similar to a conventional error feedback modulator loop. The input signal to the transition shaper is the first order difference of the modulator signal. The maximum (T.sub.n,max) and minimum (T.sub.n,min) number of on transitions is generated from the modulator signal by implementing equations (3) and (4). A modified quantizer 31 is used to select T.sub.n from the available on transitions. A constant value C is added to the input signal to form the signal T.sub.y which is used as input to the modified quantizer 31 whose operation is governed by equation (7). In this manner the decoder ensures that T.sub.n forms a signal that does not contain second or higher order distortion components. In addition, any error that occurs due to the difference between the available on transitions and the first order difference of the signal plus the constant C will be high pass filtered by filter 32; this means that the error will be suppressed at low frequencies close to the signal band and pushed to higher frequencies away from the band of interest.

(25) $\begin{array}{cc}{T}_n=\{\begin{array}{cc}{T}_{n,\max }& \mathrm{if}{T}_y{T}_{n,\max }\\ T_{n,\min }& \mathrm{if}{T}_y{T}_{n,\min }\\ T_y& \mathrm{otherwise}\end{array}& \left(7\right)\end{array}$

(26) FIG. 7(a) shows the signal flow diagram of the circuit used to select the appropriate number of transitions (T.sub.n). By extension, a simplified version of the method to choose the transitions is represented by FIG. 7(b), indicated by the reference numeral 40. The sequence of on transitions is formed by taking the first order difference of the input signal on each cycle to which a constant value C is added. The off transitions can be subsequently set to a constant C.

(27) Selection of Elements

(28) This section describes the selection of the elements so that the mismatch and ISI error is shaped out of band. To achieve this, a mismatch and ISI shaping loop as shown in FIG. 8, indicated by the reference numeral 50. At each cycle the ISI shaper splits 51 the modulator signal x[k] into two signals; T.sub.n representing the number of elements to turn on and R.sub.n representing the number of elements to remain on where R.sub.n[k]=x[k]T.sub.n[k]. For each conversion cycle, a Vector Quantizer A (VQA) sets T.sub.n values in vector D.sub.Tn to 1. Similarly a Vector Quantizer B (VQB) sets R.sub.n values in vector D.sub.Rn to 1. The output vector of a decoder D, 52 is formed by the summation of D.sub.Tn and D.sub.Rn. VQA only chooses to turn on elements that were previously off and similarly VQB only chooses to keep on elements that were previously on. These VQA & VQB actions are ensured by a feedback loop containing the element selection vector D, 53 which is used to select the appropriate signals.

(29) Logic blocks 54a and 54b separate the vector output of the mismatch shaping filter S.sub.f into two signals; S.sub.Tn which contains the S.sub.f values pertaining to the elements that are currently off and so become available to be turned on; and S.sub.Rn which contains the S.sub.f values of the elements that are currently on and are available to remain on. VQA chooses which elements in vector D.sub.Tn to set to 1 with preference given to the elements in vector D.sub.Tn with the largest corresponding values in the vector S.sub.Tn. Likewise VQB chooses which elements in vector D.sub.Rn to set to 1 based on the values contained in S.sub.Rn. In summary the ISI shaper determines the number of elements to turn on and off and the mismatch shaper determines which elements to turn on and off. This combined operation results in both mismatch and ISI shaping.

(30) To provide shaping of the transition mismatch error, a second loop can be added to the system as shown in FIG. 9, which is similar to FIG. 8. The loop accumulates the transition density of each element using a transition detector module 60. The transition density is defined as the number of transitions that occur over time. The loop attempts to keep the transition density of each element constant. In addition to this, it will seek to shape any deviation between the actual element transition density and the predefined transition density. This action has the effect of shaping transition mismatch error. By combining this loop with the ISI shaper described previously the decoder can now select the element transitions such that the transition error is shaped out of band.

(31) Results

(32) To demonstrate the effectiveness of the proposed technique, a model of a data converter as shown in FIG. 1 is used. This model comprises of a Sigma Delta modulator 10, a decoder 11, and a DAC 12. Without any error present on the DAC 12, the converter achieves a SINAD figure of 100 dB and SFDR figure of 114 dB.

(33) To simulate the inaccuracies present on a real DAC, randomly distributed errors are added to each DAC element. These errors are illustrated in FIG. 2b where .sub.1 represents the mismatch error, .sub.ni represents the error on the rising edge of the element, and .sub.fi represents the error on the falling edge of the DAC element. The values of the errors are scaled with respect to a unit element value. The mismatch error (.sub.i) is set to represent a deviation of 1% of the unit element value. With respect to the ISI error the difference in magnitude between the error on the rising edge (.sub.ni) and error on the falling (.sub.fi) edge of the elements is scaled to 1% of the unit element value. The transition mismatch error is scaled to 0.1% of the unit element value. Table 1 compares the SINAD and SFDR performance of a thermometer decoder, 1.sup.st order mismatch shaper, and the proposed mismatch and ISI shaper for the error values specified in the table. Table 1 illustrates the performance of the ISI error mitigation and Mismatch shaper invention performance with error values specified.

(34) TABLE-US-00001 TABLE 1 MM ISI TE MM ISI TE MM ISI TE MM ISI TE 1% 0% 0.0% 0% 1% 0.0% 1% 1% 0.0% 1% 1% 0.1% Thermometer SINAD 63 dB 82 dB 62 dB 59 dB Decoder SFDR 65 dB 98 dB 64 dB 61 dB 1.sup.st Order SINAD 96 dB 47 dB 47 dB 47 dB Mismatch Shaper SFDR 105 dB 49 dB 49 dB 49 dB Mismatch & ISI SINAD 90 dB 100 dB 90 dB 90 dB Shaper SFDR 103 dB 114 dB 103 dB 101 dB MM: Mismatch Error ISI: Intersymbol interference error TE: Transition Error

(35) It will be appreciated that the invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling converters. The algorithm extends the ability of conventional mismatch shaping selection logic by deterministically controlling the element transitions the DAC makes in response to an input signal. Utilizing this new technique, the dynamic element matching logic can spectrally shape both element mismatch error and the rise & fall time errors commonly known as inter symbol interference (ISI). This technique results in a reduction in DAC non-linearity and achieves an increase in SNR/SINAD/SNDR without the need for strict matching of the DAC elements.

(36) The invention presents a design of a DEM decoder that provides optimal ISI error mitigation and is suitable for shaping both ISI and mismatch error. The algorithm hereinbefore described controls the number of on transitions such that they are maximized when the rate of change of the signal is most positive and minimized when it is most negative.

(37) Alternatively, another embodiment controls the number of off transitions such that they are minimized when the rate of change of the signal is most positive and maximized when it is most negative. In addition to this, a noise shaping loop ensures that any error that occurs as a result of this transition selection will be shaped out of band. The algorithm can be extended to shape both the mismatch error and the transition error The results show that since the technique controls the number of transitions from the available window of transitions while also shaping the individual elements, it achieves the best performance in the presence of both mismatch and ISI errors when compared to prior art techniques.

(38) In the context of the present invention it should be noted that while the description has focused on oversampling and noise shaping converters, the proposed DEM scheme is not strictly limited to this class of converter. This technique can be applied to any class of converter that possesses redundancy in terms of both the signal bandwidth and DAC element permutations.

(39) The embodiments in the invention described with reference to the drawings comprise a computer apparatus and/or processes performed in a computer apparatus. However, the invention also extends to computer programs, particularly computer programs stored on or in a carrier adapted to bring the invention into practice. The program may be in the form of source code, object code, or a code intermediate source and object code, such as in partially compiled form or in any other form suitable for use in the implementation of the method according to the invention. The carrier may comprise a storage medium such as ROM, e.g. CD ROM, or magnetic recording medium, e.g. a memory stick or hard disk. The carrier may be an electrical or optical signal which may be transmitted via an electrical or an optical cable or by radio or other means.

(40) In the specification the terms comprise, comprises, comprised and comprising or any variation thereof and the terms include, includes, included and including or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

(41) The invention is not limited to the embodiments hereinbefore described but may be varied in both construction and detail.