VARIABLE FREQUENCY RC OSCILLATOR

Abstract

An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.

Claims

1. An oscillator circuit having a programmable output frequency comprising: a first delay section having an input end and an output end, the first delay section having a negative gain between the input end and the output end, the first delay section having a variable delay that is set by a control signal provided to the first delay section; a second delay section electrically connected in series with the first delay section, the second delay section having an input end and an output end, the second delay section having a negative gain between the input end and the output end, the second delay section having a fixed delay; and a circuit output for an output signal having a frequency that is a function of the delay due to the first delay section and the second delay section, the circuit output comprising the output end of the second delay section.

2. The circuit of claim 1, wherein the first delay section comprises: a first RC network comprising a resistor and a variable capacitor; and a second RC network connected in series with the first RC network and comprising a resistor and a variable capacitor, a delay of the first delay section determined based on capacitances of the variable capacitors of the first and second RC networks.

3. The circuit of claim 2 wherein the control signal sets the capacitance of the variable capacitor of the first RC network, and an additional control signal sets the capacitance of the variable capacitor of the second RC network.

4. The circuit of claim 1, wherein the first delay section comprises an RC network comprising a resistor and a variable capacitor, wherein the control signal provided to the first delay section sets a capacitance of the variable capacitor of the first RC network, a delay of the first delay section determined based on the capacitance of the variable capacitor.

5. The circuit of claim 1, wherein the first delay section comprises a plurality of switched capacitors, wherein the control signal selectively sets each of the plurality of switched capacitors to an ON state or an OFF state.

6. The circuit of claim 5, wherein when a switched capacitor is in the ON state, the switched capacitor has a node electrically connected to a DC voltage.

7. The circuit of claim 5, wherein when a switched capacitor is in the ON state, the switched capacitor has a node electrically connected to ground potential.

8. The circuit of claim 5, wherein the control signal is an n-bit word.

9. The circuit of claim 1, wherein the second delay section comprises an RC network comprising a fixed value resistive component and a fixed value capacitive component.

10. The circuit of claim 9, wherein at least one node of the fixed value capacitive component swings above supply voltage of the oscillator circuit.

11. The circuit of claim 10, wherein the at least one node of the fixed value capacitive component swings below ground potential.

12. The circuit of claim 1, wherein the first delay section is electrically connected to the circuit output via the second delay section in a feedback loop.

13. An oscillator circuit comprising: a first delay section having an input end and an output end, the first delay section having a negative gain between the input end and the output end, the first delay section comprising a first RC network comprising a resistor and a variable capacitor and a second RC network connected in series with the first RC network and comprising a resistor and a variable capacitor; at least one control signal provided to at least the variable capacitor of the first RC network to set a delay of the first delay section; a second delay section electrically connected in series with the first delay section, the second delay section having an input end and an output end, second delay section having a negative gain between the input end and the output end, the second delay section having a fixed delay; and a circuit output for an output signal having a frequency that is a function of the delay due to the first delay section and the second delay section, the circuit output comprising the output end of the second delay section.

14. The circuit of claim 13, wherein each of the variable capacitors in the first and second RC networks in the first delay section comprises a plurality of switched capacitors, wherein the control signal provided to the programmable delay stage selectively sets each of the plurality of switched capacitors to an ON state or an OFF state.

15. The circuit of claim 14, wherein when a switched capacitor is in the ON state, a node of the switched capacitor is electrically connected to a DC voltage.

16. The circuit of claim 14, wherein when a switched capacitor is in the ON state, a node of the switched capacitor is electrically connected to ground potential.

17. The circuit of claim 13, wherein the control signal is provided to the variable capacitor in the first RC network, the circuit further comprising an additional control signal provided to the variable capacitor in the second RC network.

18. The circuit of claim 13, wherein the first delay section further comprises at least a third RC network connected in series with the second RC network and comprising a resistor and a variable capacitor.

19. The circuit of claim 13, wherein the second delay section comprises an RC network comprising a fixed value resistive component and a fixed value capacitive component, wherein at least one node of the capacitive component swings above supply voltage of the oscillator circuit.

20. The circuit of claim 19, wherein the at least one node of the capacitive component swings below ground potential.

21. An oscillator circuit comprising: a first inverter stage; a second inverter stage having an input electrically connected to an output of the first inverter stage, the second inverter stage having an output for an output signal of the oscillator circuit; an RC circuit comprising a resistor element connected to a capacitive element, the RC circuit electrically connected between the input and output of the second inverter stage, wherein at least one node of the capacitive element of the RC circuit swings above supply voltage of the oscillator circuit and below ground potential; and at least one variable delay stage having a delay that is set by a control signal provided to the at least one variable delay stage, the at least one variable delay stage electrically connected between a node in the RC circuit that connects the resistor element and the capacitive element and an input of the first inverter stage, a frequency of the output signal being dependent on a delay of the at least one variable delay stage.

22. The circuit of claim 21, further comprising at least one additional variable delay stage connected in series with the at least one variable delay stage, and having a delay that is dependent on a control signal provided to the at least one additional variable delay stage.

23. The circuit of claim 21, wherein the at least one node of the capacitive element corresponds to a node that connects the resistor element and the capacitor element.

24. The circuit of claim 21, wherein the at least one variable delay stage comprises a resistor and a variable capacitor, wherein the control signal provided to the at least one variable delay stage sets a capacitance of the variable capacitor, wherein the delay of the at least one variable delay stage is dependent on the capacitance of the variable capacitor.

25. The circuit of claim 21, wherein the at least one variable delay stage comprises a plurality of switched capacitors, wherein the control signal sets each of the plurality of switched capacitors to an ON state or an OFF state.

26. The circuit of claim 25, wherein when a switched capacitor is in the ON state, a node of the switched capacitor is electrically connected to a DC voltage or to ground potential.

27. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, makes apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. Similar or same reference numbers may be used to identify or otherwise refer to similar or same elements in the various drawings and supporting descriptions. In the accompanying drawings:

[0024] FIGS. 1A and 1B show oscillator circuits in accordance with the present disclosure.

[0025] FIG. 2 shows an oscillator circuit in accordance with the present disclosure.

[0026] FIG. 2A shows details of a variable capacitor in accordance with the present disclosure.

[0027] FIG. 3 shows an oscillator circuit in accordance with the present disclosure.

[0028] FIG. 3A shows details of a variable capacitor in accordance with the present disclosure.

[0029] FIGS. 4A and 4B illustrate alternate embodiments in accordance with the present disclosure.

[0030] FIG. 5 shows an example of a conventional RC oscillator.

DETAILED DESCRIPTION

[0031] In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

[0032] FIG. 1A shows an electronic circuit 10 in accordance with an embodiment of the present disclosure. The electronic circuit 10 may include an oscillator circuit 102 and electronic circuitry 12. The oscillator circuit 102 may have an output 114 for an output signal (e.g., a clock signal 132), which for example, may be used by the electronic circuitry 12. The electronic circuit 10 may be a component in an electronic device (not shown). The oscillator circuit 102 may be powered by a source V.sub.DD and the electronic circuitry 12 may be powered by a source V.sub.DD1. In some embodiments, V.sub.DD may be the same as V.sub.DD1, and in other embodiments V.sub.DD may be different from V.sub.DD1.

[0033] The oscillator 102 may comprise a first delay section 104 and a second delay section 106 electrically connected in series with the first delay section 104. In accordance with the present disclosure, the first delay section 104 may be characterized by a negative gain between the input end of the first delay section 104 and the output end of the first delay section 104. With reference to FIG. 1A, for example, in some embodiments the first delay section 104 may include a delay stage 126 connected in series with an inversion stage 122. As discussed in more detail below, the first delay section 104 may be further characterized by having a variable delay. Further, by negative gain, we mean that a given positive change (say of the voltage) at the input end produces a negative change (of the voltage) at the output end.

[0034] The input end of the first delay section 104 may be defined by the input side of delay stage 126. The output end of the first delay section 104 may be defined by the output of the inversion stage 122. It will be clear from the discussion below that the gain of delay stage 126 is positive. The inversion stage 122 has a negative gain, and so the first delay section 104 has a negative gain. In some embodiments, the inversion stage 122 may comprise a single inverter as shown in FIG. 1A. In other embodiments, the inversion stage 122 may comprise any odd number of inverters, and in general any suitable circuitry that can provide a negative gain.

[0035] The second delay section 106 may likewise be characterized by a negative gain between its input end and its output end. In some embodiments, the second delay section 106 may include an inversion stage 124 connected across (in parallel with) a delay stage 128; for example, at terminals and of delay stage 128. The input and output ends of the second delay section 106 may be the input and output, respectively, of the inversion stage 124. The inversion stage 124 has a negative gain, and so the second delay section 106 has a negative gain. In some embodiments, the inversion stage 124 may comprise a single inverter as shown in FIG. 1A. In other embodiments, the inversion stage 124 may comprise any odd number of inverters, and in general any suitable circuitry that can provide a negative gain.

[0036] The first delay section 104 may be connected to the output 114 via the second delay section 106 to define a feedback loop around which oscillations can propagate to produce the clock signal 132. The frequency f.sub.CLOCK of the clock signal 132 is generally a function of the delay .sub.1 of the delay stage 128 and the delay .sub.2 of the delay stage 126. The clock signal 132 may be tapped out or otherwise produced at the output of the second inversion stage 124, as depicted in FIG. 1A. However, it is understood that the clock signal 132 may be obtained at other points 114 within the loop.

[0037] Referring to FIG. 1B, in some embodiments the delay stage 128 may comprise an RC network comprising a resistor R and a capacitor C. Terminal of the delay stage 128 may be connected to the resistor R and capacitor C may be connected to terminal . Terminal of the delay stage 128 may be connected to a node V.sub.X to which resistor R and capacitor C are connected. The delay .sub.1 of the RC network is generally a function of a time constant (sometimes referred to as the RC time constant) defined as RC, which represent respective element values of resistor R and capacitor C. In some embodiments, resistor R and capacitor C may be fixed-value elements. Accordingly, the delay stage 128 may provide a fixed delay.

[0038] It is noted that node V.sub.X is not connected to ground potential, as compared to other elements in the oscillator circuit 102 (e.g., inversion stages 122, 124, delay stage 126). Rather, node V.sub.X is a floating node, which means that the potential at node V.sub.X may vary as the voltage across capacitor C varies during operation of the oscillator circuit 102. For example, during operation the voltage at node V.sub.X may swing above and below the supply voltage in one half of a cycle of the clock signal 132 at the output 114, and may swing above and below ground potential in the other half of the cycle. This aspect of the present disclosure is discussed below.

[0039] Returning to FIG. 1A, in accordance with some embodiments, the delay stage 126 may have a variable (tunable, programmable) delay. The delay stage 126 may receive a selector input signal 112 to select or otherwise set the delay .sub.2 of the delay stage 126. In some embodiments, the selector input 112 may be a digital code. In accordance with the present disclosure, the selector input 112 may change in order to select a different delay .sub.2 for the delay stage 126 during operation of the electronic circuit 10. For example, the selector input 112 may provide different digital codes to the delay stage 126, thus allowing for on-the-fly selection of a delay .sub.2.

[0040] The frequency of oscillation in oscillator circuit 102 may be controlled according to the delays .sub.1 and .sub.2. The delay .sub.1 may be determined, for example, during the design phase by selecting appropriate element values for resistor R and capacitor C in the delay stage 128. The delay of .sub.2 may be set by providing a suitable selector input 112 to the delay stage 126. Since the delay .sub.2 of the delay stage 126 may be set on-the-fly, the frequency of clock signal 132 produced by oscillator circuit 102 may likewise be set on-the-fly, namely by providing a suitable selector input 112 to the delay stage 126.

[0041] FIG. 2 shows additional details for delay stage 126 of the first delay section 104 in accordance with some embodiments of the present disclosure. In some embodiments, for example, the delay stage 126 may comprise a high input impedance non-inverting input buffer 202 and a variable RC network 204. The supply (not shown) for input buffer 202 may be the V.sub.DD supply provided to the delay stage 126, as illustrated in FIG. 1A for example.

[0042] The variable RC network 204 may comprise a resistor R.sub.1 and a variable capacitor C.sub.1. The selector input 112 may be an n-bit signal bus that can be provided to the variable capacitor C.sub.1 to select or otherwise set a capacitance for the variable capacitor C.sub.1. The delay .sub.2 of delay stage 126 may be determined based on a time constant defined as RC, which are respective values of resistor R.sub.1 and variable capacitor C.sub.1. The delay .sub.2 may therefore be set depending on the capacitance setting of variable capacitor C.sub.1.

[0043] One of ordinary skill will appreciate that any suitable delay circuitry may be used for the delay stage 126. Merely to illustrate the point, in other embodiments for example, the delay stage 126 may employ a tunable current source to charge a fixed capacitor. The delay stage 126 may use a current starved inverter with a tunable current source and/or a tunable capacitor, and so on.

[0044] FIG. 2A shows additional details of the variable capacitor C.sub.1. In accordance with some embodiments, the variable capacitor C.sub.1 may include a set of n fixed value switched capacitive elements C.sub.x. The capacitive elements C.sub.x may be connected in parallel with each other. For example, each capacitive element C.sub.x may have a connection between resistor R.sub.1 and a ground potential connection via a corresponding switch M.sub.0-M.sub.n-1. It will be appreciated that in other embodiments, the capacitive elements C.sub.x may be arranged in connection topologies other than in parallel.

[0045] The capacitive elements C.sub.x may be realized using any semiconductor technology suitable for a given application of the oscillator circuit 102. Merely to illustrate this point, in various embodiments, capacitive elements C.sub.x may be PN junction capacitors, MOSFET gate capacitors, metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and so on. The capacitive elements C.sub.x may be based on the same semiconductor technology, or they may be based on different technologies. In some embodiments, each of the capacitive elements C.sub.x may have the same capacitance. In other embodiments, the capacitive elements C.sub.x may have different capacitances.

[0046] The capacitive elements C.sub.x may be selectively switched to ground potential via a set of corresponding switches M.sub.0-M.sub.n-1. The switches M.sub.0-M.sub.n-1 may be any suitable switching device. In some embodiments, for example, the switches M.sub.0-M.sub.n-1 may be semiconductor switches such as NMOS transistors shown in FIG. 2A, for instance; although in other embodiments other transistor technologies or designs may be used, such as NFETs for example. In some embodiments, all the switches M.sub.0-M.sub.n-1 may be based on the same technology, or they may be based on several different technologies. Each of the n signal lines that comprise the selector input 112 may be connected to a respective one of the switches M.sub.0-M.sub.n-1. For example, in FIG. 2A, each signal line of the selector input 112 is connected to a respective gate terminal of the switches M.sub.0-M.sub.n-1. The input to selector input 112 may be generated by digital logic or other suitable circuitry associated with the oscillator circuit 102 or with electronic circuit 10 (FIG. 1A).

[0047] In accordance with the present disclosure, the nodes of capacitive elements C.sub.x in FIG. 2A are not floating nodes as explained above in connection with node V.sub.X. Rather, in some embodiments, the nodes of capacitive elements C.sub.x may be electrically connected to or otherwise referenced to ground potential. In other embodiments, the capacitive elements C.sub.x may be electrically connected to or otherwise referenced to a DC voltage; e.g., a supply voltage such as V.sub.DD. More generally, one of skill in the art will appreciate that the capacitive elements C.sub.x may be electrically connected to any suitable low impedance node.

[0048] In operation, any one or more of the n signal lines in the selector input 112 may be asserted to turn ON their corresponding switches M.sub.0-M.sub.n-1, and hence the corresponding capacitive element C.sub.x. A switch (e.g., M.sub.0) that is in the ON state connects its corresponding capacitive element C.sub.x to the RC network 204 (switched on), and conversely a switch that is in the OFF state disconnects its corresponding capacitive element C.sub.x from the RC network 204 (switched off). If the capacitive elements C.sub.x are connected in parallel, as shown in FIG. 2A for example, the capacitance of variable capacitor C.sub.1 may be computed as the sum of the switched-on capacitive elements. Thus, the delay .sub.2 of the delay stage 126 may be set depending on which capacitive elements are switched on or switched off in the RC network 204.

[0049] In some embodiments, resistor R.sub.1 may be a fixed value element such as shown in FIG. 2A. In other embodiments (not shown), resistor R.sub.1 may be a variable resistor and capacitor C.sub.1 may be a fixed value element. In still other embodiments, resistor R.sub.1 may be a variable resistor and capacitor C.sub.1 may be a variable capacitor.

[0050] Referring to FIG. 3, in some embodiments in accordance with the present disclosure the first delay section 104 may comprise an additional delay stage 326 connected in series with the delay stage 126. An input inverter 322 may be provided to couple the oscillations produced at the output of delay stage 126 to the input of the additional delay stage 326; in other words, the inverter 322 keeps the oscillations going. An output inverter 324 may be provided to maintain a net negative gain between the input end and the output end of the first delay section 104. The supply (not shown) for input inverter 322 and output inverter 324 may be the same V.sub.DD supply provided to the delay stage 126, as illustrated in FIG. 1A for example. In some embodiments, the additional delay stage 326 can improve the noise performance of oscillator circuit 102.

[0051] The additional delay stage 326 may include a variable RC network 304 comprising a resistor R.sub.2 and a variable capacitor C.sub.2. A selector input 312 may comprise an m-bit signal bus that can be provided to the variable capacitor C.sub.2 to select or otherwise set a capacitance for the variable capacitor C.sub.2. The additional delay stage 326 may provide a delay .sub.3 that may be determined based on a time constant defined as RC, which are respective values of resistor R.sub.2 and variable capacitor C.sub.2. The delay .sub.3 provided by additional delay stage 326 may therefore be set depending on the capacitance setting of variable capacitor C.sub.2.

[0052] FIG. 3A shows additional details of the variable capacitor C.sub.2. In accordance with some embodiments, variable capacitor C.sub.2 may comprise a set of m fixed value switched capacitive elements C.sub.y. The capacitive elements C.sub.y may be connected in parallel with each other. In other words, each capacitive element C.sub.y may have a connection between resistor R.sub.2 and a ground potential connection via a corresponding switch M.sub.0-M.sub.m-1. It will be appreciated that in other embodiments, the capacitive elements C.sub.y may be connected in connection topologies other than in parallel.

[0053] The capacitive elements C.sub.y may be realized using any semiconductor technology suitable for a given application of the oscillator circuit 102. Merely to illustrate this point, in various embodiments, capacitive elements C.sub.y may be PN junction capacitors, MOSFET gate capacitors, metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and so on. The capacitive elements C.sub.y may be based on the same semiconductor technology, or they may be based on different technologies. In some embodiments, each of the capacitive elements C.sub.y may have the same capacitance. In other embodiments, the capacitive elements C.sub.y may different capacitances.

[0054] The capacitive elements C.sub.y may be selectively switched to ground potential via a set of corresponding switches M.sub.0-M.sub.m-1. The switches M.sub.0-M.sub.m-1 may be any suitable switching device. In some embodiments, for example, the switches M.sub.0-M.sub.m-1 may be semiconductor switches such as PNP transistors shown in FIG. 3A, for example. In some embodiments, all the switches M.sub.0-M.sub.m-1 may be based on the same technology, or may they may be based on different technologies. Each of the m signal lines that comprise the selector input 312 may be connected to a respective one of the switches M.sub.0-M.sub.m-1. The input to selector input 312 may be generated by digital logic or other suitable circuitry associated with the oscillator circuit 102 or with electronic circuit 10 (FIG. 1A).

[0055] In accordance with the present disclosure, the nodes of capacitive elements C.sub.y in FIG. 3A are not floating. Rather, the nodes of capacitive elements C.sub.y may be electrically connected to ground potential. One of skill in the art will appreciate that in other embodiments, the capacitive elements C.sub.y may be electrically connected to a DC voltage; (e.g., supply V.sub.DD). More generally, the capacitive elements C.sub.y may be electrically connected to any suitable low impedance node.

[0056] In operation, any one or more of the m signal lines in the selector input 312 may be asserted to turn ON their corresponding switches M.sub.0-M.sub.m-1. A switch (e.g., M.sub.0) that is in the ON state connects its corresponding capacitive element (switched on) to the RC network 304, and conversely a switch that is in the OFF state disconnects its corresponding capacitive element (switched off) from the RC network 304. If the capacitive elements C.sub.y are connected in parallel, as shown in FIG. 3A for example, the capacitance of variable capacitor C.sub.2 may be computed as the sum of the switched-on capacitive elements. Thus, the delay .sub.3 of the additional delay stage 326 may be set depending on which capacitive elements C.sub.y are switched on or switched off in the RC network 304.

[0057] In some embodiments, resistor R.sub.2 may be a fixed value element such as shown in FIG. 3A. In other embodiments (not shown), resistor R.sub.2 may be a variable resistor and capacitor C.sub.2 may be a fixed value element. In still other embodiments (not shown), resistor R.sub.2 may be a variable resistor and capacitor C.sub.2 may be a variable capacitor.

[0058] In some embodiments, the selector inputs 112, 312 of respective delay stages 126, 326 may receive the same selection input; e.g., the same n-bit code may be provided to each selector input 112, 312. In other embodiments, each selector input 112, 312 may receive different selection inputs.

[0059] The frequency of oscillation in oscillator circuit 102 may be controlled according to the delays .sub.1, .sub.2, and .sub.3. As explained above, the delay .sub.1 in delay stage 128 may be fixed for resistor R and capacitor C. The delay .sub.2 of the delay stage 126 may be set by asserting appropriate bit lines that comprise selector input 112 for the delay stage 126. Likewise, the delay .sub.3 in delay stage 326 may be set by asserting appropriate bit lines that comprise selector signal 312. Accordingly, the frequency of the clock signal 132 may be selected as a function of the variable delays .sub.2 and .sub.3.

[0060] In some embodiments in accordance with the present disclosure, the first delay section 104 may comprise several additional delay stages connected in series. FIG. 4A, for example, is a schematic representation of an oscillator circuit 102a in accordance with some embodiments of the present disclosure. The first delay section 104 may comprise delay stage 126 and two additional delay stages 426a, 426b. Inverters 422a, 422b may be provided to couple the signal between delay stages. For example, inverter 422a may couple the signal between delay stage 126 and delay stage 422a, and likewise inverter 422b may couple the signal between delay stage 422a and delay stage 422b. Note that inverters 422a, 422b, 122 that comprise the first delay section 104 provide a net negative gain.

[0061] FIG. 4B is a schematic representation of an oscillator circuit 102b comprising a first delay section 102 that has three additional delay stages 426a, 426b, 426c and inverters 422a, 422b, 422c, 422d. The inverters 422a-422c couple the signal among delay stages 126 and 426-426c. It can be seen that the inverter 424 provides the first delay section 104 with a net negative gain.

Technical Effect and Advantages

[0062] A conventional RC oscillator design, such as shown in FIG. 5, has many desirable properties. Such designs are generally insensitive to variations in supply voltage. The design is relatively simple, having few components. As a results these RC oscillators can achieve low noise performance. Some designs, for example, may achieve noise levels only 3 dB above the theoretical low limit. Because of their relatively simple designs, RC oscillators have smaller footprints on the IC chip.

[0063] The present disclosure provides an oscillator circuit having the capability of a programmable frequency to further improve the utility of RC oscillators. As shown in FIG. 5, for example, a basic RC oscillator design comprises two inverters (e.g., inversion stages 122, 124) and an RC network comprising a resistor R and a capacitor C. The RC network provides a delay that sets an operating frequency of the RC oscillator. Accordingly, varying the elements values of either R or C can serve to provide programmability in the operating frequency of the RC oscillator.

[0064] However, the method of making R or C may not be practical. Programmable resistors can be difficult to provide. High programmability requires the ability to modify the total R in small increments. This necessitates a large network of resistors and a large number of switches that have low ON resistance. Furthermore, the voltage across a switch can vary over the oscillation cycle thereby complicating the switch design. Using switched resistors to build a variable resistor may not practical.

[0065] Programmable capacitors can be difficult, since the capacitor C is a floating capacitor because of the behavior at node V.sub.X. As explained above, the node V.sub.X is a floating node because the voltage at node V.sub.X may swing above and below the supply voltage in one half of a cycle of the output and above and below ground potential in the other half of the cycle. Programmable capacitors typically comprise a bank of switched capacitor elements. When the source (or drain) of a switch is connected at the node V.sub.X, the state of the switch can become forward biased during portions of the cycle and conduct when it is supposed to be in an OFF (non-conducting) state. The presence of the floating node V.sub.X presents a challenge in using a variable capacitor at this location to provide a variable delay RC network and hence a variable frequency oscillator circuit. Thus, replacing C with a bank of switched capacitors to build a variable capacitor may not be easily accomplished.

[0066] Oscillator circuits in accordance with the present disclosure can overcome this challenge. As shown in FIG. 1B, a delay stage 126 can be provided separately from the RC network 128. The delay stage 126 may be grounded so that operation of the delay stage 126 is significantly less affected by voltage swings in the circuit.

[0067] The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.