SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a first thermal oxide film serving as a gate oxide film of a MOS transistor on a surface of a silicon substrate having a light receiving element forming region and a MOS transistor forming region; forming a polysilicon film on the first thermal oxide film; patterning the polysilicon film, to thereby form a gate electrode of the MOS transistor in the MOS transistor forming region; removing the first thermal oxide film other than the first thermal oxide film under the gate electrode; forming a second thermal oxide film on the surface of the silicon substrate; and performing ion implantation of an impurity on the light receiving element forming region through the second thermal oxide film, to thereby form an impurity region.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the second thermal oxide film is formed on an upper surface and a side surface of the gate electrode.

3. A method of manufacturing a semiconductor device according to claim 1, wherein the impurity is also implanted into the MOS transistor forming region through the ion implantation, to thereby form an LDD region of the MOS transistor.

4. A method of manufacturing a semiconductor device according to claim 1, further comprising: forming an insulating film on the second thermal oxide film; and performing anisotropic etching in a state in which a mask layer is formed on the second thermal oxide film in the light receiving element forming region, such that a side wall comprising the insulating film is formed on a side surface of the gate electrode of the MOS transistor and the insulating film remains in the light receiving element forming region.

5. A method of manufacturing a semiconductor device according to claim 1, further comprising: forming a first insulating film on the second thermal oxide film; forming a second insulating film on the first insulating film; and performing anisotropic etching by using the first insulating film as an etching stopper, to thereby form a side wall comprising the second insulating film on a side surface of the gate electrode of the MOS transistor.

6. A method of manufacturing a semiconductor device according to claim 1; wherein an impurity concentration of the impurity region at an outermost surface of the silicon substrate is 10.sup.19 cm.sup.3 or more, and wherein a depth from the surface of the silicon substrate to a point at which the impurity concentration in the impurity region becomes 10.sup.17 cm.sup.3 or less is 100 nm or less.

7. A method of manufacturing a semiconductor device according to claim 1, wherein the second thermal oxide film has a thickness of 30 nm or less.

8. A semiconductor device, comprising: a MOS transistor and a light receiving element formed on a silicon substrate, the MOS transistor comprising: a gate electrode; a first thermal oxide film for a gate oxide formed only under the gate electrode; a second thermal oxide film covering a side surface of the gate electrode and a side surface of the gate oxide film, and formed on a surface of the silicon substrate; a side wall formed on the second thermal oxide film, the side wall and the side surface of the gate electrode sandwiching the second thermal oxide film therebetween, and the side wall and the silicon substrate sandwiching the second thermal oxide film therebetween; and an LDD region formed on the silicon substrate, being self-alignment to the second thermal oxide film formed on the side surface of the gate electrode; the light receiving element comprising: the second thermal oxide film formed directly on the surface of the silicon substrate; an impurity region formed on the surface of the silicon substrate just under the second thermal oxide film; and an insulating film formed on the second thermal oxide film, the insulating film being a same film as that forms the side wall.

9. A semiconductor device according to claim 8; wherein an impurity concentration of the impurity region at an outermost surface of the silicon substrate is 210.sup.19 cm.sup.3 or more; and wherein a depth from the surface of the silicon substrate to a point at which the impurity concentration in the impurity region becomes 10.sup.17 cm.sup.3 or less is 100 nm or less.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIGS. 1A to 15 are cross-sectional views for illustrating a method of manufacturing a semiconductor device of a first embodiment of the present invention in the order of steps.

[0023] FIGS. 2A to 2D are cross-sectional views for illustrating the method of manufacturing a semiconductor device of the first embodiment of the present invention in the order of steps.

[0024] FIGS. 3A and 3B are cross-sectional views for illustrating a method of manufacturing a semiconductor device of a second embodiment of the present invention in the order of steps.

[0025] FIGS. 4A to 4D are cross-sectional views for illustrating a method of manufacturing a semiconductor device of a third embodiment of the present invention in the order of steps.

[0026] FIG. 5 is a graph for showing a concentration profile of boron after BF.sub.2 injection through a thermal oxide film having a thickness of 10 nm.

[0027] FIG. 6 is a graph for showing a concentration profile of boron after BF.sub.2 injection through a thermal oxide film having a thickness of 30 nm.

[0028] FIG. 7 is a graph for showing wavelength dependence to a light penetration depth of the incident light to silicon.

[0029] FIGS. 8A to 8D are cross-sectional views for illustrating a related-art method of manufacturing a semiconductor device in the order of steps.

[0030] FIGS. 9A to 9D are cross-sectional views for illustrating the related-art method of manufacturing a semiconductor device in the order of steps.

DESCRIPTION OF THE EMBODIMENTS

First Embodiment

[0031] FIGS. 1A to 1E and FIGS. 2A to 2D are cross-sectional views for illustrating a method of manufacturing a semiconductor device of a first embodiment of the present invention in the order of steps.

[0032] In FIGS. 1A to 1E and FIGS. 2A to 2D, PD represents a light receiving element forming region in which a light receiving element is formed, and TR represents a MOS transistor forming region in which a PMOS transistor is formed.

[0033] First, as illustrated in FIG. 1A, an N-well regions 2 and an element isolation region 3 are formed on a surface of a p-type silicon substrate 1, and then ion implantation for adjusting a threshold voltage of a transistor is performed as necessary.

[0034] Then, the entire surface of the silicon substrate 1 is thermally oxidized, to thereby form a gate oxide film (also referred to as first thermal oxide film) 4. The gate oxide film 4 has a thickness of 10 nm, for example.

[0035] Next, a polysilicon film 5, which is a material of a gate electrode 6, is deposited (FIG. 1B). The polysilicon film 5 is patterned through etching such that the gate electrode 6 is formed. In order to remove foreign matters remaining after the etching, a wet process is performed such that the gate oxide film 4 other than that under the gate electrode 6 is removed (FIG. 10).

[0036] Then, the entire surface is thermally oxidized, to thereby form a thermal oxide film (also referred to as second thermal oxide film) 7 on a surface of the silicon substrate 1, and on side surfaces and an upper surface of the gate electrode 6 (FIG. 1D). The thickness of the thermal oxide film 7 is 10 nm in the light receiving element forming region PD, for example. To thermally oxidize the side surfaces of the gate electrode 6 in this step has a role of removal of etching damage when the gate electrode 6 is patterned, and prevention of ion penetration through the gate electrode 6 when ion implantation for forming source/drain regions is performed in a later step.

[0037] Next, ion implantation of a p-type impurity is performed on the N-well region 2 in the light receiving element forming region PD through the thermal oxide film 7, to thereby form a p-type impurity region 8 (FIG. 1E). Implantation conditions of the ion implantation are BF.sub.2, 10 keV, and 5.010.sup.13 cm.sup.2, for example. As a result, a shallow pn junction is formed. The thermal oxide film 7 is not the gate oxide film (first thermal oxide film) 4 but a thermal oxide film newly formed after removing the gate oxide film 4, and hence is not damaged through etching or the like. Further, the ion implantation may be performed while other insulating films are not formed on the thermal oxide film 7.

[0038] As a result, a dose amount of the ion implantation may be kept low as described above, and there may be formed the light receiving element, which has high reliability and has the shallow junction in which the impurity concentration of the outermost surface of the silicon substrate in the impurity region is 10.sup.19 cm.sup.3 or more, and a depth from the surface of the silicon substrate at which the impurity concentration in the impurity region becomes 10.sup.17 cm.sup.3 or less is 100 nm or less.

[0039] Subsequently, the p-type impurity ion implantation is performed on the MOS transistor forming region TR in which the gate electrode 6 and the second thermal oxide film 7 formed on the side surfaces of the gate electrode are used as a mask, to thereby form lightly doped drain (LDD) regions 9 in a self-alignment manner (FIG. 2A).

[0040] Next, an insulating film 10 is deposited on the entire surface (FIG. 2B). The insulating film 10 has a thickness of 300 nm, for example. Subsequently, the light receiving element forming region PD is covered with a mask layer R formed of a resist, and then anisotropic etching is performed in the light receiving element forming region PD in that state, to thereby form side walls 11 on the side surfaces of the gate electrode 6 (FIG. 2C). Surfaces of the LDD regions 9 in the MOS transistor forming region TR are removed until the thermal oxide film 7 is removed. However, the light receiving element forming region PD is covered with the mask layer R, and hence the insulating film 10 remains in the light receiving element forming region PD. Thus, the thermal oxide film 7 that is in direct contact with the surface of the silicon substrate 1 is less likely to be damaged through etching.

[0041] Then, as illustrated in FIG. 2D, the p-type impurity ion implantation is performed on the MOS transistor forming region TR, to thereby form the source/drain regions 12. Then, a high-temperature short-time activation annealing is performed at 950 C. for 1 second, for example, such that the shallow junction in the light receiving element forming region PD remains intact.

[0042] A concentration profile of boron in the light receiving element forming region PD that is formed as above is shown in FIG. 5. As described above, the thickness of the thermal oxide film 7 in the light receiving element forming region PD is 10 nm, and the ion implantation conditions are BF.sub.2, 10 keV, and 5.010.sup.13 cm.sup.2.

[0043] As shown in FIG. 5, a boron concentration of the outermost silicon surface is 210.sup.19 cm.sup.3, and a depth from the silicon surface at which the boron concentration becomes 10.sup.17 cm.sup.3 or less is 55 nm. Hence, an impurity profile needed in order to detect an ultraviolet light with high sensitivity may be achieved.

[0044] As described above, according to this embodiment, since the dose amount of the ion implantation for forming the impurity region 8 is in the 10.sup.13 cm.sup.2 range, the light receiving element, which has the impurity profile as shown in FIG. 5 and has high reliability, may be formed together with the MOS transistor through a manufacturing method that matches with the manufacturing steps of the MOS transistor, without the failures in the manufacturing that occur in the related-art manufacturing method.

Second Embodiment

[0045] FIGS. 3A and 3B are cross-sectional views for illustrating a manufacturing method of a second embodiment of the present invention in the order of steps. In FIG. 3A, the same step as that of FIG. 1D is illustrated. Steps up to this step are the same as those in the first embodiment, and the descriptions thereof are thus omitted. However, in this embodiment, the thickness of the thermal oxide film 7 is set to be 30 nm, which is thicker than that of the first embodiment.

[0046] In this state, as illustrated in FIG. 3B, ion implantation for forming a shallow junction is performed on the light receiving element forming region PD. The ion implantation conditions are BF.sub.2, 15 keV, and 5.310.sup.14 cm.sup.2, for example. This ion implantation is also performed on the MOS transistor forming region TR, to thereby form the LDD regions 9.

[0047] After the step of FIG. 3B, the PMOS transistor and the light receiving element may be formed on the same silicon surface by following the same steps as illustrated in FIG. 2B and in the subsequent drawings.

[0048] Through use of the method of this embodiment, since the formation of the impurity region 8 in the light receiving element forming region PD, that is, the ion implantation for forming the shallow junction also serves as the ion implantation for forming the LDD regions 9 of the MOS transistor, the number of steps may be reduced as compared to the first embodiment.

[0049] A concentration profile of boron in the light receiving element forming region PD of this embodiment is shown in FIG. 6. As described above, the thickness of the thermal oxide film 7 in the light receiving element forming region PD is 30 nm, and the ion implantation conditions are BF.sub.2, 15 keV, and 5.010.sup.14 cm.sup.2.

[0050] As shown in FIG. 6, a boron concentration of the outermost silicon surface is 210.sup.19 cm.sup.3, and a depth from the silicon surface at which the boron concentration becomes 10.sup.17 cm.sup.3 or less is 65 nm. Hence, an impurity profile needed in order to detect an ultraviolet light with high sensitivity may be achieved.

[0051] As can be seen from FIG. 5 and FIG. 6, in a case where the ion implantation is performed through an oxide film, when the thickness of the oxide film is changed from 10 nm to 30 nm, the dose amount of implantation needs to be increased by an order of magnitude in order to set the boron concentration in the outermost silicon surface to be 10.sup.19 cm.sup.3 or more. Further, when the oxide film is formed to be thicker, implantation energy also needs to be raised, and thus it becomes difficult to form the shallow junction with high controllability. As a result, it is desired that the thickness of the oxide film be 30 nm or less.

Third Embodiment

[0052] FIGS. 4A to 4D are cross-sectional views for illustrating a manufacturing method of a third embodiment of the present invention in the order of steps. In FIG. 4A, the same step as that of FIG. 2A is illustrated. Steps up to this step are the same as those in the first embodiment, and the descriptions thereof are thus omitted.

[0053] Next, as illustrated in FIG. 4B, insulating films 10a and 10b for forming side walls are deposited. In this case, the insulating film 10a is a silicon nitride film having a thickness of 20 nm, and the insulating film 10b is a silicon dioxide film having a thickness of 280 nm. Further, the thermal oxide film 7 on the surface of the light receiving element forming region has a thickness of 30 nm or less.

[0054] Subsequently, as illustrated in FIG. 4C, side walls 11b including the insulating film (silicon dioxide film) 10b are formed on the side surfaces of the gate electrode 6 through anisotropic etching. Through use of etching conditions in which an etching rate of the oxide film is high, and an etching rate of the nitride film is low, the insulating film (silicon nitride film) 10a remains as an etching stopper. As a result, the etching damage to the thermal oxide film 7 that is in direct contact with the silicon surface in the light receiving element forming region PD may be reduced. After forming the side walls 11b, ion implantation is performed to form the source/drain regions 12 (FIG. 4D).

[0055] As described above, the MOS transistor and the light receiving element may be formed together on the same silicon substrate.

[0056] Through use of the method of this embodiment, there is no need to cover the insulating film in the light receiving element forming region PD with a resist when the side walls 11b are formed, and hence the number of steps may be reduced. In this embodiment, the nitride film 10a and the oxide film 10b have a laminated structure. However, when the nitride film is near the silicon surface, the nitride film functions as a charge trap, and may affect characteristics of the light receiving element or characteristics of the MOS transistor. In that case, a structure having three or more layers such as an oxide film/nitride film/oxide film structure may also be used.

[0057] Further, in the laminated structure formed of the nitride film and the oxide film in the light receiving element forming region PD, transmittance of a particular wavelength range of light may be selectively increased by optimally designing each film thickness. As a result, the light receiving element having a high sensitivity to a particular wavelength range may also be manufactured.

[0058] The embodiments of the present invention have been described above, but needless to say, the present invention is not limited to those embodiments, and various changes may be made thereto without departing from the gist of the present invention.

[0059] For example, in each of the embodiments described above, an example of manufacturing the PMOS transistor and the light receiving element having a p-type outermost surface in the N-well region has been described. However, it goes without saying that it is also possible to manufacture an NMOS transistor and a light receiving element having an n-type outermost surface in a P-well region. In that case, an ion species, for example, arsenic, phosphorus, or antimony, is used in the ion implantation for forming the shallow pn junction.

[0060] Further, in each of the embodiments described above, BF.sub.2 is used as the ion species in the ion implantation, but in the ion implantation, for example, boron may be used alone or a cluster ion containing boron may be used.