Method and equipment for treating a precursor of a heterojunction photovoltaic cell and associated method for producing a photovoltaic cell

Abstract

The precursor comprises at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material. The method comprises the steps of placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer, then applying a state change electrical voltage (U1) between the conducting layer and ground, the said state change electrical voltage (U1) being designed to bring the Fermi level at the interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the said amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature (T.sub.E), and finally cooling down the cell precursor (10) prior to interrupting the application of the state change electrical voltage (U1).

Claims

1. A method for processing a precursor of a heterojunction photovoltaic cell, the precursor comprising at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material, the method comprising: placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer; applying a state change electrical voltage between the conducting layer and ground, the state change electrical voltage being designed to bring the Fermi level at an interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature; cooling down the cell precursor prior to interrupting the application of the state change electrical voltage.

2. The processing method as claimed in claim 1, wherein the equilibration temperature is higher than or equal to a defect equilibration threshold temperature below which the energy provided is insufficient to allow a modification of the defect density in the amorphous semiconductor.

3. The processing method as claimed in claim 1, wherein the equilibration temperature is higher than or equal to 150 C.

4. The method as claimed in claim 1, wherein the equilibration temperature is less than or equal to a maximum temperature beyond which the amorphous semiconductor would be degraded.

5. The method as claimed in claim 1, wherein the equilibration temperature is less than or equal to 300 C.

6. The method as claimed in claim 1, wherein, during the application of the state change electrical voltage, the cell precursor is heated to the equilibration temperature for an equilibration time, the temperature and equilibration time pair being chosen as a function of a desired efficiency, and wherein, in order to determine the temperature and equilibration time pair, during a prior configuration phase, a plurality of test cell precursors, analogous to the precursor of the cell to be fabricated, is provided and, for each test precursor, the steps are implemented for placing the test precursor sandwiched between a grounded support and a plate made of insulating material coated with a conducting metal layer, for applying a state change electrical voltage between the conducting metal layer and ground, while at the same time heating the test precursor to an equilibration temperature, and for cooling down the test precursor prior to interrupting the application of the state change electrical voltage, the various test precursors being tested for various respective pairs of temperature and of equilibration time, then the efficiency of each test precursor is evaluated and the optimum pair of temperature and of equilibration time is selected corresponding to the best efficiency obtained.

7. The method as claimed in claim 1, wherein the precursor is heated to the equilibration temperature with the application of the state change electrical voltage for an equilibration time in the range between 1 and 30 minutes.

8. The processing method as claimed in claim 1, wherein the assembly comprising the cell precursor, the conducting plate and the insulating plate coated with the conducting layer is placed in a vessel under a controlled atmosphere and, in order to cool down the precursor, a cooling fluid is circulated within the vessel.

9. The processing method as claimed in claim 1, wherein the insulating plate has a thickness greater than or equal to 100 nm.

10. A method of fabrication of a heterojunction photovoltaic cell, the method comprising: providing a cell precursor comprising at least one layer of doped crystalline silicon and one layer of doped amorphous semiconductor material and implementing a processing method as claimed in claim 1, applied to the cell precursor.

11. The method of fabrication as claimed in claim 10, wherein, after cooling down the cell precursor and interruption of the state change electrical voltage, the method of fabrication comprises depositing at least one layer of electrically-conducting material and performing a metallization in order to form electrical contacts.

12. The processing method as claimed in claim 2, wherein the equilibration temperature is higher than or equal to 150 C.

13. The method as claimed in claim 2, wherein the equilibration temperature is less than or equal to a maximum temperature beyond which the amorphous semiconductor would be degraded.

14. The method as claimed in claim 3, wherein the equilibration temperature is less than or equal to a maximum temperature beyond which the amorphous semiconductor would be degraded.

15. The method as claimed in claim 2, wherein the equilibration temperature is less than or equal to 300 C.

16. The method as claimed in claim 3, wherein the equilibration temperature is less than or equal to 300 C.

17. The method as claimed in claim 4, wherein the equilibration temperature is less than or equal to 300 C.

18. The method as claimed in claim 2, wherein, during the application of the state change electrical voltage, the cell precursor is heated to the equilibration temperature for an equilibration time, the temperature and equilibration time pair being chosen as a function of a desired efficiency, and wherein, in order to determine the temperature and equilibration time pair, during a prior configuration phase, a plurality of test cell precursors, analogous to the precursor of the cell to be fabricated, is provided and, for each test precursor, the steps are implemented for placing the test precursor sandwiched between a grounded support and a plate made of insulating material coated with a conducting metal layer, for applying a state change electrical voltage between the conducting metal layer and ground, while at the same time heating the test precursor to an equilibration temperature, and for cooling down the test precursor prior to interrupting the application of the state change electrical voltage, the various test precursors being tested for various respective pairs of temperature and of equilibration time, then the efficiency of each test precursor is evaluated and the optimum pair of temperature and of equilibration time is selected corresponding to the best efficiency obtained.

19. The method as claimed in claim 3, wherein, during the application of the state change electrical voltage, the cell precursor is heated to the equilibration temperature for an equilibration time, the temperature and equilibration time pair being chosen as a function of a desired efficiency, and wherein, in order to determine the temperature and equilibration time pair, during a prior configuration phase, a plurality of test cell precursors, analogous to the precursor of the cell to be fabricated, is provided and, for each test precursor, the steps are implemented for placing the test precursor sandwiched between a grounded support and a plate made of insulating material coated with a conducting metal layer, for applying a state change electrical voltage between the conducting metal layer and ground, while at the same time heating the test precursor to an equilibration temperature, and for cooling down the test precursor prior to interrupting the application of the state change electrical voltage, the various test precursors being tested for various respective pairs of temperature and of equilibration time, then the efficiency of each test precursor is evaluated and the optimum pair of temperature and of equilibration time is selected corresponding to the best efficiency obtained.

20. A piece of equipment for processing a precursor of a heterojunction photovoltaic cell, comprising: a grounded conducting plate; a plate made of an insulating material coated with a conducting layer, the two plates being arranged to sandwich a photovoltaic cell precursor to be processed, the precursor comprising at least one layer of doped crystalline silicon and one layer of doped amorphous semiconductor material; an electrical voltage generator connected to the conducting layer; a heating device; a cooling device; a control module designed to control the operation of the electrical voltage generator, of the heating device and of the cooling device so as to apply a state change electrical voltage between the conducting layer and ground, the state change electrical voltage being designed to bring the Fermi level at an interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature, then to cool down the precursor prior to interrupting the application of the state change electrical voltage.

Description

(1) The invention will be better understood by means of the following description of one particular embodiment of the method of fabrication of a heterojunction photovoltaic cell, with reference to the appended drawings in which:

(2) FIG. 1 shows a device for processing a cell precursor for the fabrication of a photovoltaic cell according to one particular embodiment of the invention;

(3) FIG. 2 shows a schematic view of the cell in cross-section;

(4) FIG. 3 shows the time variation of the temperature of the cell precursor and the time variation of the electrical voltage applied during the processing of the cell precursor;

(5) FIG. 4 shows the variation of the defect density in amorphous silicon as a function of the position of the Fermi level within the amorphous silicon, according to the predictions of the of defect-pool model;

(6) FIG. 5 shows the variation of the open-circuit electrical voltage of a photovoltaic cell fabricated according to the method of the invention, as a function of the modified position of the Fermi level during the processing;

(7) FIG. 6 shows a flow diagram of the steps of the method.

(8) The method of the invention relates to the fabrication of a heterojunction photovoltaic cell, referenced 100. It relates more particularly to the processing a cell precursor 10 adapted to the fabrication of the cell 100, which is aimed at improving the performance characteristics of the finished cell 100. This processing is implemented during the fabrication of the cell 100.

(9) In the particular example described here, the heterojunction photovoltaic cell 100 is a cell said to be of the N type, in other words it comprises a central layer 1 of N-type doped crystalline silicon on which and under which are respectively disposed two layers 2 and 3 of an amorphous semiconductor material, for example of hydrogenated amorphous silicon. The central layer 1 is, in particular, formed starting from a substrate, in the present case a wafer, of crystalline silicon doped according to the N type. The material composing it is accordingly denoted (N) c-Si.

(10) The amorphous layers 2 and 3 could be formed of a semiconductor material other than hydrogenated amorphous silicon, notably of an amorphous semiconductor alloy formed from silicon and from an element such as germanium, carbon, oxygen, etc.

(11) At least one of the two layers of amorphous silicon 2, 3 is doped with a doping of the P or N type. In the particular exemplary embodiment described here, the top (or front) layer 2 is doped with a doping of the P type and the bottom (or back) layer 3 is doped with a doping of the N type. The materials composing the top layer 2 and the bottom layer 3 are denoted (P)a-Si:H and (N)a-Si:H, respectively.

(12) Any other combination of stacking of layers of the P and/or N type may be envisioned within the scope of the invention. The bottom, or back, layer 3 could also be formed of an intrinsic semiconductor material. In any case, the cell comprises at least one layer of doped crystalline silicon (of the P or N type) carrying a layer of amorphous semiconductor, an interface INT being disposed at the separation between doped crystalline silicon and amorphous semiconductor.

(13) By definition, an intrinsic semiconductor material is an undoped semiconductor material, whose electrical behavior only depends on its structure, and not on the addition of impurities as in the case of a doping. In an intrinsic semiconductor material, the charge carriers are only created by crystalline defects or by thermal excitation. Furthermore, the Fermi level is close to the middle of the band gap (more particularly, slightly higher than the middle of the gap).

(14) The photovoltaic cell 100 here also comprises an intermediate layer 4 of intrinsic semiconductor material, in the present case hydrogenated amorphous silicon denoted (i)a-Si:H, disposed between the central layer 1 and the top layer 2. This layer of intrinsic amorphous silicon is deposited directly on the central layer 1, in order to reduce the number of defects at the interface INT between amorphous silicon and crystalline silicon.

(15) It could also be envisioned to deposit an intermediate layer of intrinsic amorphous semiconductor material under the central layer 1, between the latter and the bottom layer 3 of amorphous semiconductor material.

(16) The intermediate layer or layers could be micro-doped, instead of being intrinsic.

(17) The term interface INT is understood here to denote a region situated at the separation between crystalline silicon and amorphous silicon which contains the first nanometer or nanometers of amorphous silicon, typically the first 2 or 3 nanometers, adjoining the crystalline silicon.

(18) After having been deposited on the central layer 1, the layer of intrinsic amorphous silicon 4 is initially of good quality: its Fermi level is close to the middle of the band gap of the intrinsic amorphous silicon and, consequently, its defect density is minimized according to the predictions of the of defect-pool model. For more detailed information on the defect-pool model, the reader is invited to refer for example to the document Defect-pool model and the hydrogen density of states in hydrogenated amorphous silicon, M. J. Powell and S. C. Deane, Phys. Rev. B, 53:10121-32, 1996. The purpose of the intrinsic layer 4, which is deposited on the crystalline silicon, is to reduce the defects at the interface INT and hence to improve the efficiency of the cell 100.

(19) However, when the layer 2 of P-doped amorphous silicon is deposited on top of the layer 4 of intrinsic amorphous silicon, this P-doped layer forces the Fermi level of the intrinsic layer 4, and as a consequence of the interface INT, to come closer to the valence band, as if the intrinsic layer 4 were P-doped. This results in a modification of the Fermi level in the interface INT which comes closer to the valence level. However, as the deposition of the P-doped layer is carried out at a temperature close to or higher than a threshold temperature for equilibration of the defects, the defect density in the intrinsic layer 4, including in the interface INT, varies, and more particularly increases, until it reaches an equilibrium defect density which depends on the modified Fermi level.

(20) Each layer of amorphous silicon 2 (respectively 3) is coated with a top, or front, layer 5 (respectively bottom, or back, layer 6) of a transparent conductive material, for example a transparent electrically-conducting oxide, or TCO (for Transparent Conductive Oxide).

(21) The thicknesses of the layers may be as follows: central layer 1 in the range between 50 and 200 m, layers 2 (doped amorphous silicon), 3 (doped amorphous silicon) and 4 (intrinsic silicon) each in the range between 1 and 40 nm, layers 5 and 6 (conductive material) each in the range between 50 and 300 nm.

(22) Lastly, top (or front) electrical contacts 7A, 7B are disposed on the free face of the top layer 5 of TCO, referred to as front face of the cell 100, and bottom (or back) electrical contacts 8A, 8B are disposed on the free face of the bottom layer 6 of TCO, referred to as back face of the cell 100.

(23) It should be noted that, on the back face, the layer 6 is not necessarily transparent. For a cell of the bifacial type, the layer 6 has the same function as on the front face and is, in this case, transparent. For a cell of the mono-facial type, having a full-sheet metallization, the layer 6 provides a better contact on the amorphous silicon and does not need to be transparent. These layers 5 and 6 provide the lateral transport of the charges toward the electrical contacts or metallizations, front and back.

(24) The invention allows the defect density to be reduced in the interface INT between crystalline silicon and amorphous silicon in the cell 100 by a thermal processing of this interface INT under an applied electrical voltage. This processing is applied during the fabrication of the cell 100.

(25) The method of fabrication of the cell 100, according to one particular embodiment of the invention, will now be described with reference notably to FIG. 6. For the sake of concision, only the steps relating to the invention will be detailed in the description that follows.

(26) During an initial step E0, a cell precursor 10 is provided here comprising the stacking of the central layer 1 of crystalline silicon of the N type, of the layer of intrinsic amorphous silicon 4 and of the top layer 2 of amorphous silicon of the P type. The cell precursor 10 is formed in a known manner starting from a wafer of crystalline silicon of the N type on which the layer of intrinsic amorphous silicon 4 and the top layer 2 of amorphous silicon of the P type are successively deposited.

(27) During a second step E1, the cell precursor 10 is sandwiched, in other words interposed, between a grounded conducting carrier plate 11 and a plate 12 made of insulating material coated with a conducting layer 13, as shown in FIG. 1. For example, the plate 12 is made of mica and the conducting layer 13 is of a metal or metal alloy. The carrier plate 11 here is a heating plate, incorporating a resistive heating element 110 connected to a current generator 15. The heating carrier plate 11 is designed to heat up the cell precursor 10.

(28) The assembly comprising the conducting layer 13, the insulator 12 and the cell precursor 10 forms a structure 14 of the MIS (for Metal-Insulator-Semiconductor) type, in which the cell precursor 10 plays the role of the semiconductor of the MIS structure. This structure 14 is disposed on the carrier 11 which is connected to a reference potential, in the present case to ground M.

(29) The conducting layer 13 is connected to an electrical voltage generator 16, by means of electrical contacts, not shown. The generator 16 is designed to apply a state change electrical voltage U1 between the conducting layer 13 and ground M (or the reference potential to which the carrier plate 11 is connected).

(30) The MIS structure and the carrier plate 11 are placed in a vessel 17 under a controlled atmosphere, in which dihydrogen and/or dinitrogen circulates. It could also be envisioned to evacuate the vessel.

(31) As a variant, the MIS structure 14 and the carrier plate 11 could be placed in an oven designed to heat the cell precursor 10. In this case, the carrier plate 11 would not be heated but would nevertheless be connected to ground M.

(32) After formation of the MIS structure, during a step E2, the cell precursor 10 is heated by means of the heating plate 11 whose resistive element is supplied with current by the generator 15. In FIG. 3, the time variation of the temperature T of the precursor 10 is shown by dashed lines. Initially, the temperature T of the precursor 10 is equal to ambient temperature T.sub.A. The heater raises the temperature T of the precursor 10 from ambient temperature T.sub.A to an equilibration temperature T.sub.E. The time of start of heating is denoted t.sub.0 and t.sub.1 the time at which the precursor 10 reaches the temperature T.sub.E.

(33) During a step E3, the heating continues in such a manner as to maintain the temperature T of the cell precursor 10 at the equilibration temperature T.sub.E, until a time t.sub.2. A temperature probe (not shown) connected to the metal carrier 11 allows the temperature T to be monitored and controls the operation of the current generator 15 supplying the resistive element 110 of the heating plate 11.

(34) The equilibration temperature T.sub.E must be higher than an equilibration threshold temperature T.sub.TSH. The equilibration threshold temperature is understood to denote a minimum temperature starting from which the defects initially present in the amorphous silicon forming the layer 4 reach equilibrium, the energy provided by the heating being sufficient to cause chemical reactions, such as notably described in the document Defect-pool model and the hydrogen density of states in hydrogenated amorphous silicon, M. J. Powell and S. C. Deane, Phys. Rev. B, 53:10121-32, 1996, which have the effect of reducing the defect density in the amorphous silicon. The equilibration temperature T.sub.E must also be less than a maximum temperature T.sub.max beyond which the heating would degrade the structure of the amorphous silicon and the interface INT, notably by crystallization and/or by effusion of hydrogen. The equilibration temperature T.sub.E can be in the range between 150 C. and 300 C.

(35) U denotes the electrical voltage across the terminals of the MIS structure 14, in other words between the conducting metal layer 13 and ground M. Initially, at time t.sub.0, the electrical voltage U is zero (U=0), as shown in FIG. 3. During a step E4, starting from time t.sub.1, or shortly after this time t.sub.1, the voltage generator 16 applies an electrical voltage U equal to a state change electrical voltage, denoted U1. This results in a non-zero electrical voltage across the terminals of the cell precursor 10 (in other words between the free top face of the layer 2 of amorphous silicon and the free bottom face of the layer 1 of crystalline silicon). Applying a voltage to the MIS structure 14 and, as a consequence, to the precursor 10, is carried out without causing current to flow by virtue of the insulator 12 which prevents it from flowing. The thickness of the insulator 12 must be greater than about 100 nm in order to avoid any leakage current.

(36) The value U1 of the state change electrical voltage applied to the terminals of the cell precursor 10 is designed to modify the position of the Fermi level in the interface INT of the cell precursor 10 and to bring it closer to the middle of the band gap of the amorphous silicon. The band gap denotes, in a known manner, the gap between the valence band and the conduction band of the semiconductor material, in the present case the hydrogenated amorphous silicon forming the intermediate layer 4. The state change electrical voltage U1 that should be applied in order shift the Fermi level up to the middle of the band gap or to a position close to the latter, also depends on the thickness of the insulator 12. The thicker the insulator 12 (the thickness of the insulator notably allowing a good mechanical strength of the layer 12 to be ensured), the higher must be the state change electrical voltage U1. Depending on the thickness of the insulator 12, the state change electrical voltage U1 can thus be in the range between a few tens of Volts and several thousand Volts. In order to determine the electrical voltage U1 to be applied, a value of electrical voltage U1 may be chosen such that the product C*U1, where C represents the electrical capacitance of the insulator of the MIS structure, is higher than 10.sup.12 charges per cm.sup.2. This value of 10.sup.12 charges per cm.sup.2 indeed corresponds to around the fixed quantity of charges present in the layer 2 of doped hydrogenated amorphous silicon. However, it is this value of quantity of charges that must be made to vary in order to change the position of the Fermi level in the layer

(37) The phrase close to the middle of the gap is understood here to mean that the shifted position of the Fermi level, resulting from the application of the state change electrical voltage U1, denoted E.sub.F and expressed in eV, is such that:

(38) $\frac{\left(E_c-E_v\right)}{2}-0.2E_F-E_v\frac{\left(E_c-E_v\right)}{2}+0.2$

(39) where E.sub.c and E.sub.v respectively denote the energy state of the lower limit of the conduction band, expressed in eV, and the energy state of the upper limit of the valence band, expressed in eV, in the hydrogenated amorphous silicon forming the layer 4; (E.sub.cE.sub.v) corresponds to the height of the band gap between the valence band and the conduction band; E.sub.FE.sub.v denotes the energy state, expressed in eV, of the Fermi level with respect to the valence band, corresponding to the position relative of the Fermi level with respect to the valence band (more particularly with respect to the upper limit of the valence band).

(40) In other words, the Fermi level shifted by application of the state change electrical voltage U1 is in the range between the middle of the band gap decreased by 0.2 eV and the middle of the band gap increased by 0.2 eV.

(41) In the particular exemplary embodiment described here, the band gap is 1.8 eV. The Fermi level shifted by application of the state change electrical voltage U1 is therefore in the range between 0.7 eV and 1.1 eV.

(42) The sign of the state change electrical voltage U1 to be applied depends on the relative dopings of the layer 1 of crystalline silicon and of the layer of amorphous silicon 2. It must be adapted in order to bring the Fermi level closer to the middle of the band gap at the interface INT. For example, in the case of a layer 1 of crystalline silicon of the N type and of a layer 2 of hydrogenated amorphous silicon of the P type, the positive pole must be applied on the side of the layer 2. In other words, the state change electrical voltage (with respect to ground) applied by the generator 16 to the conducting plate 13 is positive.

(43) The state change electrical voltage U1 is applied to the terminals of the precursor 10 (in other words between the conducting layer 13 and ground M), while at the same time heating and maintaining the cell precursor 10 at the temperature T.sub.E of equilibration of the defects, between time t.sub.1 (or shortly after this time t.sub.1) and time t.sub.2. is used, with =t.sub.2t.sub.1, to denote the equilibration time of the defects, corresponding to the time during which the precursor 10 is subjected both to the application of the state change electrical voltage U1 and to the heating to the temperature T.sub.E. This duration can be in the range between 1 minute and 30 minutes, depending on the kinetics of equilibration of the defects.

(44) During the period for equilibration of the defects of duration (in other words between the times t.sub.1 and t.sub.2), under the effect of the state change electrical voltage U1, the shifted Fermi level of the interface INT is close to the middle of the band gap of the amorphous silicon forming the interface INT. The Fermi level then has the same position as in intrinsic amorphous silicon. By virtue of the energy provided by the heating to the equilibration temperature T.sub.E, the defect density within the interface INT reaches equilibrium as a function of the shifted Fermi level (in other words close to the middle of the gap). Since the shifted Fermi level corresponds to the Fermi level of intrinsic amorphous silicon, the density d of defects in the interface INT decreases toward an equilibrium defect density d.sub.E corresponding to the defect density in the intrinsic amorphous silicon. As previously explained, the equilibration of the defects takes place by chemical reactions such as described in the document Defect-pool model and the hydrogen density of states in hydrogenated amorphous silicon, M. J. Powell and S. C. Deane, Phys. Rev. B, 53:10121-32, 1996. Thus, the application of the state change electrical voltage U1 to the terminals of the precursor 10 allows a virtual transformation, in terms of energy state, of the interface INT into an intrinsic semiconductor.

(45) FIG. 4 shows the variation of the maximum density of defects in the amorphous silicon forming the layer 4 containing the interface INT (expressed in cm.sup.3.Math.eV.sup.1) as a function of the relative position of the Fermi level with respect to the valence band, in other words (E.sub.FE.sub.v), expressed in eV, according to the predictions of the defect-pool model. The curve in FIG. 4 shows that the defect density is a minimum when the Fermi level is positioned at 0.9 eV above the valence band, i.e. in the middle of the band gap whose height is 1.8V.

(46) After the period for equilibration of the defects of duration , the method continues with a step E5 for cooling down the cell precursor 10. This step E5 begins at time t.sub.2 and ends at time t.sub.3 when the precursor 10 has returned to ambient temperature T.sub.A. The duration of the cooling (in other words the duration (t.sub.3t.sub.2)) may be of any given length. Preferably, it can be carried out rapidly, for example in less than 1 minute, by causing a cooling fluid, for example nitrogen N.sub.2 at low temperature, to circulate within the vessel 17.

(47) After cooling of the precursor 10, at time t.sub.3 (or potentially at a later moment in time), the application of the state change electrical voltage U is interrupted, the electrical voltage across the terminals of the precursor 10 thus being reset to zero, during a step E6.

(48) It should be noted that the cell precursor 10 should be cooled down prior to interrupting the state change electrical voltage U1, in order not to cause an a posteriori increase of the defect density. It could however be envisaged to interrupt the application of the state change electrical voltage before the temperature of the precursor 10 reaches the ambient temperature, as long as the temperature of the precursor 10 is lower than the equilibration threshold temperature T.sub.TSH.

(49) In order for the defect density in the interface INT to reach or to become close to the equilibrium density during the period of heating to temperature T.sub.E under an applied electrical voltage U1, referred to as equilibration period, an equilibration temperature and equilibration time pair (T.sub.E,) should be chosen that defines a sufficient thermal budget to be provided to the cell precursor 10 and that allows a desired efficiency for the finished cell 100 to be obtained. In order to determine the temperature and equilibration time pair (T.sub.E,), during a prior configuration phase, a plurality of test cell precursors is provided, analogous to the cell precursor 10. For each test precursor, the processing steps previously described E0 to E6 are implemented. The various test precursors are subjected to processing for various respective pairs of equilibration temperature and time (T.sub.Ei,.sub.i). During a later evaluation step, the efficiency of each test precursor is evaluated, for example by measuring, in a known manner, the lifetime of the minority carriers in the test cell precursor. Finally, the optimum pair of equilibration temperature T.sub.E and of equilibration time is selected corresponding to the best efficiency. As a variant, the efficiency of finished cells could be tested, carried out using the processed test precursors.

(50) FIG. 5 shows the variation of the open circuit electrical voltage V.sub.OC, expressed in mV, of the finished cell 100 as a function of the position of the Fermi level relative to the valence band in the interface INT of the precursor 10 during the equilibration period (while heating to T.sub.E under an applied electrical voltage U1). The highest values of V.sub.OC are obtained for Fermi levels close to the middle of the band gap (the gap being 1.8 eV) during the heating under an applied electrical voltage.

(51) It should be highlighted that it is thanks to the absence of current through the cell precursor 10 that, by application of the state change electrical voltage, it is possible to shift the Fermi level up to the desired position close to the middle of the gap.

(52) After resetting the electrical voltage U across the terminals of the precursor 10 to zero, the method continues with a plurality of known steps for finishing the cell using the precursor 10. These steps comprise: a step E7 for deposition of the back layer 3 of doped amorphous silicon; a step E8 for deposition of the layers 5 and 6 of TCO; a metallization step E9 for forming the contacts 7A, 7B, 8A and 8B.

(53) After the step E9, the finished photovoltaic cell is obtained 100.

(54) The finishing steps E7 to E9 may be carried out after the processing steps E0 to E6 en passant (in other words without interrupting the fabrication process) or after interruption of the fabrication process. In the second case, the steps E0 to E6, on the one hand, and the steps E7 to E9, on the other, could be implemented respectively by two different actors in the fabrication sequence for the cell 100.

(55) In the preceding description, the cell precursor 10 comprises a stacking of layers comprising a layer of doped crystalline silicon, an intermediate layer of intrinsic hydrogenated amorphous silicon and a top layer of doped hydrogenated amorphous silicon. This stack may be formed on the front face and/or on the back face of the cell 100. In one variant, the intermediate layer of amorphous silicon could be micro-doped. In another variant, the top layer of doped hydrogenated amorphous silicon is deposited directly onto the crystalline silicon, with no intrinsic or microdoped intermediate layer.

(56) In order to also process the interface, denoted INT, between crystalline silicon and amorphous silicon at the separation between the central layer 1 and the bottom layer of amorphous silicon 3, steps analogous to the processing steps E1 to E6 could be carried out, by heating under an applied electrical voltage, with a cell precursor composed of the stack of layers comprising the central layer 1, the intermediate layer 4, the top layer 2 and the bottom layer 3. In this case, the processing of the interface INT and that of the interface INT would be carried out one after the other. Where appropriate, the processing of these two interfaces INT and INT, by heating under an applied electrical voltage, could be carried out simultaneously if the respective dopings of the layers 1, 2 and 3 allow it.

(57) An intermediate layer of intrinsic amorphous silicon could be interposed between the central layer 1 and the bottom layer of doped amorphous silicon.

(58) The invention also relates to a piece of processing equipment, designed to be used during the fabrication of a heterojunction photovoltaic cell, comprising: the grounded conducting plate 11; the plate made of insulating material 12 coated with the conducting layer 13, the two plates 12, 13 being arranged to sandwich a photovoltaic cell precursor to be processed, for example the precursor 10; the electrical voltage generator 16 connected to the conducting layer 13; a heating device, for example the resistive element 110 powered by the current generator 15, integrated into the plate 11; a cooling device, for example the vessel 17 and means for making a cooling fluid circulate within this the vessel 17; a control module (not shown) designed to control the operation of the electrical voltage generator, of the heating device and of the cooling device in such a manner as to apply a state change electrical voltage U1 between the conducting metal layer 13 and ground, the electrical voltage U1 being designed to bring the Fermi level at the interface INT between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the amorphous semiconductor material of the precursor, while at the same time heating the precursor to a defect equilibration temperature, then to cool down the precursor prior to interrupting the application of the said state change electrical voltage.