Method of manufacturing a transistor with oxidized cap layer

Abstract

A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a channel layer on or above a substrate, wherein a two dimensional electron gas channel exists in the channel layer; forming a spacer layer on the channel layer, wherein the spacer layer is in contact with the channel layer; forming a barrier layer on the spacer layer, wherein the barrier layer is in contact with the spacer layer; forming a cap layer on the barrier layer, wherein the spacer layer, the barrier layer and the cap layer are made of different materials; the spacer layer is an etching stop layer during a barrier layer etching process; the barrier layer is an etching stop layer during a cap layer etching process; oxidizing the cap layer to form an oxidized cap layer on the barrier layer, wherein the oxidized cap layer is in contact with the barrier layer and made of oxynitride; and forming a passivation layer on the oxidized cap layer and forming at least a portion of the passivation layer between the oxidized cap layer and the gate electrode.

2. The manufacturing method of claim 1, wherein the spacer layer is made of aluminum nitride.

3. The manufacturing method of claim 1, wherein the oxidized cap layer is made of aluminum oxynitride.

4. The manufacturing method of claim 1, wherein the barrier layer is made of aluminum gallium nitride (Al.sub.xGa.sub.(1-x)N), and 0.1x0.4.

5. The manufacturing method of claim 1, wherein the cap layer is oxidized using a high-temperature oxidizing process, and the temperature is higher than 700 C.

6. The manufacturing method of claim 1, further comprising: forming a source electrode and a drain electrode on or above the barrier layer; and forming a gate electrode at least on or above the oxidized cap layer and between the source electrode and the drain electrode.

7. The manufacturing method of claim 6, further comprising: forming a first recess in the cap layer to expose a portion of the barrier layer; and forming a second recess in the barrier layer through the first recess to expose a portion of the spacer layer.

8. The manufacturing method of claim 7, wherein oxidizing the cap layer comprises: oxidizing the cap layer and the portion of the spacer layer together to form the oxidized cap layer and an oxidation segment in the spacer layer; and wherein forming the gate electrode comprises: further forming the gate electrode in the first recess and the second recess.

9. The manufacturing method of claim 8, further comprising: conformally forming the passivation layer in the first recess and the second recess, such that at least a portion of the passivation layer is disposed between the gate electrode and the oxidation segment of the spacer layer.

10. A method for manufacturing a semiconductor device, comprising: forming a channel layer on or above a substrate, wherein a two dimensional electron gas channel exists in the channel layer; forming a spacer layer on the channel layer, wherein the spacer layer is in contact with the channel layer; forming a barrier layer on the spacer layer, wherein the barrier layer is in contact with the spacer layer; forming a cap layer on the barrier layer, wherein the spacer layer, the barrier layer and the cap layer are made of different materials; the spacer layer is an etching stop layer during a barrier layer etching process; the barrier layer is an etching stop layer during a cap layer etching process; forming a first recess in the cap layer by etching the cap layer; forming a second recess in the barrier layer by etching the barrier layer to expose a portion of the spacer layer; and oxidizing the cap layer and the exposed spacer layer to form an oxidized cap layer and an oxidation segment, wherein the oxidized cap layer and the oxidation segment are made of different materials and the oxidized cap layer is in contact with the barrier layer and made of oxynitride.

11. The manufacturing method of claim 10, wherein the spacer layer is made of aluminum nitride.

12. The manufacturing method of claim 10, wherein the oxidized cap layer is made of aluminum oxynitride.

13. The manufacturing method of claim 10, wherein the barrier layer is made of aluminum gallium nitride (Al.sub.xGa.sub.(1-x)N), and 0.1x0.4.

14. The manufacturing method of claim 10, wherein the cap layer is oxidized using a high-temperature oxidizing process, and the temperature is higher than 700 C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A to FIG. 1E are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the first embodiment of the present invention;

(2) FIG. 2A to FIG. 2B are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the second embodiment of the present invention;

(3) FIG. 3A to FIG. 3B are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the third embodiment of the present invention;

(4) FIG. 4A to FIG. 4D are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the fourth embodiment of the present invention; and

(5) FIG. 5A to FIG. 5B are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the fifth embodiment of the present invention.

DETAILED DESCRIPTION

(6) Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

(7) FIG. 1A to FIG. 1E are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the first embodiment of the present invention. As shown in FIG. 1A, a substrate 110 is provided first. Subsequently, a buffer layer 210 is optionally formed on the substrate 110. In this embodiment, the substrate 110 can be made of sapphire, Si, or SiC, and the buffer layer 210 can be made of AlN or other suitable materials. Then, a channel layer 120 is formed on or above the substrate 110. For example, in FIG. 1A, the channel layer 120 is formed above the substrate 110 and on the buffer layer 210. In this embodiment, the channel layer 120 can be made of GaN, and the act of forming the channel layer 120 can be performed by chemical vapor deposition (CVD).

(8) Reference is made to FIG. 1B. A spacer layer 130 is formed on the channel layer 120. In this embodiment, the spacer layer 130 can be made of aluminum nitride (AlN), the thickness T1 of the spacer layer 130 can be less than 5 nm, and the act of forming the spacer layer 130 can be performed by metal organic chemical vapor deposition (MOCVD).

(9) Reference is made to FIG. 10. Subsequently, a barrier layer 140 is formed on the spacer layer 130. In this embodiment, the barrier layer 140 can be made of aluminum gallium nitride (Al.sub.xGa.sub.(1-x)N), and 0.1x0.4. The thickness T2 of the barrier layer 140 can be less than 40 nm, and the act of forming the barrier layer 140 can be performed by metal organic chemical vapor deposition (MOCVD).

(10) Reference is made to FIG. 1D. A cap layer 150 is formed on the barrier layer 140. In this embodiment, the cap layer 150 can be made of aluminum nitride (AlN), the thickness T3 of the cap layer 150 can be less than 5 nm, and the act of forming the cap layer 150 can be performed by metal organic chemical vapor deposition (MOCVD). Furthermore, the metal organic chemical vapor deposition process can be a high-temperature growth process to reduce the defect of the cap layer 150, and the performance of the cap layer 150 can be improved.

(11) Subsequently, a sacrificial layer 250 is formed on the cap layer 150. In this embodiment, the sacrificial layer 250 can be made of gallium nitride (GaN). The act of forming the sacrificial layer 250 can be performed by metal organic chemical vapor deposition (CVD). The sacrificial layer 250 is configured to prevent native oxidization. In some other embodiments, the sacrificial layer 250 can be omitted.

(12) Reference is made to FIG. 1E. Then, the cap layer 150 is oxidized (see FIG. 1D) to form an oxidized cap layer 155 on the barrier layer 140, and the sacrificial layer 250 (see FIG. 1D) is also oxidized to form an oxidized sacrificial layer (not shown). In this embodiment, the oxidized cap layer 155 can be made of aluminum oxynitride (AlON), and the act of oxidizing the cap layer 150 can be performed by high-temperature oxidizing process, such as high-temperature oxygen in furnace process or rapid thermal annealing (RTA) process, and the temperature is higher than 700 C. In some other embodiments, the act of oxidizing the cap layer 150 can be performed by oxygen-based plasma process or chemical solutions (such as hydrogen peroxide (H.sub.2O.sub.2)). The oxidized sacrificial layer can be removed by dipping the structure in dilute HCl.

(13) From a structural point of view, the semiconductor device includes the substrate 110, the channel layer 120, the spacer layer 130, the barrier layer 140, and the oxidized cap layer 155. The channel layer 120 is disposed above the substrate 110. The spacer layer 130 is disposed on the channel layer 120. The barrier layer 140 is disposed on the spacer layer 130. The oxidized cap layer 155 is disposed on the barrier layer 140. The oxidized cap layer 155 is made of oxynitride, such as aluminum oxynitride (AlON). A two-dimensional electron gas (2DEG) channel 122 exists in the channel layer 120 and near the spacer layer 130. In one or more embodiments, the semiconductor device can further include the buffer layer 210 disposed between the substrate 110 and the channel layer 120. Since the cap layer 150 is performed by high-temperature growth process, the quality of the interface of the cap layer 150 and the structure formed thereon can be improved.

(14) FIG. 2A to FIG. 2B are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the second embodiment of the present invention. The difference between the second embodiment and the first embodiment pertains to a source electrode 160, a drain electrode 170, and a gate electrode 180. Reference is made to FIG. 2A. The manufacturing processes of FIG. 1A to FIG. 1E can be performed first. Since the relevant manufacturing details are all the same as the first embodiment, and, therefore, a description in this regard will not be repeated hereinafter. Subsequently, a source electrode 160 and a drain electrode 170 are formed on the barrier layer 140. For example, a first conductive layer is formed to cover the oxidized cap layer 155 and the exposed barrier layer 140. Subsequently, the first conductive layer is patterned to form the source electrode 160 and the drain electrode 170. In one or more embodiments, an annealing process can be performed after forming the source electrode 160 and the drain electrode 170.

(15) In this embodiment, the source electrode 160 and the drain electrode 170 can be made of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or any combination thereof. The first conductive layer can be performed by physical vapor deposition process such as sputtering, or e-beam evaporation, and the first conductive layer can be patterned by lithography and etching process. The temperature of performing the annealing process can be about 800 C., and the claimed scope of the present invention is not limited in this respect.

(16) Reference is made to FIG. 2B. A gate electrode 180 is formed on the oxidized cap layer 155 and between the source electrode 160 and the drain electrode 170. For example, a second conductive layer can be formed to cover at least the oxidized cap layer 155. Subsequently, the second conductive layer is patterned to form the gate electrode 180. The gate electrode 180 can be made of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or any combination thereof. The second conductive layer can be performed by physical vapor deposition process such as sputtering, or e-beam evaporation process, and the second conductive layer can be patterned by lithography and etching process.

(17) From a structural point of view, the difference between the second embodiment and the first embodiment pertains to the source electrode 160, the drain electrode 170, and the gate electrode 180. The source electrode 160 and the drain electrode 170 are separately disposed on the barrier layer 140. The gate electrode 180 is disposed at least on the oxidized cap layer 155 and is disposed between the source electrode 160 and the drain electrode 170.

(18) A two-dimensional electron gas (2DEG) channel 122 exists in the channel layer 120 and near the spacer layer 130. The source electrode 160 can be electrically connected to the drain electrode 170 through the 2DEG channel 122. That is, the semiconductor device of this embodiment is a depletion-mode transistor. Other relevant structural details of the second embodiment are all the same as the first embodiment, and, therefore, a description in this regard will not be repeated hereinafter.

(19) FIG. 3A to FIG. 3B are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the third embodiment of the present invention. The difference between the third embodiment and the second embodiment pertains to a passivation layer 190. Reference is made to FIG. 3A. The manufacturing processes of FIG. 1A to FIG. 1E, and FIG. 2A can be performed first. Since the relevant manufacturing details are all the same as the second embodiment, and, therefore, a description in this regard will not be repeated hereinafter. Subsequently, the passivation layer 190 is formed on the oxidized cap layer 155. In this embodiment, the passivation layer 190 can be made of aluminum oxide (Al.sub.2O.sub.3), aluminum nitride (AlN), silicon nitride (Si.sub.3N.sub.4), silicon oxide (SiO.sub.2), hafnium oxide (HfO.sub.2), or any combination thereof. The passivation layer 190 can be performed by chemical vapor deposition.

(20) Reference is made to FIG. 3B. A gate electrode 180 is formed above the oxidized cap layer 155, on the passivation layer 190, and between the source electrode 160 and the drain electrode 170. For example, a second conductive layer is formed to cover at least the passivation layer 190. Subsequently, the second conductive layer is patterned to form the gate electrode 180. The gate electrode 180 can be made of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or any combination thereof. The second conductive layer can be performed by physical vapor deposition process such as sputtering, or e-beam evaporation process, and the second conductive layer can be patterned by lithography and etching process.

(21) From a structural point of view, the difference between the third embodiment and the second embodiment pertains to the passivation layer 190. In this embodiment, the passivation layer 190 is disposed on the oxidized cap layer 155, and at least a portion of the passivation layer 190 is disposed between the oxidized cap layer 155 and the gate electrode 180. The passivation layer 190 protects the underlying layers. Other relevant structural details of the third embodiment are all the same as the second embodiment, and, therefore, a description in this regard will not be repeated hereinafter.

(22) FIG. 4A to FIG. 4D are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the fourth embodiment of the present invention. The difference between the fourth embodiment and the first embodiment pertains to a source electrode 160, a drain electrode 170, a gate electrode 180, a first recess 156, and a second recess 142. Reference is made to FIG. 4A. The manufacturing processes of FIG. 1A to FIG. 1D are performed first. Since the relevant manufacturing details are all the same as the first embodiment, and, therefore, a description in this regard will not be repeated hereinafter. Subsequently, a first recess 156 is formed in the cap layer 150 to expose a portion of the barrier layer 140. The first recess 156 can be performed by lithography and etching process. In this embodiment, since the materials of the cap layer 150 (ex. AlN) and the barrier layer 140 (ex. Al.sub.xGa.sub.(1-x)N, and 0.1x0.4) are different, the barrier layer 140 can be an etching stop layer during the cap layer 150 etching process.

(23) Then, a second recess 142 is formed in the barrier layer 140 to expose a portion of the spacer layer 130. The second recess 142 can be performed by etching process using the cap layer 150 as a mask. In this embodiment, since the materials of the barrier layer 140 (ex. Al.sub.xGa.sub.(1-x)N, and 0.1x0.4) and the spacer layer 130 (ex. AlN) are different, the spacer layer 130 can be an etching stop layer during the barrier layer 140 etching process. Therefore, the spacer layer 130 prevents the channel layer 120 from being etched, and the surface of the channel layer 120 avoids etching damages, leading to a good quality of 2DEG channel.

(24) Reference is made to FIG. 4B. The cap layer 150 (see FIG. 4A) and the portion of the spacer layer 130 are oxidized together to form the oxidized cap layer 155 and an oxidation segment 132 in the spacer layer 130. In other words, the materials of the oxidized cap layer 155 and the oxidation segment 132 are both aluminum oxynitride (AlON). The act of oxidizing the cap layer 150 and the portion of the spacer layer 130 can be performed by high-temperature oxidizing process, such as high-temperature oxygen in furnace process or rapid thermal annealing (RTA) process, and the temperature is higher than 700 C. In some other embodiments, the act of oxidizing the cap layer 150 can be performed by oxygen-based plasma technique or chemical solutions (such as H.sub.2O.sub.2).

(25) Reference is made to FIG. 4C. A source electrode 160 and a drain electrode 170 are formed on the barrier layer 140. In one or more embodiments, an annealing process can be performed after forming the source electrode 160 and the drain electrode 170 to form ohmic contacts between the source electrode 160 and the barrier layer 140, and between the drain electrode 170 and the barrier layer 140.

(26) In this embodiment, the source electrode 160 and the drain electrode 170 can be made of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or any combination thereof. The source electrode 160 and the drain electrode 170 can be performed by physical vapor deposition process such as sputtering, or e-beam evaporation process, and the source electrode 160 and the drain electrode 170 can be patterned by lithography process. The temperature of performing the annealing process can be about 800 C., and the claimed scope of the present invention is not limited in this respect.

(27) Reference is made to FIG. 4D. A gate electrode 180 is formed in the first recess 156 and the second recess 142 and on the oxidized cap layer 155. For example, a conductive layer can be formed to fill the first recess 156 and the second recess 142 and cover the oxidized cap layer 155. Subsequently, the conductive layer is patterned to form the gate electrode 180. The gate electrode 180 can be made of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or any combination thereof. The conductive layer can be performed by physical vapor deposition process such as sputtering or e-beam evaporation process.

(28) From a structural point of view, the difference between the fourth embodiment and the first embodiment pertains to the configuration of the source electrode 160, the drain electrode 170, the gate electrode 180, the first recess 156, and the second recess 142. The source electrode 160 and the drain electrode 170 are both disposed on the barrier layer 140. The oxidized cap layer 155 has the first recess 156, and the barrier layer 140 has the second recess 142. The spacer layer 130 has the oxidation segment 132. The first recess 156 and the second recess 142 together expose at least a portion of the oxidation segment 132. The gate electrode 180 is disposed at least on the oxidized cap layer 155, in the first recess 156 and the second recess 142, and between the source electrode 160 and the drain electrode 170.

(29) A two-dimensional electron gas (2DEG) channel 122 exists in the channel layer 120 and near the spacer layer 130. The 2DEG channel 122 is interrupted under the first recess 156 and the second recess 142. That is, the semiconductor device of this embodiment is an enhancement-mode transistor. Other relevant structural details of the fourth embodiment are all the same as the first embodiment, and, therefore, a description in this regard will not be repeated hereinafter.

(30) FIG. 5A to FIG. 5B are cross-sectional views of a method for manufacturing a semiconductor device at different stages according to the fifth embodiment of the present invention. The difference between the fifth embodiment and the fourth embodiment pertains to the configuration of a passivation layer 190. Reference is made to FIG. 5A. The manufacturing processes of FIG. 1A to FIG. 1D, and FIG. 4A to FIG. 4C are performed first. Since the relevant manufacturing details are all the same as the fourth embodiment, and, therefore, a description in this regard will not be repeated hereinafter. Subsequently, the passivation layer 190 is conformally formed in the first recess 156 and the second recess 142. In this embodiment, the passivation layer 190 can be made of aluminum oxide (Al.sub.2O.sub.3), aluminum nitride (AlN), silicon nitride (Si.sub.3N.sub.4), silicon oxide (SiO.sub.2), Hafnium oxid (HfO.sub.2), or any combination thereof. The passivation layer 190 can be performed by chemical vapor deposition process.

(31) Reference is made to FIG. 5B. A gate electrode 180 is formed above the oxidized cap layer 155, on the passivation layer 190, and in the first recess 156 and the second recess 142. For example, a conductive layer can be formed to cover at least the passivation layer 190. Subsequently, the conductive layer is patterned to form the gate electrode 180. The gate electrode 180 can be made of titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or any combination thereof. The conductive layer can be performed by physical vapor deposition process such as sputtering, or e-beam evaporation process.

(32) From a structural point of view, the difference between the fifth embodiment and the fourth embodiment pertains to the configuration of the passivation layer 190. In this embodiment, the passivation layer 190 is conformally disposed in the first recess 156 and the second recess 142, and at least a portion of the passivation layer 190 is disposed between the gate electrode 180 and the oxidation segment 132 of the spacer layer 130. The passivation layer 190 protects the underlying layers. Other relevant structural details of the fifth embodiment are all the same as the fourth embodiment, and, therefore, a description in this regard will not be repeated hereinafter.

(33) Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

(34) It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.