BOOTSTRAP CAPACITOR GATE DRIVER

Abstract

A bootstrap gate driver charging circuit arranged to drive the gate of an upper switch (Q.sub.U) and a lower switch (Q.sub.L) connected in series to provide an AC output voltage (400) voltage by alternatively turning on and off according to a predetermined duty cycle of alternate upper switch turn-on and lower switch turn-on phases, the bootstrap gate driver charging circuit comprising: an input terminal; an output terminal; an H-bridge inverter with an inverter input and an inverter output; a charging path; and a bootstrap capacitor. The input inverter is electrically connected to the input terminal, the inverter output is electrically connected to a first end of the bootstrap capacitor, the charging path is electrically connected between a second end of the bootstrap capacitor and a gate driver supply voltage; wherein in response to the lower switch being turned ON and providing a path to ground with respect to the supply voltage.

Claims

1. A bootstrap gate driver charging circuit arranged to drive the gate of an upper switch (Q.sub.U)and a lower switch (Q.sub.L) connected in series to provide an AC output voltage voltage by alternatively turning on and off according to a predetermined duty cycle of alternate upper switch turn-on and lower switch turn-on phases, the bootstrap gate driver charging circuit comprising: an input terminal; an output terminal; a bootstrap capacitor; a charging path; and an H-bridge inverter with an inverter input and an inverter output, wherein the input inverter is electrically connected to the input terminal, the inverter output is electrically connected to a first end of the bootstrap capacitor, the charging path is electrically connected between a second end of the bootstrap capacitor and a gate driver supply voltage; wherein in response to the lower switch being turned ON and providing a path to ground with respect to the gate driver's supply voltage and in response to the lower switch being turned off, the charging circuit provides a sufficient voltage level to maintain the upper switch ON for the duration of the upper switch turn-on phase by toggling the upper and lower switches for a short period of time during the upper switch turn-on phase, so as to maintain the charge of the bootstrap capacitor during that phase.

2. The bootstrap gate driver circuit of claim 1, wherein the temporary toggling of the upper and lower switches is performed using a logic circuit configured to detect the polarity of the output voltage and, in response to detection that the polarity is negative, applying a predefined pulse to reverse the ON/OFF states of the upper and lower switches for a predetermined short period of time.

3. The bootstrap gate driver circuit of claim 1, wherein the temporary toggling of the upper and lower switches is performed using a logic circuit configured to determine when the capacitor voltage falls below a predetermined threshold voltage and, in response thereto, reversing the ON/OFF states of the upper and lower switches for a predetermined short period of time.

4. The bootstrap gate driver circuit of claim 2, wherein the short period is in the microsecond range.

5. The bootstrap gate driver circuit of claim 4, wherein the short period is 1 μs.

6. An H-bridge circuit comprising: a first set of two series connected switches arranged to switch on and off at a first frequency; and a second set of two series connected switches in parallel with the first set and arranged to switch on and off at a second frequency; and a first bootstrap gate drive charging circuit of claim 1, arranged to drive the second set of switches.

7. An H-bridge circuit as claimed in claim 6, further comprising a second bootstrap gate drive charging circuit as claimed in claim 1, arranged to drive the first set of switches.

8. An H-bridge circuit as claimed in 7, wherein the first set of switches are a different type of switch to the second set of switches.

9. An H-bridge circuit as claimed in claim 8, wherein the first set of switches are Si switches and the second set of switches are SiC or GaN switches.

10. An H-bridge circuit as claimed in claim 6, wherein the second frequency is lower than the first frequency.

11. An H-bridge circuit as claimed in claim 6, wherein the first bootstrap gate drive charging circuit is configured to reverse the ON/OFF states of the second set of switches when the first set of switches are OFF.

12. A method of controlling power supply to a gate drive of switches of an H-bridge circuit comprising upper and lower switches, by means of a bootstrap gate drive charging circuit, the method comprising: reversing the ON/OFF states of the upper and lower switches for a predetermined short period of time depending on the H-bridge circuit output voltage.

Description

BRIEF DESCRIPTION

[0011] Techniques according to the disclosure will be described in more detail by way of example only. Variation on the described examples are possible within the scope of the claims.

[0012] FIG. 1 shows an example of a conventional H-bridge inverter topology for a power converter.

[0013] FIG. 2 shows an example of a hybrid H-bridge inverter topology for a power converter.

[0014] FIG. 3 shows use of a conventional bootstrap circuit.

[0015] FIG. 4 shows use of a bootstrap circuit incorporating a boost converter.

[0016] FIG. 5 is an example of control logic for a modified bootstrap technique according to this disclosure.

[0017] FIG. 6 is an example of an alternative control logic for a modified bootstrap technique according to this disclosure.

[0018] FIG. 7A shows the low-side switch outputs and inverter output over time for a conventional bootstrap technique.

[0019] FIG. 7B shows the low-side switch outputs and inverter output over time for a modified bootstrap technique according to the disclosure.

[0020] FIG. 8A shows Fast Fourier Transform, FFT, analysis of the harmonic voltages for a conventional bootstrap technique.

[0021] FIG. 8B shows Fast Fourier Transform, FFT, analysis of the harmonic voltages for a modified bootstrap technique according to the disclosure.

DETAILED DESCRIPTION

[0022] The standard and hybrid H-bridge inverter topologies mentioned in the background, above, will be briefly described again with reference to FIGS. 1 and 2.

[0023] FIG. 1 shows a traditional Si—Si H-bridge topology comprising a first set of two semiconductor switches Q1, Q2 connected in series and a second set of Si—Si switches Q3, Q4 also connected in series and connected in parallel with the first set of switches to form an H-bridge. The bridge is connected across a DC link comprising a DC supply 10 and a DC link capacitor 20. The AC link 50 has a first terminal T1 connected at the junction between the two first switches Q1, Q2, and a second terminal T2 connected at the junction between the two second switches Q3, Q4 and provides, via a filter 30, an AC voltage output 40 to drive a load. The four switches Q1, Q2, Q3, Q4 switch on and off at the same frequency, with switches Q1 and Q4 switching in synch and switches Q2 and Q3 switching in synch. When switches Q1 and Q4 are on, switches Q2 and Q3 are off and vice versa.

[0024] FIG. 2 shows a hybrid Si—SiC or Si—GaN H-bridge topology comprising a first set of two SiC or GaN switches Q1′, Q2′ connected in series and a second set of Si switches Q3′, Q4′ also connected in series and connected in parallel with the first set of switches to form an H-bridge. The bridge is connected across a DC link comprising a DC supply 100 and a DC link capacitor 200. The AC link 500 has a first terminal T′1 connected at the junction between the two first switches Q1′, Q2′, and a second terminal T′2 connected at the junction between the two second switches Q3′, Q4′ and provides, via a filter 300, an AC voltage output 400 to drive a load. The first switches Q1′, Q2′ switch on and off at the same frequency, with switch Q1′ on when switch Q2′ is off. The second switches Q3′ and Q4′ switch on and off at a significantly lower frequency than the first switches.

[0025] As mentioned above, a bootstrap circuit is conventionally used to ensure that all upper (high side) switches are supplied with power at all times. FIG. 3 shows a simple bootstrap gate driver 60 which can be connected before the low frequency switches to provide a boost charge to the switch that is off at any one time. The design and operation of a conventional bootstrap circuit will be known to those skilled in the art, and will not be described here in detail. Briefly, a bootstrap circuit includes a bootstrap capacitor 70 associated with the leg of the H-bridge, and charging circuitry to control charging and discharging of the capacitor 70 based on the state of the switches QU, QL such that power is always provided to the upper switch QU of the leg when required. The bootstrap circuit is usually implemented with an H-bridge gate driver circuit that has two sets of series-connected switches (P-type and N-type) connected as a push-pull configuration. The mid-point between the two switches is connected to the gate of the H-bridge switch. The bootstrap capacitor 70 is connected across the two switches that drive the H-bridge upper switch. When the low side switch of the leg of the H-bridge is ON, current from the gate drive power supply flows through the bootstrap resistor RBST and the bootstrap diode DBST to charge the bootstrap capacitor 70 through the low side switch QU which connects to ground, and when the low side switch is OFF, the bootstrap capacitor remains connected to the gate driver of the high side switch and the capacitor discharges some of its energy to drive the gate of the high side switch to a sufficiently high voltage to switch the high side switch ON. Thus the charge is provided by the bootstrap capacitor 70 that charges from the on switch and discharges to power the off switch. A bootstrap circuit can be provided for each set of switches and will generally drive the upper of the two switches (Q3′—shown as Qu in FIG. 3) In FIG. 3, Q L represents the lower switch (Q4′) in a switch set (Q3′,Q4′). Where a high charge is required, rather than increasing the size of the bootstrap capacitor, additional components such as a buck or boost converter can be added as shown in FIG. 4. Here a boost converter comprising a boost inductor 80 and a boost diode 90 boosts charges from a supply to re-charge the boost capacitor 70′.

[0026] The addition of extra boost components, or increasing the size of the bootstrap capacitor, adversely affects the system efficiency and adds to the size, weight and complexity of the overall system.

[0027] The technique according to the disclosure, described below, avoids the need for larger capacitors or buck/boost components by essentially reducing the amount of capacitance needed to drive the switches.

[0028] The technique according to the disclosure modifies the use of the conventional bootstrap circuit such as shown in FIG. 3 by applying a very short pulse (in the microsecond range) to temporarily toggle the switching pattern of the low frequency switching leg of the inverter. This injection of a short ON pulse, while the output voltage 400 is negative, allows the bootstrap circuit to top up, replenishing the charge of the bootstrap capacitor 70. This means that the bootstrap capacitor 70 can continue to supply charge to the upper switch (i.e. Q3′) during the negative output voltage so that the upper switch remains powered.

[0029] The control logic for the delivery of the pulse according to one method is shown in FIG. 5, where the polarity of the output voltage Vout is detected 600 and is provided to an AND gate 700. A pulse of predefined width and timing is provide to the other input of the AND gate 700. When the polarity of the output voltage is determined to be negative, the AND gate applies a short pulse of the predefined width and timing to toggle or reverse the switching pattern of the low frequency switches Q3′ and Q4′ and to turn the high frequency switches Q1′ and Q2′ temporarily off (to avoid a short circuit). In this short time, the bootstrap capacitor will re-charge.

[0030] An alternative technique that can be used to apply a short charging pulse is shown in FIG. 6. Here, the charging pulse is applied only during the dead time or OFF time of the high frequency switches and when the bootstrap capacitor voltage drops below the switching device turn-on voltage threshold. The bootstrap capacitor voltage is compared, 800, with the gate ON threshold voltage and the result of the comparison is provided to one input of an AND gate 700′. The outputs of the two high frequency switches (Q1′, Q2′) are provided to the inputs of a NOR gate 900. If neither high-frequency switch is high (dead time) and if the bootstrap capacitor voltage is less than the threshold, the switching pattern of the low frequency switches (Q3′, Q4′) is toggled. This approach works in systems where the switching frequency of the high frequency switches is relatively low (e.g. 200 kHz so that the dead time is long enough to fit in the short re-charging pulse.

[0031] FIGS. 7A and 7B and 8A and 8B show, from tests, how the operation of the inverter is improved using the application of a short re-charging pulse according to the disclosure. As seen in FIG. 7A, for the conventional bootstrap operation, when the charge stored in the bootstrap capacitor 70 is too low, the bootstrap circuit cannot maintain the upper switch Q3′ powered on for the duration of the negative period. The switch is therefore forced to switch off to recharge the bootstrap capacitor which results in oscillations seen in the graphs. In contrast, as seen in FIG. 7B, using the techniques of this disclosure, the short re-charging pulse x is applied at a time just before it would be otherwise expected that the switch would be force off and the oscillations are, therefore, avoided.

[0032] Similarly, the FFT graphs are shown in FIGS. 8A and 8B for comparison and it can be seen that for the present technique (FIG. 8B) there are fewer and more uniform harmonic voltages.

[0033] The pulse width, bootstrap charging current and the number of times the pulse is applied can be varied according to the application and the size of the bootstrap capacitor.

[0034] The technique of this disclosure improves the efficiency of the inverter whilst minimising its size and weight. The overall system start-up and re-charging times are reduced and large spikes are avoided during the bootstrap capacitor re-charging. The modification can be implemented as an analogue or digital circuit and no additional components are required.