Wide bandgap semiconductor switching device with wide area schottky junction, and manufacturing process thereof

Abstract

A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

Claims

1. A switching device comprising: a body of semiconductor material, which has a first conductivity type and a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type, are arranged within the semiconductor body, and are spaced apart from the front surface, the contact layer, and each other by semiconductor material portions of the body.

2. The switching device according to claim 1, further comprising a plurality of connection regions of a second conductive material, which is different from the first conductive material, each connection region extending in the semiconductor body from the front surface, and contacting a corresponding buried region of the buried regions.

3. The switching device according to claim 2, wherein each connection region extends at least in part into the corresponding buried region.

4. The switching device according to claim 2, wherein the semiconductor body and the contact layer form a Schottky contact; and wherein each connection region forms an ohmic contact with the corresponding buried region.

5. The switching device according to claim 2, wherein said second conductive material is a silicide of a transition metal.

6. The switching device according to claim 1, wherein said first conductive material is a transition metal.

7. The switching device according to claim 1, wherein the body is of silicon carbide.

8. The switching device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type.

9. The switching device according to claim 1, further comprising a top layer of conductive material, which overlies, in direct contact, the contact layer and has a greater thickness than the contact layer.

10. The switching device according to claim 1, which forms a Junction-barrier Schottky diode.

11. A process for manufacturing a switching device, comprising: forming, within a body of semiconductor material having a first conductivity type and a front surface, a plurality of buried regions of a second type of conductivity, said buried regions being spaced apart from the front surface and each other by semiconductor material portions of the body; and forming, in contact with the front surface, a contact layer of a first conductive material.

12. The process according to claim 11, further comprising forming a plurality of connection regions of a second conductive material, which is different from the first conductive material, each connection region extending in the semiconductor body from the front surface and contacting a corresponding buried region of the plurality of buried regions.

13. The process according to claim 12, wherein said forming the plurality of connection regions includes extending each connection region at least in part within the corresponding buried region.

14. The process according to claim 11, wherein said forming the plurality of buried regions comprises: carrying out an ion implantation that forms in the semiconductor body a plurality of preliminary regions of a buried type; and carrying out a thermal process of activation of the ions of the preliminary regions.

15. The process according to claim 14, further comprising: forming a plurality of connection regions of a second conductive material, which is different from the first conductive material, each connection region extending in the semiconductor body from the front surface and contacting a corresponding buried region of the plurality of buried regions; forming a masking layer of dielectric material on top of said front surface; forming a plurality of trenches so that each trench traverses the masking layer, a portion of the semiconductor body, and at least part of a corresponding buried region of the plurality of buried regions; filling the trenches with filling regions of a third conductive material; getting portions of the filling regions to react thermally with the semiconductor material of the semiconductor body and form a silicide; and removing portions of the filling regions that have not reacted thermally with the semiconductor material of the semiconductor body.

16. The process according to claim 11, wherein said forming the plurality of buried regions comprises: carrying out an ion implantation that forms in the semiconductor body a plurality of preliminary regions having a temporary surface that temporarily delimits said semiconductor body; and growing an epitaxial layer on said temporary surface; said process further comprising carrying out a thermal process of activation of the ions of the preliminary regions.

17. The process according to claim 16, further comprising: forming a masking layer of dielectric material on top of said front surface; forming a plurality of trenches so that each trench traverses the masking layer, a portion of the semiconductor body, and at least part of a corresponding buried region of the plurality of buried regions; filling the trenches with filling regions of a third conductive material; getting portions of the filling regions to react thermally with the semiconductor material of the semiconductor body and form a silicide; and removing portions of the filling regions that have not reacted thermally with the semiconductor material of the semiconductor body.

18. A Junction-barrier Schottky diode comprising: a body of semiconductor material, which has a first conductivity type and a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; a buried region, of a second conductivity type, arranged within the semiconductor body, and spaced apart from the front surface and the contact layer by a portion of the body; and a connection region of a second conductive material, which is different from the first conductive material, the connection region extending in the semiconductor body from the front surface and contacting the buried region.

19. The Junction-barrier Schottky diode according to claim 18, wherein the semiconductor body and the contact layer form a Schottky contact; and wherein each connection region forms an ohmic contact with the corresponding buried region.

20. The Junction-barrier Schottky diode according to claim 18, further comprising a top layer of conductive material, which overlies, in direct contact, the contact layer and has a greater thickness than the contact layer.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) For a better understanding of the present disclosure preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

(2) FIGS. 1-4 are schematic cross-sectional views of embodiments of the present switching device;

(3) FIGS. 5A-5E are schematic cross-sectional views of the embodiment illustrated in FIG. 1, during successive steps of a manufacturing process;

(4) FIGS. 6A-6E are schematic cross-sectional views of the embodiment illustrated in FIG. 2, during successive steps of a manufacturing process;

(5) FIGS. 7A-7E are schematic cross-sectional views of the embodiment illustrated in FIG. 3, during successive steps of a manufacturing process; and

(6) FIGS. 8A-8E are schematic cross-sectional views of the embodiment illustrated in FIG. 4, during successive steps of a manufacturing process.

DETAILED DESCRIPTION

(7) FIG. 1 is a schematic illustration of the structure of a JBS diode, referred to in what follows as the diode 1.

(8) In detail, the diode 1 comprises a semiconductor body 2, which is made, for example, of a wide bandgap semiconductor, such as for example a material chosen from silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN). In what follows, without this implying any loss of generality, it is assumed that the semiconductor body 2 is of silicon carbide.

(9) The semiconductor body 2 comprises a substrate 4 of an N+ type and a first epitaxial layer 6 of an N type. The first epitaxial layer 6 is arranged on the substrate 4, with which it is in direct contact, and has a doping level lower than the doping level of the substrate 4. In addition, the semiconductor body 2 is delimited at the top and at the bottom by a first surface S.sub.a and a second surface S.sub.b, respectively, which are formed by the first epitaxial layer 6 and by the substrate 4, respectively.

(10) The diode 1 further comprises a bottom contact layer 10, which is made, for example, of nickel silicide and extends underneath the second surface S.sub.b, in direct contact with the substrate 4.

(11) The diode further comprises a conductive layer 12 and a top metallization 14.

(12) The conductive layer 12 extends over the first surface S.sub.a, in direct contact with the first epitaxial layer 6, and is of a metal, such as for example a material chosen from nickel, titanium, and molybdenum, or any transition metal.

(13) The top metallization 14 extends over the conductive layer 12 and in direct contact with the latter. Furthermore, the top metallization 14 is of a metal material, such as for example aluminum, and has a thickness greater than the thickness of the conductive layer 12. For practical purposes, the top metallization 14 is designed to contact a conductive element, such as for example a so-called lead, in order to make it possible to inject current into the diode 1 or draw off current therefrom. Consequently, the top metallization 14 is designed to withstand the mechanical stresses induced by contact with the conductive element.

(14) The diode 1 further comprises a plurality of buried regions 20, of the same semiconductor material as that of the semiconductor body 2, which are located at a distance from the first surface S.sub.a and thus do not contact the conductive layer 12.

(15) Without this implying any loss of generality, in the embodiment illustrated in FIG. 1, the buried regions 20 are of a P type and are substantially the same as one another. Further, the buried regions 20 extend to approximately the same depth as the semiconductor body 2.

(16) In greater detail, the buried regions 20 are separated from one another. In addition, in top plan view, the buried regions 20 may for example have an elongated shape (for instance, in a direction parallel to the first surface S.sub.a), or else, once again by way of example, a shape chosen from between circular and polygonal. In general, in top plan view, the buried regions 20 may thus define a strip-like or else cell-like arrangement.

(17) In even greater detail, the conductive layer 12 and the first epitaxial layer 6 are such that a so-called Schottky contact is formed between them. In the contact regions between the buried regions 20 and the first epitaxial layer 6 there PN junctions are, instead, formed. In other words, the first epitaxial layer 6 and the buried regions 20 form, respectively, cathode regions and anode regions of bipolar diodes, while the first conductive layer 12 and the first epitaxial layer 6 form, respectively, an anode region and a cathode region of a Schottky diode. In use, the Schottky contact is activated for low biasing voltages of the diode 1, whereas the PN contacts are activated at higher voltages. Furthermore, since the buried regions 20 are separate from the conductive layer 12, the Schottky contact develops over a particularly extensive area.

(18) As illustrated in FIG. 2, further possible are embodiments in which the semiconductor body 2 comprises a second epitaxial layer 24, arranged on the first epitaxial layer 6.

(19) For instance, the second epitaxial layer 24 may have approximately the same doping level as the first epitaxial layer 6. In the case where, instead, the first and second epitaxial layers 6, 24 have different doping levels, two degrees of freedom are available for optimizing, in the design stage, the compromise between forward-biasing voltage drop and reverse-biasing leakage current. Furthermore, the second epitaxial layer 24 forms the aforementioned first surface S.sub.a and a third surface S.sub.c. In particular, the second epitaxial layer 24 overlies, in direct contact, the buried regions 20, which extend into the first epitaxial layer 6 starting from the third surface S.sub.c. In practice, the third surface S.sub.c delimits the first epitaxial layer 6 at the top.

(20) FIG. 3 shows an additional embodiment, in which the diode 1 further comprises a plurality of regions 28, referred to in what follows as the connection regions 28.

(21) In detail, the connection regions 28 are of a conductive material, such as for example nickel silicide, titanium silicide, molybdenum silicide, or a silicide of a transition metal. Furthermore, each connection region 28 extends into the first epitaxial layer 6 starting from the first surface S.sub.a until it contacts a corresponding buried region 20. In addition, as illustrated precisely in FIG. 3, each connection region 28 may extend at least partially into the corresponding buried region 20, and in particular into a top portion of this buried region 20.

(22) In greater detail, the connection regions 28 and the buried regions 20 are such that the area of contact between each connection region 28 and the corresponding buried region 20 forms a corresponding ohmic contact. In this way, the diode 1 is characterized by a particular strength in forward biasing.

(23) As illustrated in FIG. 4, further possible are embodiments whereby the diode 1 includes both the connection regions 28 and the second epitaxial layer 24. In this case, the connection regions 28 extend through the second epitaxial layer 24. In particular, without this implying any loss of generality, each top region 28 comprises a top portion, which extends from the first surface S.sub.a through the second epitaxial layer 24, and a bottom portion, which extends into the corresponding buried region 20.

(24) The diode 1 illustrated in FIG. 1 can be obtained, for example, as shown in FIGS. 5A-5E and described in detail hereinafter.

(25) Initially, as illustrated FIG. 5A, the semiconductor body 2, formed by the substrate 4 and by the first epitaxial layer 6, is provided.

(26) Next, as shown in FIG. 5B, formed on the first surface S.sub.a is a hard mask 32, which defines a plurality of windows 34. In addition, using the windows 34, an implantation of a P type is carried out, represented schematically by arrows 36, for example of aluminum ions. The implantation is carried out at high energy (for example, higher than 200 keV) and with a dose ranging for example between 1.Math.10.sup.13 and 2.Math.10.sup.15 atoms/cm.sup.2. Further, this implantation leads to formation of regions 40 of a buried type, i.e., far from the first surface S.sub.a. These regions 40, referred to in what follows as the preliminary regions 40, are to form the buried regions 20.

(27) Next, as shown in FIG. 5C, the hard mask 32 is removed. Furthermore, a thermal process of activation of the implanted ions is carried out. This process is carried out at a temperature higher than 1500 C. Following upon the thermal-activation process, each preliminary region 40 forms a corresponding buried region 20.

(28) Next, as shown in FIG. 5D, deposited on the first surface S.sub.a is a masking layer 42, made, for example, of TEOS oxide. Further, the bottom contact layer 10 is formed underneath the second surface S.sub.b and in direct contact therewith, in a per se known manner and consequently not illustrated. For instance, a bottom layer of metal material (for example, nickel) is formed underneath the second surface S.sub.b and in direct contact therewith, and then a thermal process is carried out, which causes a silicidation of the aforementioned bottom layer of metal material, with consequent formation of the bottom contact layer 10.

(29) Next, as shown in FIG. 5E, the masking layer 42 is removed. In addition, the conductive layer 12 is formed on the first surface S.sub.a, for example by sputtering or evaporation.

(30) Finally, in a way not illustrated, the top metallization 14 is formed on the conductive layer 12, for example by sputtering or evaporation.

(31) As regards the embodiment illustrated in FIG. 2, it can be obtained, for example, in the way described hereinafter.

(32) After the operations illustrated in FIG. 5A have been carried out, the hard mask 32 is formed, and an implantation of a P type, represented schematically by arrows 46, is carried out, as shown in FIG. 6A. The implantation is carried out at low energy (for instance, less than 200 keV), for example with aluminum ions, and with a dose ranging, for example, between 1.Math.10.sup.13 and 2.Math.10.sup.15 atoms/cm.sup.2. Furthermore, this implantation leads to formation of the preliminary regions 40, which give out onto the top surface of the first epitaxial layer 6.

(33) Next, as shown in FIG. 6B, the hard mask 32 is removed, and then a process of epitaxial growth is carried out for forming the second epitaxial layer 24.

(34) Next, as shown in FIG. 6C, a thermal process of activation of the implanted ions is carried out. This process is carried out at a temperature higher than 1500 C. Following upon the thermal-activation process, each preliminary region 40 forms a corresponding buried region 20.

(35) Next, as shown in FIG. 6D, on the second epitaxial layer 24, and thus in contact with the first surface S.sub.a of the semiconductor body 2, the masking layer 42 is deposited. Furthermore, the bottom contact layer 10 is formed underneath the second surface S.sub.b and in direct contact therewith, for example in the way described previously.

(36) Next, as shown in FIG. 6E, the masking layer 42 is removed. Furthermore, the conductive layer 12 is formed on the second epitaxial layer 24, for example by sputtering or evaporation. Next, as described previously, the top metallization 14 is formed.

(37) As regards the embodiment shown in FIG. 3, it can be obtained in the way described hereinafter.

(38) Initially the operations illustrated in FIGS. 5A-5D are carried out.

(39) Next, as shown in FIG. 7A, a plurality of trenches 50 is formed, for example by a dry anisotropic etch. In particular, the trenches 50 are formed by a digging operation that entails selective removal of portions of the masking layer 42 and of the first epitaxial layer 6.

(40) In greater detail, each trench 50 extends from the top surface (designated by S.sub.d) of the masking layer 42 and traverses, beyond the masking layer 42, a corresponding portion of the first epitaxial layer 6, arranged between the masking layer 42 and a corresponding buried region 20, until it extends in part into said corresponding buried region 20. In particular, a bottom portion of each trench 50 extends through a top portion of the corresponding buried region 20. Consequently the bottom of each trench 50 extends into the corresponding buried region 20.

(41) Next, as shown in FIG. 7B, formed on the masking layer 42 and within the trenches 50 is a layer 54 of metal material (for example, nickel, titanium or molybdenum), referred to in what follows as the filling layer 54. The filling layer 54 is obtained, for example, by sputtering or evaporation and fills the trenches 50 completely.

(42) Next, as shown in FIG. 7C, a thermal process is carried out at a temperature comprised between 600 C. and 1100 C., and for a duration comprised between 10 and 300 minutes, during which the portions of the filling layer 54 arranged in contact with the semiconductor material undergo a silicidation process, at the end of which they form corresponding connection regions 28. The portion of filling layer 54 that does not undergo any reaction is instead designated by 55 in FIG. 7C.

(43) As shown in FIG. 7D, the non-reacted portion 55 of the filling layer 54 is then removed.

(44) Next, as shown in FIG. 7E, the masking layer 42 is removed; further, the conductive layer 12 is formed on the first epitaxial layer 6. Next, in a way not illustrated, the top metallization 14 is formed.

(45) As regards the embodiment illustrated in FIG. 4, it can be obtained, for example, in the way described hereinafter.

(46) Initially, the operations illustrated in FIGS. 6A-6D are carried out.

(47) Next, as shown in FIG. 8A, the trenches 50 are formed, for example once again by a dry anisotropic etch. In particular, the trenches 50 are formed by a digging operation that involves selective removal of portions of the masking layer 42 and of the second epitaxial layer 24.

(48) In greater detail, each trench 50 extends from the top surface (designated by S.sub.d) of the masking layer 42 and traverses, beyond the masking layer 42, a corresponding portion of the second epitaxial layer 24, arranged between the masking layer 42 and a corresponding buried region 20, until it extends in part into said corresponding buried region 20. In particular, a bottom portion of each trench 50 extends through a top portion of the corresponding buried region 20. Consequently the bottom of each trench 50 extends into the corresponding buried region 20.

(49) Next, as shown in FIG. 8B, the filling layer 54 is formed on the masking layer 42 and within the trenches 50.

(50) Next, as shown in FIG. 8C, a thermal process is carried out at a temperature comprised between 600 C. and 1100 C., and for a duration comprised between 10 and 300 minutes, during which the portions of the filling layer 54 arranged in contact with the semiconductor material undergo a silicidation process, at the end of which they form corresponding connection regions 28. The portion of filling layer 54 that does not undergo any reaction is instead designated by 55 in FIG. 8C.

(51) As shown in FIG. 8D, the non-reacted portion 55 of the filling layer 54 is subsequently removed.

(52) Next, as shown in FIG. 8E, the masking layer 42 is removed. Further, the conductive layer 12 is formed on the second epitaxial layer 24. Next, in a way not illustrated, the top metallization 14 is formed.

(53) The switching device described presents numerous advantages. In particular, it can be shown that the present switching device presents substantially the same electrical field as a so-called JBS trench diode; i.e., it has a value of electrical field lower than the one set up in planar JBS structures, but has a wider Schottky-contact area and thus has a wider useful area for passage of current. Furthermore, the present switching device is characterized by lower leakage currents, as well as by a forward-biasing voltage drop lower than what occurs, for example, in planar JBS structures.

(54) Finally, it is clear that modifications and variations can be made to the device and to the manufacturing method described and illustrated herein, without thereby departing from the scope of the present disclosure.

(55) For instance, the types of doping may be reversed with respect to what has been described herein.

(56) As regards the manufacturing process, the order of the steps may be different from what has been described herein. In addition, the manufacturing process may include further steps other than the ones described. For instance, the manufacturing process may include, in a per se known manner, a so-called step of definition of the active area, which envisages formation of field-oxide regions (not illustrated) delimiting the area in which the JBS diode is to be obtained.

(57) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.