PREPARATION METHOD OF SILICON-BASED MOLECULAR BEAM HETEROEPITAXY MATERIAL, MEMRISTOR, AND USE THEREOF

Abstract

A preparation method of a silicon-based molecular beam heteroepitaxy material, a memristor, and use thereof are provided. A structure of the heteroepitaxy material is obtained by allowing a SrTiO.sub.3 layer, a La.sub.0.67Sr.sub.0.33MnO.sub.3 layer, and a (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 layer to successively grow on a P-type Si substrate. The silicon-based epitaxy structure is obtained by allowing a first layer of SrTiO.sub.3, a second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3, and a third layer of (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 (in which an atomic ratio of BaTiO.sub.3 to CeO.sub.2 is 0.5:0.5) to successively grow at a specific temperature and a specific oxygen pressure. The preparation method of a silicon-based molecular beam heteroepitaxy material adopts pulsed laser deposition (PLD), which is relatively simple and easy to control, and can achieve the memristor function and neuro-imitation characteristics. A thickness of the first buffer layer of SrTiO.sub.3 can reach 40 nm.

Claims

1. A preparation method of a silicon-based molecular beam heteroepitaxy material, comprising the following steps: (a) fixing a cleaned Si substrate on a substrate platform in a cavity of a pulsed laser deposition (PLD) device, and vacuum-pumping the cavity to 1×10.sup.−4 Pa to 5×10.sup.−4 Pa; (b) raising a temperature in the cavity to 90° C. to 110° C., and introducing Ar into the cavity to maintain a gas pressure in the cavity at 0.8 Pa to 1.2 Pa; turning on a laser to conduct pre-sputtering of a SrTiO.sub.3 target for 1 min to 2 min and then conduct formal sputtering of the SrTiO.sub.3 target to form a SrTiO.sub.3 film with a thickness of 4 nm to 8 nm; after the sputtering is completed, introducing N.sub.2 into the cavity to maintain the gas pressure in the cavity at 90 Pa to 110 Pa; further raising the temperature in the cavity to 550° C. to 650° C., and pumping out the gas from the cavity to 1×10.sup.−4 Pa to 5×10.sup.−4 Pa; introducing O.sub.2 into the cavity, and adjusting an interface valve to maintain the gas pressure in the cavity at 0.8 Pa to 1.2 Pa; and raising the temperature in the cavity to 680° C. to 720° C., turning on the laser to conduct the pre-sputtering of the SrTiO.sub.3 target for 1 min to 2 min; (c) raising the temperature in the cavity to 740° C. to 760° C., and conducting the formal sputtering of the SrTiO.sub.3 target for 10 min to 20 min to form a first layer of SrTiO.sub.3 on the cleaned Si substrate; (d) adjusting an O.sub.2 pressure to 20 Pa to 30 Pa, and conducting the pre-sputtering of a La0.67Sr.sub.0.33MnO.sub.3 target for 1 min to 2 min and then the formal sputtering of the La.sub.0.67Sr.sub.0.33MnO.sub.3 target for 20 min to 40 min to form a second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3 on the first layer of SrTiO.sub.3; (e) adjusting the O.sub.2 pressure to 0.8 Pa to 1.2 Pa, and conducting the pre-sputtering of a BTO-CeO.sub.2 target for 1 min to 2 min and then the formal sputtering of the BTO-CeO.sub.2 target for 10 min to 20 min to form a third layer of BTO-CeO.sub.2 on the second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3; and (f) adjusting the O.sub.2 pressure to 2×10.sup.4 Pa to 5×10.sup.4 Pa, annealing in-situ, and taking a. product out after the product is cooled to room temperature.

2. The preparation method according to claim 1, wherein in step (a), a Si substrate is subjected to ultrasonic cleaning successively in acetone and alcohol, a diluted hydrofluoric (HF) acid solution is used to remove SiO.sub.2, and the Si substrate is subjected to ultrasonic cleaning in deionized water to obtain the cleaned Si substrate, and then the cleaned Si substrate is taken out and blow-dried with N.sub.2.

3. The preparation method according to claim 1, wherein during a preparation process, a temperature procedure is set as follows: step 1: raising from 0° C. to 100° C. in 5 min; step 2: keeping at 100° C. for 3 min; step 3: raising from 100° C. to 500° C. in 30 min; step 4: raising from 500° C. to 750° C. in 25 min; step 5: keeping at 750° C. for 90 min; and step 6: decreasing from 750° C. to 0° C. in 150 min.

4. The preparation method according to claim 1, wherein during a preparation process, the laser is set to be in an EGY NGR mode, a frequency of the pre-sputtering is set to 1 HZ to 3 HZ, and a frequency of the formal sputtering is set to 3 HZ to 7 HZ.

5. The preparation method according to claim 1, wherein the first, second, and third layers have thicknesses of 42 nm, 30 nm, and 40 nm, respectively.

6. The preparation method according to claim 1, wherein crystal phases of the first, second, and third layers are (001)(002); (001)(002); and (001)(002).sub.BTO and (002)(004).sub.CeO2, respectively.

7. The preparation method according to claim 1, wherein an atomic ratio of BaTiO.sub.3 to CeO.sub.2 in the third layer is 0.5:0.5.

8. A memristor, wherein a structure of the memristor is Obtained by allowing a Pd top electrode layer to grow on a silicon-based molecular beam heteroepitaxy material prepared by the preparation method according to claim 1.

9. The memristor according to claim 8, wherein the Pd top electrode layer has a thickness of 30 nm to 50 nm and a diameter of 80 μm to 100 μm.

10. A method of using the memristor according to claim 8, comprising using the memristor in neuro-imitation devices and ferroelectric devices.

11. The memristor according to claim 8, wherein in step (a), a Si substrate is subjected to ultrasonic cleaning successively in acetone and alcohol, a diluted hydrofluoric (HF) acid solution is used to remove SiO.sub.2, and the Si substrate is subjected to ultrasonic cleaning in deionized water to obtain the cleaned Si substrate, and then the cleaned Si substrate is taken out and blow-dried with N.sub.2.

12. The memristor according to claim 8, wherein during a preparation process, a temperature procedure is set as follows: step 1: raising from 0° C. to 100° C. in 5 min; step 2: keeping at 100° C. for 3 min; step 3: raising from 100° C. to 500° C. in 30 min; step 4: raising from 500° C. to 750° C. in 25 min; step 5: keeping at 750° C. for 90 min; and step 6: decreasing from 750° C. to 0° C. in 150 min.

13. The memristor according to claim 8, wherein during a preparation process, the laser is set to be in an EGY NGR mode, a frequency of the pre-sputtering is set to 1 HZ to 3 HZ, and a frequency of the formal sputtering is set to 3 HZ to 7 HZ.

14. The memristor according to claim 8, wherein the first, second, and third layers have thicknesses of 42 nm, 30 nm, and 40 nm, respectively.

15. The memristor according to claim 8, wherein crystal phases of the first, second, and third layers are (001)(002); (001)(002); and (001)(002).sub.BTO and (002)(004).sub.CeO2 respectively.

16. The memristor according to claim 8, wherein an atomic ratio of BaTiO.sub.3 to CeO.sub.2 in the third layer is 0.5:0.5.

17. The memristor according to claim 11, wherein the Pd top electrode layer has a thickness of 30 nm to 50 nm and a diameter of 80 μm to 100 μm.

18. The memristor according to claim 12, wherein the Pd top electrode layer has a thickness of 30 nm to 50 nm and a diameter of 80 μm to 100 μm.

19. The memristor according to claim 13, wherein the Pd top electrode layer has a thickness of 30 nm to 50 nm and a diameter of 80 μm to 100 μm.

20. The memristor according to claim 14, wherein the Pd top electrode layer has a thickness of 30 nm to 50 nm and a diameter of 80 μm to 100 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 is a schematic diagram of a structure of a sample prepared by the method of the present disclosure, where 1 represents a substrate, 2. represents a first epitaxial layer, 3 represents a second epitaxial layer, and 4 represents a third epitaxial layer.

[0033] FIG. 2 is a schematic diagram of a structure of a PM sputtering device used in the preparation of the present disclosure, where (a) represents a cavity, (h) represents a gate valve, (c) represents a laser beam, (d) represents a substrate platform, € represents a target platform, (f) represents a tableting platform, and (g) represents a target.

[0034] FIG. 3 is an atomic force microscopy (AFM) image of a sample obtained in Example 2.

[0035] FIG. 4 is an XRD pattern of a sample obtained in Example 2.

[0036] FIG. 5 shows a current change recorded by scanning the sample of Example 2 at a continuous voltage of −10 V to 10 V, which shows the memristor characteristics, wherein a resistance changes from high to low during a process of 0 V.fwdarw.+10 V.fwdarw.0 V (from 1 to 2) and a resistance changes from low to high during a process of 0 V.fwdarw.−10 V.fwdarw.0 V (from 3 to 4).

[0037] FIGS. 6A-6F show TEM images of the sample in Example 2.

[0038] FIG. 7 shows a test result of the φ scan of epitaxial layers of the sample in Example 2.

[0039] FIGS. 8A-8D show the neurological imitation of spiking-time-dependent plasticity (STDP) and paired-pulse facilitation (PPF) realized by modulating the resistance of the memristor.

[0040] FIG. 9 shows a P-E ferroelectric test result.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The present disclosure will be further described below in conjunction with examples, but the following examples are only for illustration and do not limit the protection scope of the present disclosure in any way.

Example 1 Epitaxy sample

[0042] As shown in FIG. 1, a structure of an epitaxy sample prepared by the method of the present disclosure includes a bottommost substrate 1, a first epitaxial layer 2 on the substrate 1, a second epitaxial layer 3 on the first epitaxial layer 2, and a third epitaxial layer 4 on the second epitaxial layer 3. The substrate 1 is a Si substrate, and the epitaxial layers are the first epitaxial layer SrTiO.sub.3, the second epitaxial layer La.sub.0.67Sr.sub.0.33MnO.sub.3, and the third epitaxial layer BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 from bottom to top.

Example 2 Silicon-based molecular beam heteroepitaxy method

[0043] The preparation method of the present disclosure included the following steps:

[0044] 1. A suitable substrate was prepared.

[0045] P-type Si was adopted as a substrate. The Si substrate was subjected to ultrasonic cleaning in acetone for 10 min and then in alcohol for 10 min, then soaked in a diluted HF acid solution for 90 seconds, taken out by wooden clips and subjected to ultrasonic cleaning in deionized water for 5 min, and finally taken out and blow-dried with N.sub.2.

[0046] 2. The Si substrate was placed in a cavity of a PLD device and the cavity was vacuum-pumped.

[0047] As shown in FIG. 2, the cavity (a) of the PLD device was opened, and a tableting platform (f) was taken out, polished with sandpaper to remove surface stains, washed with acetone to remove waste resulting from the polishing and organic matters adhered on the surface, and finally wiped with alcohol. The cleaned substrate (namely, Si substrate) was placed on the tableting platform (f) coated with silver glue (to enable uniform heat) for tableting, and during the tableting, the substrate was firmly pressed on the tableting platform (f) to ensure the uniform growth of a film during sputtering. The prepared tableting platform was placed and fixed on a substrate platform (d) in the cavity, and then the cavity (a) was closed and vacuum-pumped to 5×10.sup.−4 Pa.

[0048] 3. A gas was introduced.

[0049] There were four target platforms (e) located directly opposite to the tableting platform (f) (with a thermocouple wire for temperature control) in the cavity, and targets of the first, second, and third epitaxial layers were respectively placed on the target platforms (e) (with an empty one). A laser beam (c) outside the device was irradiated on the target platforms directly facing the tableting platform (f) through a glass window for initiation.

[0050] In this step, the thermocouple wire in the tableting platform (f) was heated first, then oxygen in the cavity (a) was pumped out by controlling a gate valve (b); a temperature in the cavity was raised to 100° C., and Ar was introduced to form a pressure of 1 Pa; then SrTiO.sub.3 was sputtered for 1 min, and N.sub.2 was introduced to maintain a pressure of 100 Pa; the temperature was raised to 600° C., and then the gas in the cavity was pumped out to maintain a pressure of 5×10.sup.−4 Pa; O.sub.2 was introduced into the cavity at a flow rate of 25 sccm, and the gate valve (b) was adjusted to maintain a pressure in the cavity at 1 Pa; a laser controller was set to be in an EGY NGR mode; and then the pre-sputtering of the SrTiO.sub.3 target was conducted for 1 min to 2 min at a pulse frequency of 2 HZ, and the formal sputtering of the target was conducted at a pulse frequency of 5 HZ and a temperature of 700° C.

[0051] 4. Epitaxy of a first layer of SrTiO.sub.3

[0052] After the pre-sputtering of SrTiO.sub.3, the formal sputtering was conducted for 15 min, and a resulting sample stood for 10 min, such that the first layer of SrTiO.sub.3 with a thickness of 42 nm was epitaxially formed on the Si substrate.

[0053] 5. Epitaxy of a second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3

[0054] After the first layer of SrTiO.sub.3 was formed, the gate valve (b) was adjusted to maintain the pressure in the cavity at 26 Pa, the pre-sputtering of LaSrMnO.sub.3 was conducted for 1 min to 2 min, and then the formal sputtering of the target was conducted for 30 min; and a resulting sample stood for 10 min, such that a second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3 with a thickness of 30 nm was epitaxially formed on the first layer of SrTiO.sub.3.

[0055] 6. Epitaxy of a third layer of (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5

[0056] After the second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3 was formed, the gate valve (b) was adjusted to maintain the pressure in the cavity at 1 Pa, the pre-sputtering of (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 was conducted for 1 min to 2 min, and then the formal sputtering of the target was conducted for 15 min; and a resulting sample stood for 10 min, such that a third layer of BTO-CeO.sub.2 with a thickness of 40 nm was epitaxially formed on the second layer of L.sub.0.67Sr.sub.0.33MnO.sub.3. Then the gate valve (b) was adjusted to maintain the pressure in the cavity at 3×10.sup.4 Pa, and a resulting sample was annealed in-situ, and then taken out after being cooled to room temperature.

[0057] A Pd top electrode with a thickness of 40 nm and a diameter of 90 μm was allowed to grow on the sample in a magnetron sputtering device, and an LSMO layer was adopted as a bottom electrode, such as to determine the I-V and pulse electrical properties and ferroelectric properties.

[0058] FIG. 3 shows two randomly-selected AFM images with different sizes (5 μm and 10 μm), The scan results show that the sample prepared by this method has an extremely smooth surface, with a surface undulation only of 3.3 nm to 3.4 nm.

[0059] FIG. 4 is an XRD pattern determined at a random position. The XRD pattern shows that the three layers growing exhibit particularly obvious diffraction, and the obtained crystal phase can further prove that the three layers prepared by this method are all formed through epitaxy.

[0060] FIG. 5 shows an I-V curve of the top electrode sample prepared in Example 2. The top electrode is Pd formed through magnetron sputtering, and the bottom electrode is a second epitaxial layer of LSMO. It can he seen from the figure that the device also has obvious high and low resistance states, but the resistance changes slowly between the high resistance state and the low resistance state; that is, there are many obvious and definite resistance states between the high resistance state and the low resistance state, which is fully in line with the memristor characteristics in current scientific research.

[0061] FIGS. 6A-6F show the TEM test results of the sample in Example 2, where FIG. 6A verifies that the obtained sample has a structure of BaTiO.sub.3—CeO.sub.2/L.sub.0.67Sr.sub.0.33MnO.sub.3/SrTiO.sub.3/Si from top to bottom; FIG. 6B shows the diffraction results, which verify the XRD test results of FIG. 4 and further prove that the sample prepared by this method is obtained through epitaxy; FIG. 6C to FIG. 6F show the crystallization and excessive heterojunction of the layers, respectively, where STO is a buffer layer, the initial growth presents an excessive state, and an epitaxy crystalline state is presented after a period time of growth, which verifies that the prepared sample is obtained through epitaxy.

[0062] FIG. 7 shows the epitaxial φ scan test results of the epitaxial layers CeO.sub.2 and LSMO, which further verify the epitaxy.

[0063] FIGS. 8A-8D show the neurological imitation of STDP and PPF realized by modulating the resistance of the memri stor.

[0064] FIG. 9 shows a P-E ferroelectric test result.