Nano-scale superconducting quantum interference device and manufacturing method thereof

Abstract

A nano-scale superconducting quantum interference device and a manufacturing method thereof, comprising the following steps of: S1: providing a substrate and growing a first superconducting material layer thereon; S2: forming a photo-resist layer and performing patterning; S3: etching the first superconducting material layer in a predetermined region; S4: covering a layer of insulation material on a top and a side of a structure obtained in step S3; S5: growing a second superconducting material layer; S6: removing the structure above the plane where the upper surface of the first superconducting material layer locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer is inserted; S7: forming at least one nanowire vertical to the insulating interlayer, to obtain the nano-scale superconducting quantum interference device. The width of the superconducting ring and the length of the nano junction are determined by the insulating interlayer.

Claims

1. A manufacturing method of a nano-scale superconducting quantum interference device, at least comprising the following steps of: S1: providing a substrate, and growing a first superconducting material layer thereon; S2: forming a photo-resist layer on a surface of the first superconducting material layer, and patterning the photo-resist layer, to expose the surface of the first superconducting material layer in a predetermined region; S3: etching the first superconducting material layer in the predetermined region, to expose the substrate, and to reserve remaining photo-resist; S4: covering a layer of insulation material on a top and a side of a structure obtained in step S3; S5: growing a second superconducting material layer on the insulation material, such that an upper surface of the second superconducting material layer in the predetermined region is flush with an upper surface of the first superconducting material layer; S6: removing the structure above the plane where the upper surface of the first superconducting material layer locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer is inserted; S7: on a surface of the plane superconducting structure, forming at least one nanowire vertical to the insulating interlayer and connecting the first superconducting material layer with the second superconducting material layer, so as to form two nano-junctions in parallel, to obtain the nano-scale superconducting quantum interference device.

2. The manufacturing method of the nano-scale superconducting quantum interference device according to claim 1, characterized in that: in step S3, after etching the first superconducting material layer in the predetermined region to expose the substrate, a further over etching is performed to form a recess region in the substrate; in step S4, the part of the insulation material located in the recess region exactly fills the recess region.

3. The manufacturing method of the nano-scale superconducting quantum interference device according to claim 1, characterized in that: the thickness of the insulating interlayer is ranged from 1 nm to 10 nm.

4. The manufacturing method of the nano-scale superconducting quantum interference device according to claim 1, characterized in that: a material of the substrate is selected from at least one of MgO, sapphire, Si.sub.3N.sub.4, Al.sub.2O.sub.3 and SiO.sub.2.

5. The manufacturing method of the nano-scale superconducting quantum interference device according to claim 1, characterized in that: materials of the first superconducting material layer and the second superconducting material layer are selected from at least one of Nb, NbN, NbTi and NbTiN.

6. A nano-scale superconducting quantum interference device, at least comprising a plane superconducting structure and at least one nanowire formed on a surface of the plane superconducting structure, characterized in that: the plane superconducting structure comprises a substrate, a first superconducting material layer and a second superconducting material layer formed on the substrate separately; an insulating interlayer is formed between the first superconducting material layer and the second superconducting material layer; an insulation material is formed between the second superconducting material layer and the substrate; the nanowire is vertical to the insulating interlayer and connects the first superconducting material layer with the second superconducting material layer, so as to form two nano-junctions in parallel.

7. The nano-scale superconducting quantum interference device according to claim 6, characterized in that: the device comprises an insulating interlayer and two nanowires vertical to the insulating interlayer; the first superconducting material layer and the second superconducting material layer are respectively formed at two sides of the insulating interlayer and are connected by the nanowires.

8. The nano-scale superconducting quantum interference device according to claim 6, characterized in that: the device comprises an insulating interlayer and two nanowires vertical to the insulating interlayer; the first superconducting material layer and the second superconducting material layer are respectively formed at two sides of the insulating interlayer and are connected by the nanowires; the region between the two nanowires of the device is formed with a groove or channel; the groove or channel digs through the insulating interlayer, and penetrates the first superconducting material layer and the second superconducting material layer.

9. The nano-scale superconducting quantum interference device according to claim 6, characterized in that: the device comprises two insulating interlayers and one nanowire vertical to the insulating interlayer; one end of the first superconducting material layer is formed between the two insulating interlayers, and the other end extends outwardly; the second superconducting material layer has a U-shaped portion, and a rear portion formed at a closing end of the U-shaped portion; open flanking end portions of the U-shaped portion are respectively located at the outer side of the two insulating interlayers, a groove or channel is formed between the end portion of the first superconducting material layer located between the two insulating interlayers and the closing end of the U-shaped portion of the second superconducting material layer; the groove or channel penetrates the first superconducting material layer and the second superconducting material layer.

10. The nano-scale superconducting quantum interference device according to claim 6, characterized in that: the device comprises two insulating interlayers and one nanowire vertical to the insulating interlayer; the first superconducting material layer is formed between the two insulating interlayers; the second superconducting material layer is a rectangular circuit loop, a pair of sides of the rectangular circuit loop are respectively located at the outer sides of the two insulating interlayers, and another pair of sides respectively form a groove or channel with the first superconducting material layer; the groove or channel penetrates the first superconducting material layer and the second superconducting material layer.

11. The nano-scale superconducting quantum interference device according to claim 6, characterized in that: the thickness of the insulating interlayer is ranged from 1 nm to 10 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic, cross-sectional diagram showing a growth of a first superconducting material layer on a substrate in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(2) FIG. 2 is a schematic diagram showing a formation of a photo-resist layer in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(3) FIG. 3 is a schematic diagram showing a patterning of the photo-resist layer in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(4) FIG. 4 is a schematic diagram showing an etching of the first superconducting material layer in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(5) FIG. 5 is a schematic diagram showing a covering of an insulation material in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(6) FIG. 6 is a schematic diagram showing a growth of a second superconducting material layer in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(7) FIG. 7 is a schematic diagram showing a formation of a plane superconducting structure in the manufacturing method of the nano-scale superconducting quantum interference device of the present invention.

(8) FIG. 8 is schematic, cross-sectional diagram of the nano-scale superconducting quantum interference device the present invention.

(9) FIG. 9 is a top view of the structure shown in FIG. 8.

(10) FIG. 10 is a top view of the nano-scale superconducting quantum interference device in a second embodiment of the present invention.

(11) FIG. 11 is a schematic, cross-sectional diagram of the nano-scale superconducting quantum interference device in a third embodiment of the present invention.

(12) FIG. 12 is a schematic, cross-sectional diagram of a structure obtained in step S4 of the nano-scale superconducting quantum interference device in a fourth embodiment of the present invention.

(13) FIG. 13 is a top view of the nano-scale superconducting quantum interference device in the fourth embodiment of the present invention.

(14) FIG. 14 is a top view of the nano-scale superconducting quantum interference device in a fifth embodiment of the present invention.

ILLUSTRATIONS OF REFERENCE SIGNS

(15) 1 substrate

(16) 2 first superconducting material layer

(17) 3 photo-resist layer

(18) 4 insulation material

(19) 5 second superconducting material layer

(20) 6 insulating interlayer

(21) 7 nanowire

(22) 8 channel

(23) d thickness of the insulating interlayer

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(24) The embodiment modes of the present invention are described hereunder through specific examples, and persons skilled in the art may easily understand other advantages and efficacies of the present invention from the contents disclosed in the present description. The present invention may be further implemented or applied through other different specific embodiment modes, and various modifications or amendments may also be made to each of the details in the present description based on different perspectives and applications without departing from the spirit of the present invention.

(25) Please refer to FIG. 1 to FIG. 14. It is to be noted that the drawings provided in the present embodiment only explain the basic conception of the present invention in an illustrative manner, so the drawings only display the components relevant to the present invention rather than being drawn according to the number, shape and size of the components during actual implementation, the shape, number and scale of each component may be randomly changed during its actual implementation, and the layout of the components thereof might also be more complicated.

(26) The present invention provides a manufacturing method of a nano-scale superconducting quantum interference device, at least comprising the following steps of:

(27) S1: providing a substrate, and growing a first superconducting material layer thereon;

(28) S2: forming a photo-resist layer on a surface of the first superconducting material layer, and patterning the photo-resist layer, to expose the surface of the first superconducting material layer in a predetermined region;

(29) S3: etching the first superconducting material layer in a predetermined region, to expose the substrate, and to reserve remaining photo-resist;

(30) S4: covering a layer of insulation material on a top and a side of a structure obtained in step S3;

(31) S5: growing a second superconducting material layer on the insulation material, such that an upper surface of the second superconducting material layer in the predetermined region is flush with an upper surface of the first superconducting material layer;

(32) S6: removing the structure above the plane at which the upper surface of the first superconducting material layer locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer is inserted;

(33) S7: on a surface of the plane superconducting structure, forming at least one nanowire vertical to the insulating interlayer and connecting the first superconducting material layer with the second superconducting material layer, so as to form two nano junctions in parallel, to obtain the nano-scale superconducting quantum interference device.

(34) The present invention further provides a nano-scale superconducting quantum interference device, at least comprising a plane superconducting structure and at least one nanowire formed on a surface of the plane superconducting structure, the plane superconducting structure comprises a substrate, a first superconducting material layer and a second superconducting material layer formed on the substrate separately; an insulating interlayer is formed between the first superconducting material layer and the second superconducting material layer; an insulation material is formed between the second superconducting material layer and the substrate; the nanowire is vertical to the insulating interlayer and connects the first superconducting material layer with the second superconducting material layer, so as to form two nano junction in parallel.

First Embodiment

(35) The present invention provides a manufacturing method of a nano-scale superconducting quantum interference device, firstly refer to FIG. 1, perform step S1: providing a substrate 1, and growing a first superconducting material layer 2 on the substrate 1.

(36) Specifically, a material of the substrate 1 is selected from at least one of MgO, sapphire, Si.sub.3N.sub.4, Al.sub.2O.sub.3 and SiO.sub.2, or other material which allows a superconducting thin film to grow on. In the present embodiment, the substrate 1 is preferably a MgO substrate.

(37) The meterail of the first superconducting material layer 2 is selected from at least one of Nb, NbN, NbTi and NbTiN, or other superconducting materials. The thickness of the first superconducting material layer is ranged from 10 nm to 200 nm. In the present embodiment, preferably, the substrate 1 is grown with a NbN layer of 50 nm by using the magnetron sputtering method.

(38) Please refer to FIGS. 2 and 3, perform step S2: spin coating a photo-resist layer 3 with a thickness of 2001000 nm on a surface of the first superconducting material layer 2, and patterning the photo-resist layer 3 by UV exposure and development, to expose the surface of the first superconducting material layer 2 in a predetermined region.

(39) As an example, the photo-resist layer 3 has a thickness of 200 nm, a rectangular graphic mask with a line width of 2 microns is adopted to perform the UV exposure, and further development to pattern the photo-resist layer 3. In the present embodiment, a left side of the substrate is taken as the predetermined region as an example, as shown in FIG. 3. However, it should be noted that, according to different sizes and different functions of the nanoSQUID device to be prepared, the lithographic pattern herein may be changed accordingly, i.e., the pattern in the predetermined region may be changed as well. The above herein is by way of example only, and is not intended to excessively limit the scope of the invention.

(40) Please refer to FIG. 4, perform step S3: etching the first superconducting material layer 2 in the predetermined region, i.e, removing the first superconducting material layer that is not covered by the photo-resist, to expose the substrate 1, and to reserve remaining photo-resist.

(41) Please refer to FIG. 5, perform step S4: covering a layer of insulation material 4 on a top and a side of a structure obtained in step S3.

(42) Specifically, reserving the photo-resist, and growing an insulation material with a thickness of 110 nm on the top and side of the structure as shown in FIG. 4 by taking advantage of the isotropic characteristics of the magnetron sputtering growth method. As shown in FIG. 5, an upper surface of the exposed portion of the substrate 1 and an upper surface of the photo-resist layer 3 are formed with insulation material 4, the first superconducting material layer 2 and a side of the photo-resist layer 3 are also formed with insulation material 4. In the present embodiment, as an example, the insulation material is MgO with a thickness of 5 nm, and in other embodiments, the insulation material may also be Si.sub.3N.sub.4, Al.sub.2O.sub.3, SiO.sub.2, and the like.

(43) Please refer to FIG. 6, perform step S5: growing a second superconducting material layer 5 on the insulation material 4, such that an upper surface of the second superconducting material layer 5 in the predetermined region is flush with an upper surface of the first superconducting material layer 2.

(44) Specifically, the material of the second superconducting material layer 5 is same to that of the first superconducting material layer 2, and the thickness thereof equals to thickness of the first superconducting material layer 2 minus the thickness of the insulation material 4, such that the upper surface of the second superconducting material layer 5 in the predetermined region is flush with the upper surface of the first superconducting material layer 2. In the present embodiment, as an example, the second superconducting material layer 5 is NbN with a thickness of 45 nm.

(45) Please refer to FIG. 7, perform step S6: stripping the photo-resist layer 3 to remove the structure above the plane where the upper surface of the first superconducting material layer 2 locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer 6 is inserted.

(46) As shown in FIG. 7, in the plane superconducting structure, the insulation material 4 is formed between the second superconducting material layer 5 and the substrate, while the insulation material between the first superconducting material layer 2 and the second superconducting material layer 5 serves as an insulating interlayer 6.

(47) Please refer to FIGS. 8 and 9, perform step S7: spin coating electron beam photo-resist on the surface of the plane superconducting structure; electron beam lithographing a nanowire pattern and developing; growing a superconducting thin film; on a surface of the plane superconducting structure, forming at least one nanowire 6 vertical to the insulating interlayer 6 and connecting the first superconducting material layer 2 with the second superconducting material layer 5, so as to form two nano junction in parallel; afterwards, stripping the electron beam photo-resist, to obtain the nano-scale superconducting quantum interference device.

(48) As an example, spin coating electron beam photo-resist on the surface of the plane superconducting structure; electron beam lithographing a nanowire pattern having two parallel wires with a space of 10 nm and a width of 10 nm, and developing; growing a NbN superconducting film of 10 nm; afterwards, stripping the electron beam photo-resist, to form a nanoSQUID with a superconducting ring area of 50 nm.sup.2. In other embodiments, the distance between the two nanowires may be further shortened, to obtain a smaller superconducting ring area.

(49) It should be noted that, the abovementioned nano junction refers to the superconducting thin film in the region overlapped by the nanowire and the insulating interlayer, and its length and width are respectively determined by the thickness of the insulating interlayer and the width of the nanowire; the superconducting ring refers to the region surrounded by the two nano-junctions, the first superconducting layer and the second superconducting layer, and its minimum width and length are respectively determined by the space of the nanowires and the thickness of the insulating interlayer.

(50) FIG. 8 is a schematic, cross-sectional diagram of the nano-scale superconducting quantum interference device, and FIG. 9 is a top view of the structure. Wherein, FIG. 9 shows the thickness d of the insulating interlayer. In the present embodiment, the surface of the plane superconducting structure is formed with two nanowires 6, so as to form two nano junctions in parallel, to form the nanoSQUID.

(51) In the manufacturing method of the nano-scale superconducting quantum interference device of the present invention, the length of the nano junction and the width of the superconducting ring are determined by the growth thickness of the insulation material, and the size thereof are controllable at the atomic thickness scale, the objects that the length of the nano junction is smaller than the coherence length of the superconducting material, and the size of the superconducting ring is greatly reduced can be achieved simultaneously. On the other hand, the superconducting ring and the nano junction are respectively achieved by two main steps, which may separate the thickness of superconducting ring and the thickness of nano-junction, increase the thickness of the superconducting material at two ends of the nano junction, eliminate the phase gradient diffusion of superconducting current in the region besides the nano-junction, thereby increasing the modulation depth of the device.

(52) The present invention further provides a nano-scale superconducting quantum interference device. Please refer to FIG. 8, it is shown to a schematic, cross-sectional diagram of the device; as shown in the figure, the device at least comprises a plane superconducting structure and at least one nanowire 7 formed on a surface of the plane superconducting structure, the plane superconducting structure comprises a substrate 1, a first superconducting material layer 2 and a second superconducting material layer 5 formed on the substrate separately; an insulating interlayer 6 is formed between the first superconducting material layer 2 and the second superconducting material layer 5; insulation material 4 is formed between the second superconducting material layer 5 and the substrate 1; the nanowire 7 is vertical to the insulating interlayer 6 and connects the first superconducting material layer 2 with the second superconducting material layer 5.

(53) In the present embodiment, the device comprises an insulating interlayer 6 and two nanowires 7 vertical to the insulating interlayer 6; please refer to FIG. 9, it is shown to a top view of the device; as shown in figure, the first superconducting material layer 2 and the second superconducting material layer 5 are respectively formed at two sides of the insulating interlayer 6 and are connected by the nanowire 7.

(54) Specifically, the thickness of the insulating interlayer 6 is ranged from 1 nm to 10 nm, in the present embodiment, preferably, 5 nm (i.e., a coherence length of the NbN thin film).

(55) In the nano-scale superconducting quantum interference device of the present invention, the line width of the nano junction is relative small (110 nm), which is less than the coherence length of the superconducting material, and may help to decrease the critical current of the nanoSQUID; moreover, the thickness of the superconducting ring is not limited by the nano junction, as a result, it may eliminate the phase gradient diffusion of superconducting current in the region besides the nano junction by increasing the thickness of the superconducting material at two ends of the nano junction, thereby increasing the modulation depth of the device.

Second Embodiment

(56) The first embodiment has provided a specific implementation manner of the nano-scale superconducting quantum interference device and the manufacturing method thereof of the present invention, however, according to different sizes and different functions of the device, the device may adopt other graphic designs, and the corresponding manufacturing method may be slightly adjusted.

(57) Please refer to FIG. 10, in view of the manufacturing method of the nano-scale superconducting quantum interference device in the first embodiment, the present embodiment further forms a groove or channel in the region between the two nanowires; the groove or channel digs through the insulating interlayer and penetrates the first superconducting material layer and the second superconducting material layer. FIG. 10 is a top view of the device structure obtained in the present embodiment, wherein, the channel 8 is shown, which penetrates the superconducting material layer and the substrate 1. The channel 8 may also be replaced by a groove, which penetrates the superconducting material layer but not the substrate. The object of providing the channel or groove is to increase the area of the superconducting ring according to requirements of the device designs.

(58) In the present embodiment, the nano-scale superconducting quantum interference device comprises an insulating interlayer and two nanowires vertical to the insulating interlayer; the first superconducting material layer and the second superconducting material layer are respectively formed at two sides of the insulating interlayer and are connected by the nanowires; the region between the two nanowires of the device is formed with a groove or channel; the groove or channel digs through the insulating interlayer and penetrates the first superconducting material layer and the second superconducting material layer. The thickness of the insulating interlayer is ranged from 1 nm to 10 nm.

Third Embodiment

(59) The approach adopted in the present embodiment is basically same to that in the first embodiment, and is different in that: in step S3, etching the first superconducting material layer in the predetermined region and exposing the substrate; after that, further performing proper over etching to form a recess region in the substrate; in step S4, the part of the insulation material located in the recess region exactly fills the recess region.

(60) Please refer to FIG. 11, it is shown to a schematic, cross-sectional diagram of the nano-scale superconducting quantum interference device formed in the present embodiment. With respect to the first embodiment, the nano-scale superconducting quantum interference device in the present embodiment has the advantages in that: the first superconducting material layer 2 has a same thickness to the second superconducting material layer 3, which makes the device more symmetrical, while the insulation material 4 between the second superconducting material layer 2 and the substrate 1 serves as a portion of the substrate, which has no harmful impact on the device.

Fourth Embodiment

(61) The approach adopted in the present embodiment is basically same to that in the first embodiment, and is different in that: the nano-scale superconducting quantum interference device formed in the first embodiment only has one insulating interlayer, while the nano-scale superconducting quantum interference device formed in the present embodiment has two insulating interlayers and a nanowire vertical to the insulating interlayer. During manufacturing, it may be achieved by the basically same method in the first embodiment by changing the graphic design.

(62) Specifically, in the first embodiment, the predetermined region is one side of the substrate, while in the present embodiment, the predetermined region is two sides of the substrate.

(63) Please refer to FIG. 12, it is shown to a sectional diagram of the structure obtain in step S4 of the present embodiment; as shown in the figure, the region at two sides of the first superconducting material layer 2 is removed, so as to form a portion of the insulation material 4 at two sides of the middle first superconducting material layer 2; by subsequently forming the second superconducting material layer and stripping the photo-resist, a nano-scale superconducting quantum interference device with two insulating interlayers can be obtained.

(64) Please refer to FIG. 13, it is shown to a top view of the nano-scale superconducting quantum interference device finally obtained in the present embodiment. The device comprises two insulating interlayers and one nanowire 7 vertical to the insulating interlayer 6; one end of the first superconducting material layer 2 is formed between the two insulating interlayers, and the other end extends outwardly; the second superconducting material layer 5 has a U-shaped portion, and a rear portion formed at a closing end of the U-shaped portion; open flanking end portions of the U-shaped portion are respectively located at the outer side of the two insulating interlayers, a groove or channel 8 is formed between the end portion of the first superconducting material layer 2 located between the two insulating interlayers and the closing end of the U-shaped portion of the second superconducting material layer 5; the groove or channel penetrates the first superconducting material layer 2 and the second superconducting material layer 5. The thickness of the insulating interlayer is ranged from 1 nm to 10 nm.

(65) Comparing to the first embodiment, the nano-scale superconducting quantum interference device in the present embodiment has the following advantages: the device in the first embodiment comprises two nanowires, and is not easy to maintain consistency of the line width during the formation, with the result that the two nano-junctions are apt to have different sizes, and the device performance is influenced as well; while in the present embodiment, the device just comprises one nanowire with a consistent line width, so that the two nano junctions are the same size.

Fifth Embodiment

(66) The approach adopted in the present embodiment is basically same to that in the fourth embodiment, and is different in the graphic design. The nano-scale superconducting quantum interference device formed in the present embodiment may be used as a gradiometer for avoiding background magnetic field interference. Please refer to FIG. 14, it is shown to a top view of the nano-scale superconducting quantum interference device formed in the present embodiment. As shown in figure, The device comprises two insulating interlayers and one nanowire 7 vertical to the insulating interlayer 6; the first superconducting material layer 2 is formed between the two insulating interlayers. The second superconducting material layer 5 is a rectangular ring, a pair of sides of the rectangular circuit loop are respectively located at the outer sides of the two insulating interlayers 6, and another pair of sides respectively form a groove or channel 8 with the first superconducting material layer 2; the groove or channel penetrates the first superconducting material layer 2 and the second superconducting material layer 5. The thickness of the insulating interlayer is ranged from 1 nm to 10 nm.

(67) From the above, in the present invention, when manufacturing the nano-scale superconducting quantum interference device, the superconducting ring and the nano junction are respectively achieved by two main steps. As for the nano-scale superconducting quantum interference device manufactured by the present invention, a space between the first superconducting material layer and the second superconducting material layer is determined by the inserted insulating interlayer, and its width is controllable at the atomic scale, which may be up to 110 nm. Another feature is to separately generate a superconducting nanowire vertical to an insulating gap by using the electron beam lithography, so as to form the nanoSQUID on the original superconducting structure, wherein the thickness of the insulating interlayer simultaneously determines the width of the superconducting loop (superconducting ring) and the length of the nano junction, while the line width of the nanowire and the space between two nanowires also simultaneously determine the width of the nano junction and the length of the superconducting loop. In the present invention, the objects that the length of the nano junction is smaller than the coherence length of the superconducting material, and the size of the superconducting ring is greatly reduced may be achieved simultaneously, and the sensitivity of the device on a small amount of spins can be increased. The structure generated by using the electron beam lithography is simple, and is easy to achieve the limit width of such technology; besides, the width of the nano junction of the prepared nanoSQUID is less than that of the prior art, which helps to decrease the critical current of the nanoSQUID. Therefore, the present invention effectively overcomes a variety of disadvantages in the prior art and has high industrial utility value.

(68) The abovementioned embodiments only illustratively describe the principle and efficacy of the present invention, rather than being used to limit the present invention. Any person skilled in the art may modify or amend the abovementioned embodiments without departing from the spirit and scope of the present invention. Thus, all equivalent modifications or amendments accomplished by persons having common knowledge in the technical field concerned without departing from the spirit and technical thoughts revealed by the present invention shall still be covered by the claims of the present invention.