SILICON-BASED SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 110.sup.14 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.

Claims

1. A method for manufacturing a semiconductor device, comprising: fabricating a silicon-based substrate having a first portion provided on a front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, the first impurity concentration being 110.sup.14 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3, and a thickness of the second portion being larger than a thickness of the first portion; and forming a nitride compound semiconductor layer which is on the front surface of the silicon-based substrate, wherein a thickness of the first portion is set to be 1 m or more and 10 m or less, and the first impurity concentration is gradually reduced from the second portion toward the surface of the first portion.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the second impurity concentration is set to be 110.sup.19 atoms/cm.sup.3 or more and 110.sup.20 atoms/cm.sup.3 or less.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of fabricating the silicon-based substrate comprises: a stage of preparing the silicon-based substrate having the second impurity concentration as a whole; and a stage of forming a silicon-based semiconductor layer having the first impurity concentration on the silicon-based substrate by epitaxial growth.

4. The method for manufacturing a semiconductor device according to claim 2, wherein the step of fabricating the silicon-based substrate comprises: a stage of preparing the silicon-based substrate having the second impurity concentration as a whole; and a stage of forming a silicon-based semiconductor layer having the first impurity concentration on the silicon-based substrate by epitaxial growth.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the step of fabricating the silicon-based substrate comprises: a stage of preparing the silicon-based substrate having the second impurity concentration as a whole; and a stage of giving a thermal treatment to the silicon-based substrate to outwardly diffuse an impurity in a substrate surface.

6. The method for manufacturing a semiconductor device according to claim 2, wherein the step of fabricating the silicon-based substrate comprises: a stage of preparing the silicon-based substrate having the second impurity concentration as a whole; and a stage of giving a thermal treatment to the silicon-based substrate to outwardly diffuse an impurity in a substrate surface.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

8. The method for manufacturing a semiconductor device according to claim 2, wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

9. The method for manufacturing a semiconductor device according to claim 3, wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

10. The method for manufacturing a semiconductor device according to claim 4, wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

11. The method for manufacturing a semiconductor device according to claim 5, wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

12. The method for manufacturing a semiconductor device according to claim 6, wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0046] FIG. 1 is a schematic cross-sectional view showing an embodiment of a silicon-based substrate according to the present invention;

[0047] FIG. 2 is a schematic cross-sectional view showing an embodiment of a semiconductor device according to the present invention;

[0048] FIG. 3 is a graph showing a relationship between an amount of warpage of the substrate and impurity concentration in the substrate, and a relationship between crystallinity of a semiconductor layer as an upper layer and impurity concentration in the substrate; and

[0049] FIG. 4 is a view showing a definition of the amount of warpage of the substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] The present invention will now be described in detail as an embodiment with reference to the drawings, but the present invention is not restricted thereto.

[0051] As described above, when boron concentration in a silicon substrate is increased to improve a warpage of a silicon substrate, there occurs a problem that crystallinity of a nitride compound semiconductor layer grown on the silicon substrate is degraded.

[0052] Thus, the present inventors repeatedly conducted keen investigations about a silicon-based substrate in which the crystallinity of a nitride compound semiconductor layer formed as an upper layer thereof can be maintained excellently while improving a warpage of the substrate.

[0053] Consequently, the present inventors have found out that, when impurity concentration in a first portion of the silicon-based substrate on a front surface side is set to be lower than impurity concentration in a second portion of the silicon-based substrate on an inner side and the impurity concentration in this first portion is set to be 110.sup.14 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3, the crystallinity of the nitride compound semiconductor layer formed as the upper layer can be maintained excellently and a warpage of the silicon-based substrate that occurs during formation of the nitride compound semiconductor layer, can be improved since the second portion provided on the inner side has the high impurity concentration, thereby bringing the present invention to completion.

[0054] FIG. 1 is a schematic cross-sectional view showing an example of the silicon-based substrate.

[0055] FIG. 1(a) shows a silicon-based substrate famed by epitaxially growing a silicon-based semiconductor layer having first impurity concentration on the silicon-based substrate having second impurity concentration as a whole.

[0056] FIG. 1(b) shows a silicon-based substrate formed by giving a thermal treatment to a silicon-based substrate having the second impurity concentration as a whole to outwardly diffuse an impurity in a substrate surface.

[0057] The silicon-based substrate shown in FIG. 1(a) will be first described.

[0058] As shown in FIG. 1(a), a silicon-based substrate 12 has a first portion 14 on a front surface side thereof and a second portion 13 on an inner side of the first portion 14. The first portion 14 is provided on only one surface side (an upper surface side in the drawing: that is, a side where a nitride compound semiconductor layer is formed) of the silicon-based substrate 12.

[0059] Here, the silicon-based substrate 12 is made of, e.g., Si or SiC.

[0060] The impurity concentration in the first portion 14 is 110.sup.14 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3.

[0061] If the impurity concentration is less than 110.sup.19 atoms/cm.sup.3, the crystallinity of the nitride compound semiconductor layer formed on an upper side of the silicon-based substrate can be excellently maintained.

[0062] Further, if the impurity concentration is 110.sup.14 atoms/cm.sup.3 or more, the impurity concentration can be easily controlled.

[0063] The impurity concentration in the first portion 14 is lower than the impurity concentration in the second portion 13. That is, the impurity concentration in the second portion 13 is higher than the impurity concentration in the first portion 14. Consequently, strength of the silicon-based substrate 12 can be raised, and the warpage of the silicon-based substrate 12 can be reduced.

[0064] It is preferable for the impurity concentration of the second portion 13 to be 110.sup.19 atoms/cm.sup.3 or more and 110.sup.20 atoms/cm.sup.3 or less. When the impurity concentration is 110.sup.19 atoms/cm.sup.3 or more, the warpage of the silicon-based substrate can be more effectively improved. Furthermore, when the impurity concentration is 110.sup.20 atoms/cm.sup.3 or less, the crystallinity of the silicon-based substrate 12 can be excellently maintained, and the crystallinity of the nitride compound semiconductor layer formed on the upper side of the silicon-based substrate can be thereby excellently maintained.

[0065] Moreover, it is preferable that a thickness of the first portion 14 is 1 m or more and 10 m or less and the thickness of the first portion 14 is smaller than a thickness of the second portion 13.

[0066] If the thickness of the first portion 14 is 1 m or more, since the impurity concentration of the silicon-based substrate surface is not increased by diffusion of the impurity from the second portion of the silicon-based substrate on the inner side even when the nitride compound semiconductor layer is foamed on the upper side of the silicon-based substrate, the crystallinity of the nitride compound semiconductor layer famed on the upper side of the silicon-based substrate can be assuredly improved.

[0067] Moreover, if the thickness of the first portion 14 is 10 m or less, the thickness of the silicon-based substrate 12 is not increased beyond necessity.

[0068] Additionally, if the thickness of the first portion 14 is smaller than the thickness of the second portion 13, the warpage of the silicon-based substrate can be assuredly improved.

[0069] Here, the impurity doped in the silicon-based substrate 12 can be, e.g., at least one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon.

[0070] As the impurity doped in the silicon-based substrate 12, the above-described elements can be preferably used.

[0071] The silicon-based substrate in FIG. 1(b) will now be described.

[0072] A silicon-based substrate 12 shown in FIG. 1(b) is similar to the silicon-based substrate 12 shown in FIG. 1(a), but a difference lies in that a first portion 14 on a front surface side is provided on an entire surface (i.e., an upper surface, a lower surface, and a side surface) of the silicon-based substrate 12.

[0073] That is because the first portion 14 is formed by out diffusion using a thermal treatment. Further, a bulk portion of the substrate becomes a second portion 13.

[0074] A semiconductor device using the silicon-based substrate according to the present invention will now be described.

[0075] FIG. 2 is a schematic cross-sectional view showing an example of a semiconductor device according to the present invention.

[0076] A semiconductor device 11 according to the present invention shown in FIG. 2 includes the silicon-based substrate 12 shown in FIG. 1(a), an initial layer 15 provided on the silicon-based substrate 12, a buffer layer 16 provided on the initial layer 15, and an operation layer 22 provided on the buffer layer 16.

[0077] The operation layer 22 has a channel layer 19 and a barrier layer 20 provided on the channel layer 19.

[0078] The first portion 14 on the front surface side of the silicon-based substrate 12 has impurity concentration lower than that in the second portion 13 on the inner side of the silicon-based substrate, this first portion has a thickness that is 1 m or more and 10 m or less, the impurity concentration in this first portion is gradually reduced toward the front surface, and the impurity concentration in this first portion is 110.sup.14 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3.

[0079] The semiconductor device 11 further has a first electrode 26, a second electrode 28, and a control electrode 30 provided on the operation layer 22.

[0080] In the semiconductor device 11, the first electrode 26 and the second electrode 28 are arranged such that an electric current can flow from the first electrode 26 to the second electrode 28 through a two-dimensional electron gas 24 famed in the channel layer 19.

[0081] The electric current flowing between the first electrode 26 and the second electrode 28 can be controlled by an electric potential applied to the control electrode 30.

[0082] Furthermore, the buffer layer 16 has a multilayer structure in which a first layer 17 and a second layer 18 having a composition different from that of the first layer 17 are alternately stacked.

[0083] Moreover, the initial layer 15, the buffer layer 16, and the operation layer 22 constitute a nitride compound semiconductor layer 25.

[0084] It is to be noted that the silicon-based substrate 12 shown in FIG. 1(a) is used as the silicon-based substrate in the above described, but the silicon-based substrate 12 shown in FIG. 1(b) can be used as the silicon-based substrate.

[0085] In the semiconductor device 11, likewise, the crystallinity of the nitride compound semiconductor layer famed on the upper side of the substrate can be excellently maintained while improving a warpage of the substrate.

[0086] A method for manufacturing a semiconductor device according to the present invention will now be described.

[0087] First, a silicon-based substrate is fabricated. Specifically, the silicon-based substrate 12 shown in FIG. 1(a) or the silicon-based substrate 12 shown in FIG. 1(b) is fabricated.

[0088] In case of fabricating the silicon-based substrate 12 shown in FIG. 1(a), for example, a silicon single-crystal ingot having the second impurity concentration is fabricated by a CZ method, this ingot is sliced and subjected to surface processing to prepare a silicon-based substrate having the second impurity concentration as a whole, and then a silicon-based semiconductor layer having the first impurity concentration lower than the second impurity concentration can be epitaxially grown on this silicon-based substrate, thereby fabrication of the silicon-based substrate 12 can be carried out.

[0089] The first impurity concentration can be controlled based on concentration of a dopant gas introduced during the epitaxial growth. Additionally, a thickness of the first portion 14 can be controlled by adjusting a thickness of the epitaxial layer to be grown.

[0090] In case of fabricating the silicon-based substrate 12 shown in FIG. 1(b), a silicon-based substrate having the second impurity concentration as a whole fabricated similarly to the above-described method is prepared, and a thermal treatment is given to this silicon-based substrate to outwardly diffuse impurities in a substrate surface, thereby the fabrication of the silicon-based substrate 12 can be carried out.

[0091] The first impurity concentration and a thickness of the first portion 14 can be controlled by adjusting a temperature and a time of the thermal treatment that effects the out diffusion.

[0092] As described above, it is possible to fabricate the silicon-based substrate that has the first portion provided on the front surface side having the first impurity concentration and the second portion having the second impurity concentration higher than the first impurity concentration and provided on the inner side of the first portion, and in which the first impurity concentration is 110.sup.14 atoms/cm.sup.3 or more and less than 110.sup.19 atoms/cm.sup.3, and the thickness of the second portion is larger than the thickness of the first portion.

[0093] Although manufacture of a semiconductor device using the silicon-based substrate 12 will be described hereinafter, but the manufacture can be likewise performed when the silicon-based substrate 12 is used.

[0094] Then, the initial layer 15 is formed on the silicon-based substrate 12. Specifically, the initial layer 15 made of AlN is grown 10 to 300 nm by an MOVPE (metal organic vapor phase epitaxy) method.

[0095] Then, the buffer layer 16 is formed on the initial layer 15. Specifically, a first layer 17 made of AlN and a second layer 18 made of GaN are alternately grown by the MOVPE method. A film thickness of the first layer 17 is, e.g., 3 to 7 nm, and a film thickness of the second layer 18 is, e.g., 2 to 7 nm. This process is repeated for, e.g., 1 to 15 times.

[0096] Then, the operation layer 22 is formed on the buffer layer 16. Specifically, the channel layer 19 made of GaN and a barrier layer 20 made of AlGaN are sequentially grown on the buffer layer 16 by the MOVPE method. A film thickness of the channel layer 19 is, e.g., 1000 to 4000 nm, and a film thickness of the barrier layer 20 is, e.g., 10 to 50 nm.

[0097] Subsequently, the first electrode 26, the second electrode 28, and the control electrode 30 are formed on the barrier layer 20. Each of the first electrode 26 and the second electrode 28 can be formed of, e.g., a stacked film of Ti/Al, and the control electrode 30 can be famed of a stacked film consisting of a lower film made of a metal oxide such as SiO or SiN and an upper film made of a metal such as Ni, Au, Mo, or Pt.

[0098] The semiconductor device 11 shown in FIG. 2 can be obtained by the above-described manufacturing method.

EXAMPLES

[0099] The present invention will now be more specifically described hereinafter based on an example and comparative examples, but the present invention is not restricted thereto.

Example 1

[0100] As a silicon-based substrate, a silicon substrate 12 in which a first portion 14 has boron concentration of 310.sup.18 atoms/cm.sup.3 and a second portion 13 has boron concentration of 210.sup.19 atoms/cm.sup.3 was used, and a semiconductor device was fabricated by the above-described method.

[0101] In regard to the semiconductor device according to Example 1, crystallinity of a nitride compound semiconductor layer as an upper layer and an amount of warpage of the substrate were measured.

[0102] It is to be noted that the crystallinity was measured with the use of a full-width at half maximum (arcsec) of a peak waveform of XRD (X-ray diffraction). Further, as to the amount of warpage of the substrate, as shown in FIG. 4, a difference between a height of a central portion of the substrate and a height of the outermost periphery of the substrate was defined as an amount of warpage x. Here, warping convexly means warping to raise the central portion of the substrate as shown in FIG. 4 when the nitride compound semiconductor layer is arranged to face upward.

[0103] Table 1 shows a measurement result.

Comparative Example 1

[0104] A semiconductor device was fabricated similarly to Example 1. However, as a silicon-based substrate, a single-layer silicon substrate having boron concentration of 210.sup.19 atoms/cm.sup.3 was used.

[0105] In regard to the semiconductor device according to Comparative Example 1, similarly to Example 1, crystallinity of a nitride compound semiconductor layer as an upper layer and an amount of warpage of the substrate were measured.

[0106] Table 1 shows a measurement result.

Comparative Example 2

[0107] A semiconductor device was fabricated similarly to Example 1. However, as a silicon-based substrate, a single-layer silicon substrate having boron concentration of 310.sup.18 atoms/cm.sup.3 was used.

[0108] In regard to the semiconductor device according to Comparative Example 2, similarly to Example 1, crystallinity of a nitride compound semiconductor layer as an upper layer and an amount of warpage of the substrate were measured.

[0109] Table 1 shows a measurement result.

TABLE-US-00001 TABLE 1 Crystallinity Substrate Substrate of semi- bulk boron surface boron conductor concen- concen- layer as an Amount of tration tration upper layer warpage of [atoms/cm.sup.3] [atoms/cm.sup.3] [arcsec]* substrate Example 1 2 10.sup.19 3 10.sup.18 560 10 to 50 m convexly Comparative 2 10.sup.19 2 10.sup.19 700 10 to 50 m Example 1 convexly Comparative 3 10.sup.18 3 10.sup.18 560 10 to 200 m Example 2 convexly *a full-width at half maximum of a peak waveform of XRD (X-ray diffraction)

[0110] As can be understood from Table 1, in Comparative Example 1 in which the boron concentration in the substrate is high as a whole, a variation in amount of warpage of the substrate is reduced, but, on the other hand, the crystallinity of the nitride compound semiconductor layer as the upper layer is degraded (a larger half value width of XRD represents poor crystallinity).

[0111] Further, in Comparative Example 2 in which the boron concentration in the substrate is low as a whole, the crystallinity of the nitride compound semiconductor layer as the upper layer is excellent but, on the other hand, a variation in amount of warpage of the substrate is large.

[0112] As compared with the above description, in Example 1, a variation in amount of warpage of the substrate is reduced, and the crystallinity of the nitride compound semiconductor layer as the upper layer is excellently maintained.

[0113] Referring to FIG. 3 in which the result in Table 1 is reflected, it can be understood that both of a reduction in variation in amount of warpage of the substrate and an improvement in crystallinity of the nitride compound semiconductor layer as the upper layer cannot be achieved in Comparative Example 1 and Comparative Example 2 of the single-layer structure, but both of the reduction in amount of warpage of the substrate and the improvement in crystallinity of the nitride compound semiconductor layer can be achieved in Example 1.

[0114] It is to be noted that the present invention is not restricted to the foregoing embodiment. The foregoing embodiment is an illustrated example, and any example that has substantially the same configuration and exercises the same functions and effects as the technical concept described in claims of the present invention is included in the technical scope of the present invention.