Gating control module transistor circuit for a gate driving method to switch between interlaced and progressive driving of the gate lines

Abstract

The present disclosure discloses a gate driving method, a driving apparatus of a display panel and a display apparatus. The driving apparatus may be in two driving modes, i.e., a first mode and a second mode. In the first mode, due to a reduced number of gate lines to be driven when various frames of images are displayed, the power consumption can be reduced. In addition, due to the effect of persistence of vision of human eyes, better quality of display images can be ensured while reducing power consumption. In the second mode, as respective lines of gate lines are driven progressively when various frames of images are displayed, the display panel is enabled to have better quality of display images. By switching the driving apparatus between the first mode and second mode, a number of gate lines to be driven can be reduced so as to reduce power consumption.

Claims

1. A driving apparatus of a display panel, comprising: a first gate driver connected to a first trigger signal terminal, configured to drive odd lines of gate lines on the display panel; a second gate driver connected to a second trigger signal terminal, configured to drive even lines of gate lines on the display panel; a first gating control module, connected in series between the first trigger signal terminal and the first gate driver; and a second gating control module, connected in series between the second trigger signal terminal and the second gate driver; wherein, the first gating control module and the second gating control module each comprises a mode control signal terminal configured to receive a mode control signal, and the first gating control module and the second gating control module are configured to respectively control the first gate driver and the second gate driver to drive in a first mode when the mode control signal is in a first state; and respectively control the first gate driver and the second gate driver to drive in a second mode when the mode control signal is in a second state; wherein, in the first mode, when odd frames of images are displayed, the odd lines of gate lines are driven sequentially by the first gate driver, and when even frames of images are displayed, the even lines of gate lines are driven sequentially by the second gate driver; or, when the odd frames of images are displayed, the even lines of gate lines are driven sequentially by the second gate driver, and when the even frames of images are displayed, the odd lines of gate lines are driven sequentially by the first gate driver; and in the second mode, when various frames of images are displayed, respective lines of gate lines are driven progressively; wherein the first gating control module further comprises a first gating clock signal terminal, and the second gating control module further comprises a second gating clock signal terminal; wherein the first gating control module comprises a first transistor, a second transistor, and a third transistor, wherein, the first transistor and the second transistor each has a gate which is the mode control signal terminal of the first gating control module and a source connected to the first trigger signal terminal, the first transistor has a drain connected to a source of the third transistor, and the second transistor has a drain respectively connected to the first gate driver and a drain of the third transistor; wherein the third transistor has a gate which is the first gating clock signal terminal of the first gating control module; and wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor; or the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

2. The driving apparatus according to claim 1, wherein the first gating clock signal terminal is configured to receive a first gating clock signal, and the second gating clock signal terminal is configured to receive a second gating clock signal; wherein the first gating clock signal and the second gating clock signal have opposite phases and a same period which is a sum of a display time of two frame cycles; wherein when the mode control signal is in the first state, the first gating control module transmits a first trigger signal transmitted by the first trigger signal terminal to the first gate driver to drive the odd lines of gate lines sequentially when the first gating clock signal is a valid signal, and the second gating control module transmits a second trigger signal transmitted by the second trigger signal terminal to the second gate driver to drive the even lines of gate lines sequentially when the second gating clock signal is a valid signal; wherein when the mode control signal is in the second state, the first gating control module transmits the first trigger signal to the first gate driver to drive the odd lines of gate lines sequentially; and the second gating control module transmits the second trigger signal to the second gate driver to drive the even lines of gate lines sequentially.

3. A display apparatus, comprising the driving apparatus according to claim 2.

4. The driving apparatus according to claim 1, wherein the second gating control module comprises a fourth transistor, a fifth transistor, and a sixth transistor, wherein, the fourth transistor and the fifth transistor each has a gate which is the mode control signal terminal of the second gating control module and a source connected to the second trigger signal terminal, the fourth transistor has a drain connected to a source of the sixth transistor, and the fifth transistor has a drain respectively connected to the second gate driver and a drain of the sixth transistor; the sixth transistor has a gate which is the second gating clock signal terminal of the second gating control module; and the fourth transistor is an N-type transistor, and the fifth transistor is a P-type transistor; or the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

5. The driving apparatus according to claim 4, wherein both the third transistor and the sixth transistor are N-type transistors or P-type transistors.

6. A display apparatus, comprising the driving apparatus according to claim 5.

7. A display apparatus, comprising the driving apparatus according to claim 4.

8. A display apparatus, comprising the driving apparatus according to claim 1.

9. A gate driving method of a display panel as claimed in claim 1, the driving method comprising: controlling a driving manner of the first gate driver and the second gate driver to be a first mode when the mode control signal is in a first state, and controlling the driving manner of the first gate driver and the second gate driver to switch from the current first mode to a second mode when the mode control signal changes to being in a second state from being in the first state; and controlling the driving manner of the first gate driver and the second gate driver to be the second mode when the mode control signal is in the second state, and controlling the driving manner of the first gate driver and the second gate driver to switch from the current second mode to the first mode when the mode control signal changes to being in the first state from being in the second state; wherein, in the first mode, when odd frames of images are displayed, the odd lines of gate lines are driven sequentially, and when even frames of images are displayed, the even lines of gate lines are driven sequentially; or, when the odd frames of images are displayed, the even lines of gate lines are driven sequentially, and when the even frames of images are displayed, the odd lines of gate lines are driven sequentially; and in the second mode, when various frames of images are displayed, respective lines of gate lines are driven progressively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a structural diagram of a driving apparatus according to an embodiment of the present disclosure;

(2) FIG. 2a illustrates a structural diagram of a first example of a first gating control module according to an embodiment of the present disclosure;

(3) FIG. 2b illustrates a structural diagram of a first example of a second gating control module according to an embodiment of the present disclosure;

(4) FIG. 3a illustrates a structural diagram of a second example of a first gating control module according to an embodiment of the present disclosure;

(5) FIG. 3b illustrates a structural diagram of a second example of a second gating control module according to an embodiment of the present disclosure; and

(6) FIG. 4 illustrates a timing diagram of a circuit of a driving apparatus according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(7) Specific implementations of a gate driving method and driving apparatus of a display panel and a display apparatus according to an embodiment of the present disclosure will be described in detail below in combination with accompanying drawings.

(8) As shown in FIG. 1, in an embodiment of the present disclosure, a driving apparatus of a display panel is provided, including a first gate driver 110 connected to a first trigger signal terminal, configured to drive odd lines of gate lines Gate(2n-1) on the display panel; a second gate driver 210 connected to a second trigger signal terminal, configured to drive even lines of gate lines Gate(2n) on the display panel, where n is a positive integer larger than or equal to 1; a first gating control module 120, connected in series between the first trigger signal terminal and the first gate driver 110; and a second gating control module 220, connected in series between the second trigger signal terminal and the second gate driver 210.

(9) The first gating control module 120 and the second gating control module 220 each includes a mode control signal terminal configured to receive a mode control signal EN. The first gating control module 120 and the second gating control module 220 are configured to respectively control the first gate driver 110 and the second gate driver 210 to drive in a first mode when the mode control signal EN indicates a first state; and respectively control the first gate driver 110 and the second gate driver 210 to drive in a second mode when the mode control signal EN indicates a second state. In the first mode, when odd frames of images are displayed, the odd lines of gate lines Gate(2n-1) are driven sequentially, and when even frames of images are displayed, the even lines of gate lines Gate(2n) are driven sequentially. Alternatively, when the odd frames of images are displayed, the even lines of gate lines Gate(2n) are driven sequentially, and when the even frames of images are displayed, the odd lines of gate lines Gate(2n-1) are driven sequentially. In the second mode, when various frames of images are displayed, respective lines of gate lines Gate(n) are driven progressively.

(10) It should be noted that in the above driving apparatus according to an embodiment of the present disclosure, the first state and the second state may indicate that the mode control signals are a high level signal and a low level signal respectively; or the first state and the second state may indicate that the mode control signals are a low level signal and a high level signal respectively. The present disclosure is not limited thereto.

(11) Preferably, as shown in FIG. 1, the first gating control module 120 further includes a first gating clock signal terminal configured to receive a first gating clock signal Sclk, and the second gating control module 220 further includes a second gating clock signal terminal configured to receive a second gating clock signal Sclkb. When the mode control signal EN is in the first state, the first gating control module 120 transmits a first trigger signal STV1 transmitted by the first trigger signal terminal to the first gate driver 110 to drive the odd lines of gate lines Gate(2n-1) sequentially when the first gating clock signal Sclk is a valid signal, and the second gating control module 220 transmits a second trigger signal STV2 transmitted by the second trigger signal STV2 terminal to the second gate driver 210 to drive the even lines of gate lines Gate(2n) sequentially when the second gating clock signal Sclkb is a valid signal. When the mode control signal EN is in the second state, the first gating control module 120 transmits the first trigger signal STV1 to the first gate driver 110 to drive the odd lines of gate lines Gate(2n-1) sequentially, and the second gating control module 220 transmits the second trigger signal STV2 to the second gate driver 210 to drive the even lines of gate lines Gate(2n) sequentially. The first gating clock signal Sclk and the second gating clock signal Sclkb have opposite phases and the same period which is a sum of display two frame cycles of images.

(12) The present disclosure will be described in detail below. It should be noted that the present embodiment is merely used to better explain the present disclosure instead of limiting the present disclosure.

(13) Preferably, as shown in FIG. 2a, in the driving apparatus according to an embodiment of the present disclosure, the first gating control module 120 may include a first NAND gate 121, a second NAND gate 122, a first NOT gate 123 and a second NOT gate 124. The first NOT gate 123 has an input terminal which is the first gating clock signal Sclk terminal of the first gating control module 120, and an output terminal connected to a first input terminal of the first NAND gate 121. The first NAND gate 121 has a second input terminal which is the mode control signal EN terminal of the first gating control module 120 and an output terminal connected to a first input terminal of the second NAND gate 122. The second NAND gate 122 has a second input terminal connected to the first trigger signal STV1 terminal and an output terminal connected to an input terminal of the second NOT gate 124. The second NOT gate 124 has an output terminal connected to the first gate driver 110.

(14) Specifically, in the above driving apparatus according to an embodiment of the present disclosure, in the case that a structure of the first gating control module 120 is the above structure illustrated in FIG. 2a, when the mode control signal EN is a high level signal, the mode control signal EN is in a first state, and when the mode control signal EN is a low level signal, the mode control signal EN is in a second state. At the same time, when the first gating clock signal Sclk is a high level signal, the first gating clock signal Sclk is a valid signal.

(15) Specifically, when the first gating control module 120 in the above driving apparatus according to an embodiment of the present disclosure uses a specific structure including a first NAND gate, a second NAND gate, a first NOT gate, and a second NOT gate, an operating principle thereof is as described below. When the mode control signal EN is a high level signal, an output terminal of the first NAND gate outputs a high level signal when the first gating clock signal Sclk is a high level signal, and at this time, the first trigger signal STV1 is transmitted to the first gate driver 110 to drive the odd lines of gate lines sequentially; and the output terminal of the first NAND gate outputs a low level signal when the first gating clock signal Sclk is a low level signal. At this time, the first trigger signal STV1 is not output. When the mode control signal EN is a low level signal, the first gating clock signal Sclk is shielded and cannot be output. Therefore, the output terminal of the first NAND gate outputs a high level signal no matter whether the first gating clock signal Sclk is a low level signal or a high level signal, and at this time, the first trigger signal STV1 is transmitted to the first gate driver 110 to drive the odd lines of gate lines sequentially.

(16) Alternatively, in the driving apparatus according to an embodiment of the present disclosure, as shown in FIG. 3a, the first gating control module 120 may include a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 and the second transistor T2 each has a gate which is the mode control signal EN terminal of the first gating control module 120 and a source connected to the first trigger signal STV1 terminal. The first transistor T1 has a drain connected to a source of the third transistor T3, and the second transistor T2 has a drain respectively connected to the first gate driver 110 and a drain of the third transistor T3. The third transistor T3 has a gate which is the first gating clock signal Sclk terminal of the first gating control module 120. The first transistor T1 is an N-type transistor, and the second transistor is a P-type transistor; or the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

(17) Specifically, in the above driving apparatus according to an embodiment of the present disclosure, when a structure of the first gating control module 120 is the above structure illustrated in FIG. 3a, in the case that the first transistor is a P-type transistor, when the mode control signal EN is a low level signal, the mode control signal EN is in a first state, and when the mode control signal EN is a high level signal, the mode control signal EN is in a second state. In contrary, in the case that the first transistor is an N-type transistor, when the mode control signal EN is a high level signal, the mode control signal EN is in a first state, and when the mode control signal EN is a low level signal, the mode control signal EN is in a second state. In the case that the third transistor is a P-type transistor, the first gating clock signal Sclk is a low level signal, the first gating clock signal Sclk is a valid signal. In contrary, when the third transistor is an N-type transistor, in the case that the first gating clock signal Sclk is a high level signal, the first gating clock signal Sclk is a valid signal.

(18) Specifically, when the first gating control module 120 in the driving apparatus according to an embodiment of the present disclosure uses the above specific structure including a first transistor, a second transistor and a third transistor, the operating principle thereof will be described below by taking N-type transistors as the first transistor and the third transistor and a P-type transistor as the second transistor. When the mode control signal EN is a high level signal, the second transistor is turned off, the first transistor is turned on, and only if the first gating clock signal Sclk is a high level signal, the third transistor is turned on, so as to transmit the first trigger signal STV1 to the first gate driver 110 to drive the odd lines of gate lines sequentially. When the first gating clock signal Sclk is a low level signal, the first trigger signal STV1 is not transmitted to the first gate driver 110. When the mode control signal EN is a low level signal, the first transistor is turned off, the second transistor is turned on, and no matter whether the third transistor is turned on, the first trigger signal terminal is connected to the first gate driver, so as to transmit the first trigger signal STV1 to the first gate driver to drive the odd lines of gate lines sequentially.

(19) The specific structure of the first gating control module in the driving apparatus is merely described above by way of example. In a specific implementation, the specific structure of the first gating control module is not limited to the above structure according to an embodiment of the present disclosure, and may be other structure known by those skilled in the art, which will not be limited here.

(20) Preferably, as shown in FIG. 2b, in the driving apparatus according to an embodiment of the present disclosure, the second gating control module 220 may include a third NAND gate 221, a fourth NAND gate 222, a third NOT gate 223 and a fourth NOT gate 224. The third NOT gate 223 has an input terminal which is the second gating clock signal terminal of the second gating control module 220, and an output terminal connected to a first input terminal of the third NAND gate 221. The third NAND gate 221 has a second input terminal which is the mode control signal terminal of the second gating control module 220, and an output terminal connected to a first input terminal of the fourth NAND gate 222. The fourth NAND gate 222 has a second input terminal connected to the second trigger signal terminal and an output terminal connected to an input terminal of the fourth NOT gate 224; and the fourth NOT gate 224 has an output terminal connected to the second gate driver 210.

(21) Specifically, in the above driving apparatus according to an embodiment of the present disclosure, in the case that a structure of the second gating control module is the above structure illustrated in FIG. 2b, when the mode control signal EN is a high level signal, the mode control signal EN is in a first state, and when the mode control signal EN is a low level signal, the mode control signal EN is in a second state. At the same time, when the first gating clock signal Sclk is a high level signal, the first gating clock signal Sclk is a valid signal.

(22) Specifically, when the second gating control module in the above driving apparatus according to an embodiment of the present disclosure uses a specific structure including a third NAND gate, a fourth NAND gate, a third NOT gate, and a fourth NOT gate, an operating principle thereof is as described below. When the mode control signal EN is a high level signal, an output terminal of the third NAND gate outputs a high level signal when the second gating clock signal Sclkb is a high level signal, and at this time, the second trigger signal STV2 is transmitted to the second gate driver to drive the even lines of gate lines sequentially. The output terminal of the third NAND gate outputs a low level signal when the second gating clock signal Sclkb is a low level signal, and at this time, the second trigger signal STV2 is shielded and cannot be output. When the mode control signal EN is a low level signal, the second gating clock signal Sclkb is shielded and cannot be output. Therefore, the output terminal of the third NAND gate outputs a high level signal no matter whether the second gating clock signal Sclkb is a low level signal or a high level signal, and at this time, the second trigger signal STV2 is transmitted to the second gate driver 210 to drive the even lines of gate lines sequentially.

(23) Alternatively, in the driving apparatus according to an embodiment of the present disclosure, as shown in FIG. 3b, the second gating control module 220 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The fourth transistor T4 and the fifth transistor T5 each has a gate which is the mode control signal terminal of the second gating control module 220 and a source connected to the second trigger signal terminal. The fourth transistor T4 has a drain connected to a source of the sixth transistor T6, and the fifth transistor T5 has a drain respectively connected to the second gate driver 210 and a drain of the sixth transistor T6. The sixth transistor T6 has a gate which is the second gating clock signal terminal of the second gating control module 220. The fourth transistor T4 is an N-type transistor, and the fifth transistor T5 is a P-type transistor; or the fourth transistor T4 is a P-type transistor, and the fifth transistor T5 is an N-type transistor.

(24) Specifically, in the above driving apparatus according to an embodiment of the present disclosure, when a structure of the second gating control module is the above structure illustrated in FIG. 3b, in the case that the fourth transistor is a P-type transistor, when the mode control signal EN is a low level signal, the mode control signal EN is in a first state, and when the mode control signal EN is a high level signal, the mode control signal EN is in a second state. In contrary, in the case that the fourth transistor is an N-type transistor, when the mode control signal EN is a high level signal, the mode control signal EN is in a first state, and when the mode control signal EN is a low level signal, the mode control signal EN is in a second state. In the case that the sixth transistor is a P-type transistor, when the second gating clock signal Sclkb is a low level signal, the second gating clock signal Sclkb is a valid signal. In contrary, in the case that the sixth transistor is an N-type transistor, when the second gating clock signal Sclkb is a high level signal, the second gating clock signal Sclkb is a valid signal.

(25) Specifically, when the second gating control module in the above driving apparatus according to an embodiment of the present disclosure uses the above specific structure including a fourth transistor, a fifth transistor and a sixth transistor, an operating principle thereof will be described below by taking N-type transistors as the fourth transistor and the fifth transistor and a P-type transistor as the sixth transistor. When the mode control signal EN is a high level signal, the fifth transistor is turned off, the fourth transistor is turned on, and only if the second gating clock signal Sclkb is a high level signal, the sixth transistor is turned on, and thus the second trigger signal terminal is connected to the second gate driver, so as to transmit the second trigger signal to the second gate driver to drive the even lines of gate lines sequentially. When the second gating clock signal Sclkb is a low level signal, the second trigger signal terminal is disconnected from the second gate driver. When the mode control signal EN is a low level signal, the fourth transistor is turned off, the fifth transistor is turned on, and no matter whether the sixth transistor is turned on, the second trigger signal terminal is connected to the second gate driver, so as to transmit the second trigger signal STV2 to the second gate driver to drive the even lines of gate lines sequentially.

(26) The specific structure of the second gating control module in the driving apparatus is merely described above by way of example. In a specific implementation, the specific structure of the second gating control module is not limited to the above structure according to an embodiment of the present disclosure, and may be other structure known by those skilled in the art, which will not be limited here.

(27) Preferably, when the first gating control module and the second gating control module use the structures illustrated in FIGS. 3a and 3b respectively, both the third transistor and the sixth transistor are N-type transistors or P-type transistors.

(28) In a specific implementation, the first gating control module and the second gating control module may be integrated in a driver IC of a display panel by a manufacturing process of the driver IC. Preferably, the first gating control module and the second gating control module may be formed on an array substrate of the display panel by an array process. Such integration process not only saves cost, but also achieves an aesthetic design of the display panel which is symmetric on both sides. At the same time, a bonding area and a wiring space for fan-out can further be omitted, thereby achieving a design of a narrow frame.

(29) An operation process of a driving apparatus according to an embodiment of the present disclosure will be described below in combination with the driving apparatuses illustrated in FIGS. 2a and 2b and FIGS. 3a and 3b by taking an input-output timing diagram illustrated in FIG. 4. In FIG. 4, EN represents a mode control signal, Sclk represents a first gating clock signal, Sclkb represents a second gating clock signal, STV1 represents a first trigger signal, STV2 represents a second trigger signal, and Gate(n) represents signals of a n.sup.th line of gate lines. In the following description, 1 represents a high level signal, and 0 represents a low level signal.

FIRST EXAMPLE

(30) The operation process of a driving apparatus will be described by taking the driving apparatus of the structure illustrated FIGS. 2a and 2b as an example. Specifically, three stages T1, T2, and T3 in the input-output timing diagram illustrated in FIG. 4 are selected.

(31) In stage T1, EN=0. In this stage, as EN=0, the first gating clock signal Sclk is shielded and cannot be output, and therefore, no matter whether Sclk=0 or Sclk=1, as long as a first trigger signal STV1 is output, the first trigger signal STV1 will be transmitted to the first gate driver to drive odd lines of gate lines sequentially. In this stage, as EN=0, the second gating clock signal Sclkb is shielded and cannot be output. Therefore, no matter whether Sclkb=0 or Sclkb=1, as long as a second trigger signal STV2 is output, the second trigger signal STV2 will be transmitted to the second gate driver to drive even lines of gate lines sequentially. Within display a frame cycle of images, the first gate driver cooperates with the second gate driver to enable driving various lines of gate lines progressively.

(32) In stage T2, EN=1, Sclk=1 and Sclkb=0. In this stage, as EN=1 and Sclk=1, when the output terminal of the first NAND gate outputs 1, as long as a first trigger signal STV1 is output, the first trigger signal STV1 will be transmitted to the first gate driver to drive odd lines of gate lines sequentially. In this stage, as EN=1 and Sclkb=0, the output terminal of the third NAND gate outputs 0, and at this time, the second trigger signal STV2 is shielded and cannot be output. Therefore, within display of a frame cycle of images, only the first gate driver drives odd lines of gate lines sequentially.

(33) In stage T3, EN=1, Sclk=0 and Sclkb=1. In this stage, as EN=1 and Sclkb=1, when the output terminal of the third NAND gate outputs 1, as long as a second trigger signal STV2 is output, the second trigger signal STV2 will be transmitted to the second gate driver to drive even lines of gate lines sequentially. In this stage, as EN=1 and Sclk=0, the output terminal of the first NAND gate outputs 0, and at this time, the first trigger signal STV1 is shielded and cannot be output. Therefore, within display time of a frame cycle, only the second gate driver drives even lines of gate lines sequentially.

(34) In stage T1, when various frames of images are displayed, respective lines of gate lines are driven progressively, and therefore the display panel is enabled to have better quality of display images. In stages T2 and T3, due to a reduced number of gate lines to be driven when various frames of images are displayed, the power consumption can be reduced. In addition, due to the effect of persistence of vision of human eyes, better quality of display images can be ensured while reducing power consumption. Therefore, by switching the driving apparatus between the first mode and second mode, a number of gate lines to be driven can be reduced to reduce power consumption.

SECOND EXAMPLE

(35) The operation process of a driving apparatus will be described by taking the driving apparatus of the structure illustrated FIGS. 3a and 3b as an example. The description is made by taking N-type transistors as the first transistor, the third transistor, the fourth transistor, and the sixth transistor and P-type transistors as the second transistor and the fifth transistor as an example. Specifically, three stages T1, T2, and T3 in the input-output timing diagram illustrated in FIG. 4 are selected.

(36) In stage T1, EN=0. In this stage, as EN=0, the first transistor is turned off, the second transistor is turned on, no matter whether the third transistor is turned on (i.e., no matter whether Sclk=0 or Sclk=1), both the first trigger signal terminal and the first gate driver are turned on, and therefore, as long as a first trigger signal STV1 is output, the first trigger signal STV1 will be transmitted to the first gate driver to drive odd lines of gate lines sequentially. In this stage, as EN=0, the fourth transistor is turned off, the fifth transistor is turned on, no matter whether the sixth transistor is turned on (i.e., no matter whether Sclkb=0 or Sclkb=1), both the second trigger signal terminal and the second gate driver are turned on. As long as a second trigger signal STV2 is output, the second trigger signal STV2 will be transmitted to the second gate driver to drive even lines of gate lines sequentially. Within display time of a frame cycle, the first gate driver cooperates with the second gate driver to enable driving various lines of gate lines progressively.

(37) In stage T2, EN=1, Sclk=1 and Sclkb=0. In this stage, as EN=1 and Sclk=1, the second transistor is turned off, the first transistor and the third transistor are turned on, the first trigger signal terminal is connected to the first gate driver. As long as a first trigger signal STV1 is output, the first trigger signal STV1 will be transmitted to the first gate driver to drive odd lines of gate lines sequentially. In this stage, as EN=1 and Sclkb=0, the fourth transistor is turned on, the fifth transistor and the sixth transistor are turned off, and at this time, the second trigger signal STV2 terminal and the second gate driver are in a turn-off state. Therefore, within display time of a frame cycle, only the first gate driver drives odd lines of gate lines sequentially.

(38) In stage T3, EN=1, Sclk=0 and Sclkb=1. In this stage, as EN=1 and Sclkb=1, the fifth transistor is turned off, the fourth transistor and the sixth transistor are turned on, the second trigger signal terminal is connected to the second gate driver. As long as a second trigger signal STV2 is output, the second trigger signal STV2 will be transmitted to the second gate driver to drive even lines of gate lines sequentially. In this stage, as EN=1 and Sclk=0, the first transistor is turned on, the second transistor and the third transistor are turned off, and at this time, the first trigger signal STV1 terminal is disconnected from the first gate driver. Therefore, within display time of a frame cycle, only the second gate driver drives even lines of gate lines sequentially.

(39) In addition, the first gate driver and the second gate driver each is a conventional gate driver and a specific structure thereof will be omitted here.

(40) Embodiments of the present disclosure further provide a display apparatus, including any of the above driving apparatuses according to an embodiment of the present disclosure. The display apparatus may include any product or part with a display function such as a mobile phone, a tablet, a television, a display, a notebook, a digital photo frame, a navigator etc. Specifically, the display apparatus may be implemented with reference to the above embodiments of the driving apparatus. Repeated parts will be omitted here.

(41) The embodiments of the present disclosure further provide a gate driving method of a display panel, the display panel comprising multiple gate lines, a first gate driver connected to a first trigger signal terminal and configured to drive odd lines of gate lines on the display panel, a second gate driver connected to a second trigger signal terminal and configured to drive even lines of gate lines on the display panel, and a mode control signal terminal configured to transmit a mode control signal, the driving method comprising:

(42) controlling a driving manner of the first gate driver and the second gate driver to be a first mode when the mode control signal is in a first state, and controlling the driving manner of the first gate driver and the second gate driver to switch from the current first mode to a second mode when the mode control signal changes to being in a second state from being in the first state; and

(43) controlling the driving manner of the first gate driver and the second gate driver to be the second mode when the mode control signal is in the second state, and controlling the driving manner of the first gate driver and the second gate driver to switch from the current second mode to the first mode when the mode control signal changes to being in the first state from being in the second state; wherein,

(44) in the first mode, when odd frames of images are displayed, the odd lines of gate lines are driven sequentially, and when even frames of images are displayed, the even lines of gate lines are driven sequentially; or, when the odd frames of images are displayed, the even lines of gate lines are driven sequentially, and when the even frames of images are displayed, the odd lines of gate lines are driven sequentially; and

(45) in the second mode, when various frames of images are displayed, respective lines of gate lines are driven progressively.

(46) It should be noted that in the embodiments of the present disclosure, even lines of gate lines and odd lines of gate lines on the display panel are scanned respectively as two independent units in different time, so as to reduce a number of gate lines to be driven during display. Other solutions should belong to the protection scope of the present disclosure If these solutions use the same technical principle as the present solution, i.e., the substantive innovation or improvement is achieved by merely changing to a different combination of units of gate lines from that in the present solution, for example, upper gate lines on the display panel which are used as one independent unit and lower gate lines on the display panel which are used as the other independent unit, are scanned in different time, or even more independent units of gate lines are combined to be scanned in different time.

(47) Obviously, various modifications and variants can be made to the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, these modifications and variants are to be encompassed by the present disclosure if they fall within the scope of the present disclosure as defined by the claims and their equivalents.