DISTRIBUTED POWER MANAGEMENT CIRCUIT

Abstract

A distributed power management circuit is provided. In embodiments disclosed herein, the distributed power management circuit can achieve multiple performance enhancing objectives simultaneously. More specifically, the distributed power management circuit can be configured to switch a modulated voltage from one voltage level to another within a very short switching window, reduce in-rush current required for switching the modulated voltage, and minimize a ripple in the modulated voltage, all at same time. As a result, the distributed power management circuit can be provided in a wireless device (e.g., smartphone) to enable very fast voltage switching across a wide modulation bandwidth (e.g., 400 MHz) with reduced power consumption and voltage distortion.

Claims

1. A distributed power management circuit comprising: a distributed voltage modulation circuit comprising: a voltage output that outputs a modulated voltage; a voltage amplifier configured to generate a modulated initial voltage; a voltage offset circuit coupled between the voltage amplifier and the voltage output and configured to raise the modulated initial voltage by a modulated offset voltage to thereby generate the modulated voltage; and a control circuit configured to: receive a modulated target voltage indicating that the modulated voltage will change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval; and activate the voltage amplifier prior to a start of the upcoming time interval to thereby change the modulated initial voltage to the future voltage level within a defined temporal limit from the start of the upcoming time interval.

2. The distributed power management circuit of claim 1, wherein: the present time interval corresponds to a preceding one of a pair of consecutive orthogonal frequency division multiplexing (OFDM) symbols; the upcoming time interval corresponds to a succeeding one of the pair of consecutive OFDM symbols; and the defined temporal limit corresponds to a cyclic prefix (CP) in each of the pair of consecutive OFDM symbols.

3. The distributed power management circuit of claim 1, further comprising: a power management integrated circuit (PMIC) coupled to the voltage output via a first conductive trace having a first inductive trace impedance; and one or more power amplifier circuits each comprising a respective voltage input coupled to the voltage output via a second conductive trace having a second inductive trace impedance substantially smaller than the first inductive trace impedance.

4. The distributed power management circuit of claim 3, wherein the PMIC and the distributed voltage modulation circuits are provided in different dies.

5. The distributed power management circuit of claim 3, wherein the PMIC comprises: a multi-level charge pump (MCP) configured to generate a low-frequency voltage as a function of a battery voltage and based on a duty cycle determined according to the modulated target voltage; and a power inductor coupled to the voltage output via the first conductive trace and configured to induce a low-frequency current based on the low-frequency voltage.

6. The distributed power management circuit of claim 5, wherein the voltage offset circuit comprises: an offset capacitor coupled between an output of the voltage amplifier and the voltage output; and a bypass switch coupled between the output of the voltage amplifier and a ground.

7. The distributed power management circuit of claim 6, wherein the control circuit is further configured to: receive the modulated target voltage indicating that the modulated voltage will increase from the present voltage level to the future voltage level; activate the voltage amplifier prior to the start of the upcoming time interval to thereby raise the modulated voltage from the present voltage level to the future voltage level within the defined temporal limit; open the bypass switch after activating the voltage amplifier to thereby charge the offset capacitor from the present voltage level to the future voltage level based on the low-frequency current; close the bypass switch in response to the offset capacitor being charged up to the future voltage level; and deactivate the voltage amplifier after closing the bypass switch.

8. The distributed power management circuit of claim 6, wherein the control circuit is further configured to: receive the modulated target voltage indicating that the modulated voltage will decrease from the present voltage level to the future voltage level; activate the voltage amplifier prior to the start of the upcoming time interval to thereby maintain the modulated voltage at the present voltage level; close the bypass switch in response to the offset capacitor being discharged to the future voltage level; and deactivate the voltage amplifier after closing the bypass switch.

9. The distributed power management circuit of claim 3, wherein the voltage amplifier comprises: an input/bias stage configured to: receive the modulated target voltage and a feedback signal indicating the modulated voltage at the voltage output; and generate a pair of bias signals based on the modulated target voltage and the modulated voltage indicated in the feedback signal; and an output stage coupled to the input/bias stage and configured to generate the modulated initial voltage based on the pair of bias signals.

10. The distributed power management circuit of claim 9, wherein the output stage comprises: a first transistor comprising: a first drain electrode configured to receive a supply voltage; a first gate electrode configured to receive a first bias signal among the pair of bias signals; and a first source electrode coupled to an output of the voltage amplifier; and a second transistor comprising: a second source electrode coupled to the output of the voltage amplifier; a second gate electrode configured to receive a second bias signal among the pair of bias signals; and a second drain electrode coupled to a ground; wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the modulated initial voltage at the output of the voltage amplifier.

11. The distributed power management circuit of claim 10, wherein the output stage further comprises: a first Miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output to thereby reduce an inductive impedance of the distributed voltage modulation circuit when the first transistor is biased by the first bias signal; and a second Miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output to thereby reduce the inductive impedance of the distributed voltage modulation circuit when the second transistor is biased by the second bias signal.

12. A distributed voltage modulation circuit comprising: a voltage output that outputs a modulated voltage; a voltage amplifier configured to generate a modulated initial voltage; a voltage offset circuit coupled between the voltage amplifier and the voltage output and configured to raise the modulated initial voltage by a modulated offset voltage to thereby generate the modulated voltage; and a control circuit configured to: receive a modulated target voltage indicating that the modulated voltage will change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval; and activate the voltage amplifier prior to a start of the upcoming time interval to thereby change the modulated initial voltage to the future voltage level within a defined temporal limit from the start of the upcoming time interval.

13. The distributed voltage modulation circuit of claim 12, wherein the voltage offset circuit comprises: an offset capacitor coupled between an output of the voltage amplifier and the voltage output; and a bypass switch coupled between the output of the voltage amplifier and a ground.

14 . The distributed voltage modulation circuit of claim 12, wherein the voltage amplifier comprises: an input/bias stage configured to: receive the modulated target voltage and a feedback signal indicating the modulated voltage at the voltage output; and generate a pair of bias signals based on the modulated target voltage and the modulated voltage indicated in the feedback signal; and an output stage coupled to the input/bias stage and configured to generate the modulated initial voltage based on the pair of bias signals.

15. The distributed voltage modulation circuit of claim 14 , wherein the output stage comprises: a first transistor comprising: a first drain electrode configured to receive a supply voltage; a first gate electrode configured to receive a first bias signal among the pair of bias signals; and a first source electrode coupled to an output of the voltage amplifier; and a second transistor comprising: a second source electrode coupled to the output of the voltage amplifier; a second gate electrode configured to receive a second bias signal among the pair of bias signals; and a second drain electrode coupled to a ground; wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the modulated initial voltage at the output of the voltage amplifier.

16. The distributed voltage modulation circuit of claim 15, wherein the output stage further comprises: a first Miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output to thereby reduce an inductive impedance of the distributed voltage modulation circuit when the first transistor is biased by the first bias signal; and a second Miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output to thereby reduce the inductive impedance of the distributed voltage modulation circuit when the second transistor is biased by the second bias signal.

17. A method of supporting distributed power management comprising: coupling a distributed voltage modulation circuit to a power management integrated circuit (PMIC) via a first conductive trace having a first inductive trace impedance; coupling the distributed voltage modulation circuit to a respective voltage input of one or more power amplifier circuits via a second conductive trace having a second inductive trace impedance substantially smaller than the first inductive trace impedance; receiving, in the distributed voltage modulation circuit, a modulated target voltage indicating that a modulated voltage will change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval; and changing, in the distributed voltage modulation circuit, a modulated initial voltage prior to a start of the upcoming time interval such that the modulated initial voltage can be changed to the future voltage level within a defined temporal limit from the start of the upcoming time interval.

18. The method of claim 17, wherein the distributed voltage modulation circuit comprises: a voltage output that outputs the modulated voltage; a voltage amplifier configured to generate the modulated initial voltage; and a voltage offset circuit comprising: an offset capacitor coupled between an output of the voltage amplifier and the voltage output and configured to raise the modulated initial voltage by a modulated offset voltage to thereby generate the modulated voltage; and a bypass switch coupled between the output of the voltage amplifier and a ground.

19. The method of claim 18, further comprising: receiving the modulated target voltage indicating that the modulated voltage will increase from the present voltage level to the future voltage level; activating the voltage amplifier prior to the start of the upcoming time interval to thereby raise the modulated voltage from the present voltage level to the future voltage level within the defined temporal limit; opening the bypass switch after activating the voltage amplifier to thereby charge the offset capacitor from the present voltage level to the future voltage level; closing the bypass switch in response to the offset capacitor being charged up to the future voltage level; and deactivating the voltage amplifier after closing the bypass switch.

20. The method of claim 18, further comprising: receiving the modulated target voltage indicating that the modulated voltage will decrease from the present voltage level to the future voltage level; activating the voltage amplifier prior to the start of the upcoming time interval to thereby maintain the modulated voltage at the present voltage level; closing the bypass switch in response to the offset capacitor being discharged to the future voltage level; and deactivating the voltage amplifier after closing the bypass switch.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] FIG. 1A illustrates an exemplary time slot(s) and a mini time slot(s) as widely supported in a fifth generation (5G) system;

[0015] FIG. 1B is a schematic diagram of an exemplary existing transmission circuit wherein a power management circuit is configured to reduce a voltage ripple in a modulated voltage based on a conventional approach;

[0016] FIG. 1C is a schematic diagram of an exemplary electrical model of the power management circuit in FIG. 1B;

[0017] FIG. 1D is a graphic diagram providing an exemplary illustration of magnitude impedance as a function of modulation frequency;

[0018] FIG. 2 is a schematic diagram of an exemplary distributed power management circuit configured according to embodiments of the present disclosure;

[0019] FIG. 3A is a timing diagram providing an exemplary illustration of the distributed power management circuit of FIG. 2 configured to increase a modulated voltage from a present voltage level in a present orthogonal frequency division multiplexing (OFDM) symbol to a future voltage level in an upcoming OFDM symbol; and

[0020] FIG. 3B is a timing diagram providing an exemplary illustration of the distributed power management circuit of FIG. 2 configured to decrease an Average Power Tracking (APT) voltage from a present voltage level in a present OFDM symbol to a future voltage level in an upcoming OFDM symbol;

[0021] FIG. 4 is a schematic diagram providing an exemplary illustration of a voltage amplifier in the distributed power management circuit of FIG. 2; and

[0022] FIG. 5 is a flowchart of an exemplary process for supporting distributed power management based on the distributed power management circuit of FIG. 2.

DETAILED DESCRIPTION

[0023] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0024] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0025] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0026] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0029] Embodiments of the disclosure relate to a distributed power management circuit. In embodiments disclosed herein, the distributed power management circuit can achieve multiple performance enhancing objectives simultaneously. More specifically, the distributed power management circuit can be configured to switch a modulated voltage from one voltage level to another within a very short switching window, reduce in-rush current required for switching the modulated voltage, and minimize a ripple in the modulated voltage, all at same time. As a result, the distributed power management circuit can be provided in a wireless device (e.g., smartphone) to enable very fast voltage switching across a wide modulation bandwidth (e.g., 400 MHz) with reduced power consumption and voltage distortion.

[0030] Before discussing the distributed power management circuit of the present disclosure, starting at FIG. 2, a brief discussion is first provided with reference to FIGS. 1A-1D to help understand several technical problems to be concurrently solved by the distributed power management circuit of the present disclosure.

[0031] FIG. 1A illustrates an exemplary time slot 10 and a pair of mini time slots 12(1)-12(2) as widely supported in a fifth generation (5G) and/or a 5G new-radio (5G-NR) system. The time slot(s) 10 is configured to include multiple symbols 14 (1)-14 (14), such as orthogonal frequency division multiplexing (OFDM) symbols. The mini time slots 12(1)-12(2) can each include at least two of the symbols 14 (1)-14(14). In the example shown in FIG. 1A, the mini time slots 12(1)-12(2) each includes four of the symbols 14 (1)-14(14).

[0032] As previously shown in Table 1, each of the symbols 14(1)-14(14) has a symbol duration that depends on the subcarrier spacing (SCS) and starts with a cyclic prefix (CP) whose duration also depends on the SCS. In this regard, once the SCS is chosen, the symbol duration of the symbols 14(1)-14(14) and the duration of the CP in each of the symbols 14(1)-14(14) will be determined accordingly. Hereinafter, the symbol duration of the symbols 14(1)-14(14) and the CP duration of each of the symbols 14(1)-14(14) can be used to define “a time interval (e.g., a present or an upcoming time interval)” and “a defined temporal limit from a start of the time interval,” respectively.

[0033] Understandably, the CP in each of the symbols 14(1)-14(14) is designed to act as a buffer zone for any changes (e.g., voltage change) between any two consecutive ones of the symbols 14(1)-14(14). As such, one of the technical problems to be solved by the distributed power management circuit of the present disclosure is to ensure that a modulated voltage change (increase or decrease) between any two consecutive ones of the symbols 14(1)-14(14) can be made within the CP duration in each of the symbols 14(1)-14(14).

[0034] FIG. 1B is a schematic diagram of an exemplary existing transmission circuit 16 wherein a power management circuit 18 is configured to reduce a voltage ripple V.sub.CC-RP in a modulated voltage V.sub.CC based on a conventional approach. The power management circuit 18 includes a power management integrated circuit (PMIC) 20 and a power amplifier circuit 22. The PMIC 20 is configured to generate the modulated voltage V.sub.CC based on a modulated target voltage V.sub.TGT and provide the modulated voltage V.sub.CC to the power amplifier circuit 22 via a conductive path 24 (e.g., a conductive trace), which is coupled between a voltage output 26 of the PMIC 20 and a power amplifier input 28 of the power amplifier circuit 22. The power amplifier circuit 22 is configured to amplify a radio frequency (RF) signal 30 based on the modulated voltage V.sub.CC.

[0035] Notably, there may be an internal routing distance from the power amplifier input 28 to an actual voltage input 32 (e.g., a collector node) of the power amplifier circuit 22. Given that the internal routing distance is far shorter than the conductive path 24, the internal routing distance is thus neglected hereinafter. Accordingly, the power amplifier input 28 as illustrated herein can be equated with the actual voltage input 32 of the power amplifier circuit 22.

[0036] The power management circuit 18 may be coupled to a transceiver circuit 34. Herein, the transceiver circuit 34 is configured to generate the RF signal 30 and the modulated target voltage VTGT.

[0037] The voltage ripple V.sub.CC-RP can be quantitively analyzed based on an equivalent electrical model of the power management circuit 18. In this regard,

[0038] FIG. 1C is a schematic diagram of an exemplary equivalent electrical model 36 of the power management circuit 18 in FIG. 1A. Common elements between FIGS. 1B and 1C are shown therein with common element numbers and will not be re-described herein.

[0039] The PMIC 20 inherently has an inductive impedance Z.sub.PMIC that can be modeled by a PMIC inductance L.sub.PMIC. The conductive path 24 can also be associated with an inductive trace impedance Z.sub.TRACE that can be modeled by a trace inductance L.sub.TRACE. As a result, looking from the power amplifier input 28 toward the PMIC 20, the power amplifier circuit 22 will see an output impedance Z.sub.OUT that includes both the inductive impedance Z.sub.PMIC and the inductive trace impedance Z.sub.TRACE (Z.sub.OUT=Z.sub.PMIC+Z.sub.TRACE).

[0040] The power amplifier circuit 22 can be modeled as a current source. In this regard, the power amplifier circuit 22 will modulate a load current I.sub.LOAD based on the modulated voltage V.sub.CC. The load current I.sub.LOAD can interact with the output impedance Z.sub.OUT to create the voltage ripple V.sub.CC-RP in the modulated voltage V.sub.CC received at the power amplifier input 28. In this regard, the voltage ripple V.sub.CC-RP is a function of the modulated load current I.sub.LOAD and the output impedance Z.sub.OUT, as expressed in equation (Eq. 1) below.

V.sub.CC-RP =I.sub.LOAD*Z.sub.OUT   (Eq. 1)

[0041] Notably from the equation (Eq. 1), it may be possible to reduce the voltage ripple V.sub.CC-RP by lowering the output impedance Z.sub.OUT seen at the power amplifier input 28. In this regard, the conventional approach for reducing the voltage ripple V.sub.CC-RP in the power management circuit 18 of FIG. 1B is to add a decoupling capacitor C.sub.PA inside the power amplifier circuit 22 and be as close to the power amplifier input 28 as possible. By adding the decoupling capacitor C.sub.PA, the output impedance Z.sub.OUT can be simply expressed as in equation (Eq. 2).

Z.sub.OUT=Z.sub.CPA∥(Z.sub.PMIC+Z.sub.TRACE)   (Eq. 2)

[0042] In the equation (Eq. 2), ZC.sub.PA represents a capacitive impedance of the decoupling capacitor C.sub.PA. The capacitive impedance Z.sub.CPA and the inductive impedance Z.sub.PMIC and Z.sub.TRACE can each be determined according to equations (Eq. 3.1-3.3) below.

|Z.sub.CPA|=1/2πf*C.sub.PA   (Eq. 3.1)

|Z.sub.PMIC|=2πf*L.sub.PMIC   (Q. 3.2)

|Z.sub.TRACE|=2πf*L.sub.TRACE   (Eq. 3.3)

[0043] In the equations (Eq. 3.1-3.3), f represents the modulation frequency of the load current I.sub.LOAD. In this regard, the capacitive impedance Z.sub.CPA, the inductive impedance Z.sub.PMIC, and the inductive trace impedance Z.sub.TRACE are each a function of the modulation frequency f. FIG. 1D is a graphic diagram providing an exemplary illustration of magnitude impedance vs. the modulation frequency f.

[0044] When the modulation frequency f is lower than 10 MHz, the output impedance Z.sub.OUT is dominated by a real part of the inductive impedance Z.sub.PMIC and a real part of the inductive trace impedance Z.sub.TRACE. Between 10 MHz and 100 MHz, the output impedance Z.sub.OUT is dominated by the inductive impedance Z.sub.PMIC and the inductive trace impedance Z.sub.TRACE . Above 1000 MHz, the output impedance Z.sub.OUT will be dominated by the capacitive impedance Z.sub.CPA.

[0045] Herein, a modulation bandwidth BW.sub.MOD of the RF signal 30 may fall between 100 MHz and 1000 MHz (e.g., 100-500 MHz). In this frequency range, the output impedance Z.sub.OUT will be determined by the output impedance Z.sub.OUT as expressed in equation (Eq. 2).

[0046] Notably from equations (Eq. 2 and 3.1), the capacitive impedance Z.sub.CPA, and therefore the output impedance Z.sub.OUT, will decrease as the capacitance C.sub.PA increases. In this regard, the conventional approach for reducing the ripple voltage V.sub.CC-RP relies largely on adding the decoupling capacitor C.sub.PA with a larger capacitance (e.g., 1 to 2 μF). However, doing so can cause some obvious issues.

[0047] Understandably, a rate of change of the modulated voltage V.sub.CC (ΔV.sub.CC or dV/dt) can be inversely affected by the capacitance of the decoupling capacitor C.sub.PA, as shown in equation (Eq. 4) below.

ΔV.sub.CC=I.sub.DC/C.sub.PA   (Eq. 4)

[0048] In the equation (Eq. 4), IDC represents a low-frequency current (a.k.a. in-rush current) provided by the PMIC 20 when the decoupling capacitor C.sub.PA is charged or discharged. In this regard, the larger capacitance the decoupling capacitor C.sub.PA has, the larger amount of the low-frequency current IDC would be needed to change the modulated voltage V.sub.CC at a required rate of change (ΔV.sub.CC). As a result, the existing transmission circuit 16 may cause a negative impact on battery life.

[0049] If the low-frequency current IDC is kept at a low level to prolong battery life, the existing transmission circuit 16 may have difficulty meeting the required rate of change (ΔV.sub.CC), particularly when the RF signal 30 is modulated based on OFDM for transmission in a millimeter wave (mmWave) spectrum.

Consequently, the existing transmission circuit 16 may not be able to change the modulated voltage V.sub.CC between any two consecutive ones of the symbols 14 (1)-14(14) that can be made within the CP duration in each of the symbols 14(1)-14(14).

[0050] On the other hand, if the capacitance of the decoupling capacitor CPA is reduced to help improve the rate of change (ΔVcc) of the modulated voltage V.sub.CC and reduce the in-rush current I.sub.DC, then the output impedance Z.sub.OUT may become too large to cause the voltage ripple V.sub.CC-RP. In this regard, another one of the technical problems to be solved by the distributed power management circuit of the present disclosure is to reduce the in-rush current without causing the voltage ripple V.sub.CC-RP.

[0051] In this regard, FIG. 2 is a schematic diagram of an exemplary distributed power management circuit 38 configured according to embodiments of the present disclosure. Herein, the distributed power management circuit 38 includes a PMIC 40, a distributed voltage modulation circuit 42, and one or more power amplifier circuits 44(1)-44(N). In an embodiment, the PMIC 40 and the distributed voltage modulation circuit 42 are provided in different dies. The power amplifier circuits 44(1)-44(N), on the other hand, can be provided in a same die or in multiple different dies.

[0052] The distributed voltage modulation circuit 42 is configured to generate a modulated voltage V.sub.CC at a voltage output 46 based on a modulated target voltage V.sub.TGT, which may be received from a transceiver circuit (not shown) via an RF front-end (RFFE) interface. The PMIC 40 is configured to generate a low-frequency current (a.k.a. in-rush current) IDC to assist in switching the modulated voltage V.sub.CC from one voltage level to another. The power amplifier circuits 44(1)-44(N) are each configured to amplify one or more RF signals 47 based on the modulated voltage V.sub.CC. Similar to the power amplifier circuit 22 in FIG. 1B, the power amplifier circuits 44(1)-44(N) can each see a ripple voltage V.sub.CC-RP at a respective voltage input 48 due to an output impedance Z.sub.OUT presenting at the respective voltage input 48.

[0053] As discussed in detail below, the distributed power management circuit 38 can switch a modulated voltage V.sub.CC from one voltage level to another between any pair of consecutive time intervals (e.g., OFDM symbols) S.sub.N−1, S.sub.N. The distributed power management circuit 38 can also reduce the in-rush current I.sub.DC required for switching the modulated voltage V.sub.CC between the consecutive time intervals S.sub.N−1, S.sub.N. The distributed power management circuit 38 can also suppress the ripple voltage V.sub.CC-RP by reducing the output impedance Z.sub.OUT seen by the power amplifier circuits 44(1)-44(N). More importantly, the distributed power management circuit 38 can perform fast switching of the modulated voltage V.sub.CC, reduce the in-rush current I.sub.DC, and suppress the ripple voltage V.sub.CC-RP all at a same time. In this regard, the distributed power management circuit 38 can solve all the technical problems as previously identified in the power management circuit 18 of FIG. 1B.

[0054] The PMIC 40 includes a multi-level charge pump (MCP) 50 configured to generate a low-frequency voltage V.sub.DC as a function of a battery voltage V.sub.BAT. For example, the MCP 50 can be a buck-boost direct-current (DC) to DC (DC-DC) converter that toggles between a buck mode and a boost mode based on a duty cycle. When operating in the buck mode, the MCP 50 can generate the low-frequency voltage V.sub.DC at 0×V.sub.BAT or 1×V.sub.BAT. When operating in the boost mode, the MCP 50 can generate the low-frequency voltage V.sub.DC at 2×V.sub.BAT. Thus, by toggling between 0×V.sub.BAT, 1×V.sub.BAT, and 2×V.sub.BAT based on the duty cycle, the MCP 50 can generate the low-frequency voltage V.sub.DC at any desired voltage level. In a non-limiting example, the duty cycle can be determined based on the modulated target voltage V.sub.TGT that indicates how the modulated voltage V.sub.CC will change (increase or decrease) from the preceding time interval S.sub.N−1 to the succeeding time interval S.sub.N.

[0055] The PMIC 40 also includes a power inductor 52. Herein, the power inductor 52 is configured to generate the low-frequency current (a.k.a. in-rush current) I.sub.DC to assist in switching the modulated voltage V.sub.CC from a present voltage level in the time interval S.sub.N−1 to a future voltage level in the time interval S.sub.N.

[0056] The distributed voltage modulation circuit 42 includes a voltage amplifier 54 and a voltage offset circuit 56. As such, the distributed voltage modulation circuit 42 can have an inherent impedance Z.sub.DPMIC, which is equivalent to the impedance Z.sub.PMIC in FIG. 1B. The voltage amplifier 54 is configured to generate a modulated initial voltage V.sub.AMP based on the modulated voltage V.sub.TGT and a supply voltage V.sub.SUP. The voltage offset circuit 56 is coupled between an output 58 of the voltage amplifier 54 and the voltage output 46. In an embodiment, the voltage offset circuit 56 includes an offset capacitor C.sub.OFF that is coupled between the output 58 of the voltage amplifier 54 and the voltage output 46, and a bypass switch SBYP coupled between the output 58 of the voltage amplifier 54 and a ground (GND).

[0057] The offset capacitor C.sub.OFF is configured to raise the modulated initial voltage V.sub.AMP by an offset voltage V.sub.OFF to generate the modulated voltage V.sub.CC at the voltage output 46 (V.sub.CC=V.sub.AMP+V.sub.OFF). The offset voltage V.sub.OFF can be modulated by charging or discharging the offset capacitor C.sub.OFF in accordance with an increase or decrease of the modulated voltage V.sub.CC. In a non-limiting example, the offset voltage V.sub.OFF can be modulated in accordance with equation (Eq. 5) below.

V.sub.OFF=V.sub.CC−MINN.sub.HEAD   (Eq. 5)

[0058] In the equation (Eq. 5) above, V.sub.CC−MIN represents a minimum level of the modulated voltage V.sub.CC in any of the time intervals, such as time intervals S.sub.N−2, S.sub.N−1, S.sub.N, and S.sub.N+1 illustrated herein. N.sub.HEAD represents a bottom headroom voltage. Given that N.sub.HEAD is typically fixed, the offset voltage V.sub.OFF will fluctuate in accordance with the V.sub.CC−MIN. As such, the offset capacitor C.sub.OFF needs to be charged when the V.sub.CC−MIN increases and discharged when the V.sub.CC−MIN decreases. According to an embodiment, the bypass switch S.sub.BYP is closed to allow the offset capacitor C.sub.OFF to be charged and opened to allow the offset capacitor C.sub.OFF to be discharged.

[0059] The distributed voltage modulation circuit 42 also includes a control circuit 60, which can be a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a bang-bang controller, as an example. As discussed in the examples in FIGS. 3A and 3B, the control circuit 60 can selectively activate/deactivate the voltage amplifier 54 and open/close the bypass switch S.sub.BYP to cause the modulated voltage V.sub.CC to change (increase or decrease) between the consecutive time intervals S.sub.N−1, S.sub.N. In a non-limiting example, the control circuit 60 can control the voltage amplifier 54 and the bypass switch S.sub.BYP via a control signal 62.

[0060] FIG. 3A is a timing diagram providing an exemplary illustration of the distributed power management circuit 38 of FIG. 2 configured to increase the modulated voltage V.sub.CC from a present voltage level VL.sub.P in an OFDM symbol S.sub.N−1 (also referred to as “a present OFDM symbol” or “present time interval”) to a future voltage level VL.sub.F in an OFDM symbol S.sub.N (also referred to as “an upcoming OFDM symbol” or “upcoming time interval”). Common elements between FIGS. 2 and 3A are shown therein with common element numbers and will not be re-described herein.

[0061] Herein, the control circuit 60 receives the target voltage V.sub.TGT during the OFDM symbol S.sub.N−1 and prior to a start time T.sub.1 of the OFDM symbol S.sub.N. The target voltage V.sub.TGT indicates that the modulated voltage V.sub.CC is set to increase from the present voltage level VL.sub.P (e.g., 1 V) in the OFDM symbol S.sub.N−1 to the future voltage level VL.sub.F (e.g., 5.5 V) in the OFDM symbol S.sub.N. Notably, during the OFDM symbol S.sub.N−1, the bypass switch S.sub.BYP is closed and the offset capacitor C.sub.OFF is charged to maintain the modulated voltage V.sub.CC at the present voltage level VL.sub.P.

[0062] Prior to the start time T.sub.1 of the OFDM symbol S.sub.N (e.g., at time T.sub.2), the control circuit 60 activates the voltage amplifier 54 to generate the modulated initial voltage V.sub.AMP and source a high-frequency current I.sub.Amp (e.g., an alternating current). In a non-limiting example, the time T.sub.2 can be so determined to account for ramping up and settling time of the voltage amplifier 54. In addition, the time T.sub.2 can be further determined to ensure that the voltage amplifier 54 can ramp up the modulated initial voltage V.sub.AMP to a level substantially equal (VL.sub.F−V.sub.OFF) within the CP duration of the OFDM symbol S.sub.N.

[0063] Concurrent to generating the modulated initial voltage V.sub.AMP to quickly raise the modulated voltage V.sub.CC to the level of (VL.sub.F−V.sub.OFF), the high-frequency current I.sub.AMP will charge up a load capacitor C.sub.PA to help maintain the modulated voltage V.sub.CC at the level of (VL.sub.F−V.sub.OFF). The load capacitor C.sub.PA, which may be provided inside or outside each of the power amplifier circuits 44(1)-44(N), has a smaller capacitance (e.g., 100 pF). As a result, according to equation (Eq. 4), it is possible to charge up the load capacitor C.sub.PA quickly with a reduced amount of the low-frequency current I.sub.DC.

[0064] At the start time T.sub.1 of the OFDM symbol S.sub.N, the control circuit 60 opens the bypass switch S.sub.BYP such that the offset capacitor C.sub.OFF can be charged by the low-frequency current I.sub.DC to raise the offset voltage V.sub.OFF from the present voltage level VL.sub.P to the future voltage level VL.sub.F. Given that the modulated voltage V.sub.CC has already been raised by the voltage amplifier 54 and maintained by the load capacitor C.sub.PA, it is thus possible to charge the offset capacitor C.sub.OFF at a slower rate to help further reduce demand for the low-frequency current I.sub.DC (a.k.a., rush current). As the offset voltage V.sub.OFF gradually increases, the voltage amplifier 54 can gradually reduce the modulated initial voltage V.sub.AMP such that a sum of the modulated initial voltage V.sub.AMP and the offset voltage V.sub.OFF would equal the future voltage level VL.sub.F.

[0065] At time T.sub.3, the offset voltage V.sub.OFF is raised to the future voltage value VL.sub.F. In this regard, the modulated initial voltage V.sub.AMP is no longer needed. Accordingly, the control circuit 60 can close the bypass switch S.sub.BYP and deactivate the voltage amplifier 54. In one embodiment, the control circuit 60 may close the bypass switch S.sub.BYP and deactivate the voltage amplifier 54 concurrently at time T.sub.3. Alternatively, the control circuit 60 may deactivate the voltage amplifier 54 with a timing delay T.sub.DLY from closing the bypass switch S.sub.BYP.

[0066] FIG. 3B is a timing diagram providing an exemplary illustration of the distributed power management circuit 38 of FIG. 2 configured to decrease the modulated voltage V.sub.CC from a present voltage level VL.sub.P in OFDM symbol S.sub.N−1 (also referred to as “a present OFDM symbol”) to a future voltage level VL.sub.F in OFDM symbol S.sub.N (also referred to as “an upcoming OFDM symbol”). Common elements between FIGS. 2 and 3B are shown therein with common element numbers and will not be re-described herein.

[0067] Herein, the control circuit 60 receives the target voltage V.sub.TGT during the OFDM symbol S.sub.N−1 and prior to a start time T.sub.1 of the OFDM symbol S.sub.N. The target voltage V.sub.TGT indicates that the modulated voltage V.sub.CC is set to decrease from the present voltage level VL.sub.P (e.g., 5.5 V) in the OFDM symbol S.sub.N−1 to the future voltage level VL.sub.F (e.g., 1 V) in the OFDM symbol S.sub.N. Notably, during the OFDM symbol S.sub.N−1, the bypass switch S.sub.BYP is closed and the offset capacitor C.sub.OFF is charged to maintain the modulated voltage V.sub.CC at the present voltage level VL.sub.P.

[0068] Prior to the start time T.sub.1 of the OFDM symbol S.sub.N (e.g., at time T2), the control circuit 60 opens the bypass switch S.sub.BYP to discharge the offset capacitor C.sub.OFF to reduce the offset voltage V.sub.OFF from the present voltage level VL.sub.P to the future voltage level VL.sub.F. The time T.sub.2 may be so determined to ensure that the offset voltage V.sub.OFF can be reduced to the future voltage level VL.sub.F within the CP duration of the OFDM symbol S.sub.N.

[0069] Notably, the distributed voltage modulation circuit 42 still needs to maintain the modulated voltage V.sub.CC at the present voltage level VL.sub.P during the OFDM symbol S.sub.N−1 while the offset capacitor C.sub.OFF is discharged to reduce the offset voltage V.sub.OFF. In this regard, the control circuit 60 is further configured to activate the voltage amplifier 54 to help maintain the modulated voltage V.sub.CC at the present voltage level VL.sub.P before discharging the offset capacitor C.sub.OFF. In addition, the voltage amplifier 54 also serves as a current sink to absorb discharge current associated with discharging the offset capacitor C.sub.OFF. The control circuit 60 may activate the voltage amplifier 54 with a timing advance T.sub.ADV before opening the bypass switch S.sub.BYP to start discharging the offset capacitor C.sub.OFF. The timing advance T.sub.ADV may be so determined to ensure that the voltage amplifier 54 can be ramped up and settled to maintain the modulated voltage V.sub.CC at the present voltage level VL.sub.P by the time T.sub.2.

[0070] At time T.sub.3, the offset voltage V.sub.OFF is reduced to the future voltage value VL.sub.F. In this regard, the modulated initial voltage V.sub.AMP is no longer needed. Accordingly, the control circuit 60 can close the bypass switch S.sub.BYP and deactivate the voltage amplifier 54. In one embodiment, the control circuit 60 may close the bypass switch S.sub.BYP and deactivate the voltage amplifier 54 concurrently at time T.sub.3. Alternatively, the control circuit 60 may deactivate the voltage amplifier 54 with a timing delay T.sub.DLY from closing the bypass switch S.sub.BYP.

[0071] With reference back to FIG. 2, each of the power amplifier circuits 44(1)-44(N) includes a respective amplifier circuit 64. Notably, each of the amplifier circuits 64 can include one or more power amplifiers 66 for concurrently amplifying the RF signals 47 based on a modulated voltage V.sub.CC for concurrent transmission via multiple antennas (not shown) according to such transmission schemes as multiple-input multiple-output (MIMO) and RF beamforming.

[0072] Each of the power amplifier circuits 44(1)-44(N) includes the respective load capacitor C.sub.PA (a.k.a. decoupling capacitor) coupled to the respective voltage input 48. As previously described, the load capacitor C.sub.PA is chosen to be smaller (e.g., 100 pF) to allow fast switching of the modulated voltage V.sub.CC between OFDM symbols S.sub.N−1 and S.sub.N. However, the smaller load capacitor C.sub.PA will also have a smaller capacitive impedance Z.sub.CPA, which may not be enough to properly match the output impedance Z.sub.OUT presenting at the voltage input 48. Consequently, the ripple voltage V.sub.CC-RP may be created in the modulated voltage V.sub.CC received at the voltage input 48. In this regard, the distributed power management circuit 38 is also configured to suppress the ripple voltage V.sub.CC−RP.

[0073] In an embodiment, the voltage output 46 in the distributed voltage modulation circuit 42 is coupled to the power inductor 52 via a first conductive trace 68 having a first inductive trace impedance Z.sub.TRACE1, and to the respective voltage input 48 in each of the power amplifier circuits 44(1)-44(N) via a second conductive trace 70 having a second inductive trace impedance Z.sub.TRACE2. Accordingly, the output impedance Z.sub.OUT seen at the respective voltage input 48 would include both the inherent impedance Z.sub.DPMIC of the distributed voltage modulation circuit 42 and the second inductive trace impedance Z.sub.TRACE2 of the second conductive trace 70. Thus, to reduce the output impedance Z.sub.OUT to help suppress the ripple voltage V.sub.CC−RP, it is necessary to reduce both the inherent impedance Z.sub.DPMIC and the second inductive trace impedance Z.sub.TRACE2.

[0074] In one aspect, it is possible to reduce the second inductive trace impedance Z.sub.TRACE2 by providing the distributed voltage modulation circuit 42 substantially close to the respective voltage input 48 of the power amplifier circuits 44(1)-44(N). In an embodiment, the distributed voltage modulation circuit 42 can be provided close enough to the respective voltage input 48 such that the second inductive trace impedance Z.sub.TRACE2 is less than 0.7 nanohenry (nH). In contrast, since the PMIC 40 is only providing the low-frequency current I.sub.DC, the first conductive trace 68 can be substantially longer (e.g., 50 times longer) than the second conductive trace 70. In other words, the PMIC 40 can be provided farther away from the respective voltage input 48 to provide more implementation flexibilities.

[0075] In another aspect, it is possible to reduce the inherent impedance Z.sub.DPMIC inside the voltage amplifier 54. In this regard, FIG. 4 is a schematic diagram providing an exemplary illustration of an inner structure of the voltage amplifier 54 in the distributed voltage modulation circuit 42 in FIG. 2. Common elements between FIGS. 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0076] In an embodiment, the voltage amplifier 54 includes an input/bias stage 72 and an output stage 74. The input/bias stage 72 is configured to receive the modulated voltage V.sub.TGT and a feedback signal V.sub.CC−FB indicating the modulated voltage V.sub.CC at the voltage output 46. Accordingly, the input/bias stage 72 generates a pair of bias signals 76P (a.k.a. first bias signal), 76N (a.k.a. second bias signal) to control the output stage 74.

[0077] In an embodiment, the output stage 74 is configured to generate the modulated initial voltage V.sub.AMP at the output 58 based on a selected one of the bias signals 76P, 76N. The output stage 74 is also configured to receive the feedback signal V.sub.CC−FB. Accordingly, the output stage 74 can modify the modulated initial voltage V.sub.AMP based on the feedback signal V.sub.CC−FB to reduce the inherent impedance Z.sub.DPMIC to thereby reduce the output impedance Z.sub.OUT.

[0078] In an embodiment, the output stage 74 includes a first transistor 78P and a second transistor 78N. In a non-limiting example, the first transistor 78P is a p-type field-effect transistor (pFET) and the second transistor 78N is an n-type FET (nFET). In this example, the first transistor 78P includes a first source electrode C.sub.1, a first drain electrode D.sub.1, and a first gate electrode G.sub.1, and the second transistor 78N includes a second source electrode C.sub.2, a second drain electrode D.sub.2, and a second gate electrode G.sub.2. Specifically, the first drain electrode D.sub.1 is configured to receive the supply voltage V.sub.SUP, the second drain electrode D2 is coupled to a ground (GND), and the first source electrode C.sub.1 and the second source electrode C.sub.2 are both coupled to the output 58 of the voltage amplifier 54.

[0079] The first gate electrode Gi is coupled to the input/bias stage 72 to receive the bias signal 76P and the second gate electrode G.sub.2 is coupled to the input/bias stage 72 to receive the bias signal 76N. Herein, the input/bias stage 72 is configured to generate the bias signal 76P in response to an increase of the modulated voltage V.sub.CC or generate the bias signal 76N in response to a decrease of the modulated voltage V.sub.CC. Specifically, the first transistor 78P will be turned on to output the modulated initial voltage V.sub.AMP and source the high-frequency current I.sub.AMP (e.g., an alternating current) from the supply voltage V.sub.SUP in response to receiving the bias signal 76P, and the second transistor 78N will be turned on to output the modulated initial voltage V.sub.AMP from the supply voltage V.sub.SUP and sink the high-frequency current I.sub.AMP to the GND in response to receiving the bias signal 76N.

[0080] In this embodiment, the output stage 74 also includes a first Miller capacitor C.sub.Miller1 and a second Miller capacitor C.sub.Miller2. Specifically, the first Miller capacitor C.sub.Miller1 is coupled between the output 58 of the voltage amplifier 54 and the first gate electrode G.sub.1, and the second Miller capacitor C.sub.Miller2 is coupled between the output 58 of the voltage amplifier 54 and the second gate electrode G.sub.2. In this regard, the output stage 74 can be regarded as a typical class AB rail-rail OpAmp output stage. The first Miller capacitor C.sub.Miller1 and the second Miller capacitor C.sub.Miller2 not only can stabilize controls of the first transistor 78P and the second transistor 78N (e.g., mitigating so-called Miller effect), but may also reduce the closed-loop output impedance of the voltage amplifier 54.

[0081] Notably, since the first Miller capacitor .sub.CMiller1 and the second Miller capacitor C.sub.Miller2 are each coupled to the output 58 of the voltage amplifier 54, the first Miller capacitor C.sub.Miller1 and the second Miller capacitor C.sub.Miller2 can reduce the inherent impedance Z.sub.DPMIC, which is part of the output impedance Z.sub.OUT.

[0082] In an embodiment, it is possible to configure the distributed power management circuit 38 to support the embodiments described above based on a process. In this regard, FIG. 5 is a flowchart of an exemplary process 200 for supporting distributed power management in the distributed power management circuit 38 of FIG. 2.

[0083] Herein, the distributed voltage modulation circuit 42 is coupled to the PMIC 40 via the first conductive trace 68 having the first inductive trace impedance Z.sub.TRACE1 (step 202). Next, the distributed voltage modulation circuit 42 is coupled to the respective voltage input 48 in each of the power amplifier circuits 44(1)-44(N) via the second conductive trace 70 having the second inductive trace impedance Z.sub.TRACE2 that is substantially smaller than the first inductive trace impedance Z.sub.TRACE1 (e.g., 50 times smaller) (step 204). The distributed voltage modulation circuit 42 receives the modulated target voltage V.sub.TGT indicating that the modulated voltage V.sub.CC will change from the present voltage level VL.sub.P in the present time interval S.sub.N−1 to the future voltage level VL.sub.F in the upcoming time interval S.sub.N (step 206). Accordingly, the voltage amplifier 54 in the distributed voltage modulation circuit 42 will be activated to change the modulated initial voltage V.sub.AMP prior to the start of the upcoming time interval S.sub.N such that the modulated initial voltage V.sub.AMP can be changed to the future voltage level VL.sub.F withing the defined temporal limit from the start of the upcoming time interval S.sub.N (step 208).

[0084] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.