Control circuit for a flyback converter, related integrated circuit, electronic flyback converter and method

Abstract

A control circuit for a driving an electronic switch associated with a switching node of a flyback converter includes a comparison circuit configured to generate a switch-off signal by comparing a current measurement signal with a current measurement threshold signal. A valley detection circuit is configured to generate a trigger in a trigger signal when a valley signal indicates a valley in a voltage at the switching node of the flyback converter, and a blanking circuit is configured to generate a switch-on signal by combining the trigger signal with a timer signal provide by a timer circuit. The timer signal indicates whether a blanking time-interval has elapsed.

Claims

1. A control circuit for a flyback converter, the flyback converter including: a positive and a negative input terminal configured to receive an input voltage; first and second output terminals configured to provide an output voltage or output current; a transformer having a primary winding and a secondary winding, wherein a first terminal of the primary winding is connected to the positive input terminal and a second terminal of the primary winding represents a switching node; a first electronic switch, connected between the switching node and the negative input terminal; and a second electronic switch connected with the secondary winding in series between the two output terminals, wherein the control circuit is configured to generate a drive signal for the first electronic switch, wherein the control circuit is configured to generate switching cycles by setting the drive signal to a first logic level for a switch-on duration for closing the first electronic switch and a second logic level for a switch-off duration for opening the first electronic switch, and wherein the control circuit comprises: a first terminal configured to be connected to a current measurement circuit and configured to generate a current measurement signal indicative of a current flowing through the primary winding during the switch-on duration; and a second terminal configured to be connected to a valley monitoring circuit and configured to provide a valley signal indicative of valleys in a voltage at the switching node; a comparison circuit configured to generate a switch-off signal by comparing the current measurement signal with a current measurement threshold signal; a valley detection circuit configured to generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node; and a blanking circuit configured to generate a switch-on signal by combining the trigger signal with a timer signal provided by a timer circuit, the timer signal indicating whether a blanking time-interval has elapsed, wherein the blanking circuit is configured to: start the timer circuit in response to the switch-on signal or the switch-off signal; monitor during each switching cycle a first number of triggers in the trigger signal, wherein the first number is indicative of the number of valleys in the voltage at the switching node until the first electronic switch is closed; and monitor during each switching cycle a second number of triggers in the trigger signal until the timer signal indicates that the blanking time-interval has elapsed, wherein the second number is indicative of the number of valleys in the voltage at the switching node during the blanking time-interval.

2. The control circuit according to claim 1, further comprising: a circuit configured to: in response to the switch-on signal, set the drive signal to the first logic level for closing the first electronic switch; and in response to the switch-off signal, set the drive signal to the second logic level for opening the first electronic switch.

3. The control circuit according to claim 1, wherein the blanking circuit is further configured to: determine whether the timer signal indicates that the blanking time-interval has elapsed and whether the first number reaches or exceeds a maximum value; store the first number as new maximum value in response to the first number exceeding the maximum value; disable the switch-on signal in response to the timer signal indicating that the blanking time-interval has not elapsed or in response to the second number being smaller than the maximum value; and set the switch-on signal in response to the trigger signal in response to the timer signal indicating that the blanking time-interval has elapsed and the second number reaches or exceeds the maximum value.

4. The control circuit according to claim 3, wherein the blanking circuit is further configured to: selectively reset the maximum value by comparing the second number with the first number or the maximum value.

5. The control circuit according to claim 4, wherein the blanking circuit comprises a first comparator circuit configured to set a blanking signal by comparing the second number with the first number, the blanking circuit further configured to: determine a first condition in response to the second number being smaller than the first number minus a first threshold value; determine a second condition in response to the second number being equal to or greater than the first number minus the first threshold value, but smaller than the first number minus a second threshold value; and determine a third condition in response to the second number being equal to or greater than the first number minus the second threshold value.

6. The control circuit according to claim 5, wherein the blanking circuit comprises a reset circuit configured to: reset the maximum value in response to the first comparator circuit indicating the first condition for a first number of consecutive switching cycles; and reset the maximum value in response to the first comparator circuit indicating the second condition for a second number of consecutive switching cycles, the second number of consecutive switching cycles being greater than the first number of consecutive switching cycles.

7. The control circuit according to claim 6, comprising: a terminal configured to be connected to a feedback circuit and configured to provide a feedback signal indicative of the output voltage or output current; and a regulator circuit comprising an integral component configured to generate the current measurement threshold signal as a function of the feedback signal.

8. The control circuit according to claim 7, wherein the reset circuit is configured to periodically store a value of the feedback signal and reset the maximum value when the feedback signal increases more than a given amount.

9. The control circuit according to any of claim 6, wherein the reset circuit is configured to: determine whether the current measurement signal reaches a maximum threshold signal, and reset the maximum value in response to the current measurement signal reaching the maximum threshold signal for a third number of consecutive switching cycles.

10. The control circuit according to claim 1, wherein the blanking circuit comprises a first digital counter configured to increase the first number in response to the trigger signal and reset the first number in response to the switch-on signal or the switch-off signal.

11. The control circuit according to claim 10, wherein the blanking circuit comprises a second digital counter configured to, when the timer signal indicates that the blanking time-interval has not elapsed, increase the second number in response to the trigger signal and reset the second number in response to the switch-on signal or the switch-off signal.

12. The control circuit according to claim 1, wherein the blanking circuit comprises: a combinational logic circuit configured to generate the switch-on signal by combining the trigger signal with a blanking signal, and a comparator circuit configured to set the blanking signal to: a first logic level when the timer signal indicates that the blanking time-interval has not elapsed or the second number is smaller than a given maximum value; and a second logic level when the timer signal indicates that the blanking time-interval has elapsed and the second number reaches or exceeds the maximum value.

13. The control circuit according to claim 1, wherein the timer circuit is implemented with a digital counter circuit configured to: reset an internal count value in response to the switch-on signal or the switch-off signal; increase the internal count value in response to a clock signal; and set the timer signal to a first logic level when the internal count value is smaller than a reference value indicative of the duration of the blanking time-interval and to a second logic level when the internal count value is greater than the reference value, wherein the reference value is determined as a function of the feedback signal, the current measurement signal or the current measurement threshold signal.

14. The control circuit according to claim 1, wherein the valley detection circuit comprises: a comparator circuit configured to compare the valley signal with a reference signal; and an edge detector configured to generate a pulse in the trigger signal when the signal at the output of the comparator circuit is set.

15. An integrated circuit, comprising the control circuit according to claim 1.

16. A flyback converter, comprising: a positive and a negative input terminal configured to receive an input voltage; two output terminals configured to provide an output voltage or output current; a transformer having a primary winding and a secondary winding, wherein a first terminal of the primary winding is connected to the positive input terminal and a second terminal of the primary winding represents a switching node; a first electronic switch, connected between the switching node and the negative input terminal; a second electronic switch connected with the secondary winding in series between the two output terminals; a current measurement circuit configured to generate a current measurement signal indicative of a current flowing through the primary winding T1 during the switch-on duration; a valley monitoring circuit configured to provide a valley signal indicative of demagnetization of valleys in the voltage at the switching node; and a control circuit configured to generate a drive signal for the first electronic switch, wherein the control circuit is configured to generate switching cycles by setting the drive signal to a first logic level for a switch-on duration for closing the first electronic switch and a second logic level for a switch-off duration for opening the first electronic switch, the control circuit including: a comparison circuit configured to generate a switch-off signal by comparing the current measurement signal with a current measurement threshold signal; a valley detection circuit configured to generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node; and a blanking circuit configured to generate a switch-on signal by combining the trigger signal with a timer signal provided by a timer circuit, the timer signal indicating whether a blanking time-interval has elapsed, wherein the blanking circuit is configured to: start the timer circuit in response to the switch-on signal or the switch-off signal; monitor during each switching cycle a first number of triggers in the trigger signal, wherein the first number is indicative of the number of valleys in the voltage at the switching node until the first electronic switch is closed; and monitor during each switching cycle a second number of triggers in the trigger signal until the timer signal indicates that the blanking time-interval has elapsed, wherein the second number is indicative of the number of valleys in the voltage at the switching node during the blanking time-interval.

17. The flyback converter according to claim 16, wherein the blanking circuit is further configured to: determine whether the timer signal indicates that the blanking time-interval has elapsed and whether the first number reaches or exceeds a maximum value; store the first number as new maximum value in response to the first number exceeding the maximum value; disable the switch-on signal in response to the timer signal indicating that the blanking time-interval has not elapsed or in response to the second number being smaller than the maximum value; and set the switch-on signal in response to the trigger signal in response to the timer signal indicating that the blanking time-interval has elapsed and the second number reaches or exceeds the maximum value.

18. The flyback converter according to claim 16, wherein the valley monitoring circuit comprising an auxiliary winding of the transformer.

19. A method of operating a flyback converter, the flyback converter including: a positive and a negative input terminal configured to receive an input voltage; first and second output terminals configured to provide an output voltage or output current; a transformer having a primary winding and a secondary winding, wherein a first terminal of the primary winding is connected to the positive input terminal and a second terminal of the primary winding represents a switching node; a first electronic switch, connected between the switching node and the negative input terminal; a second electronic switch connected with the secondary winding in series between the two output terminals; and a control circuit configured to generate a drive signal for the first electronic switch, wherein the control circuit is configured to generate switching cycles by setting the drive signal to a first logic level for a switch-on duration for closing the first electronic switch and a second logic level for a switch-off duration for opening the first electronic switch, wherein the control circuit includes: a first terminal configured to be connected to a current measurement circuit and configured to generate a current measurement signal indicative of a current flowing through the primary winding during the switch-on duration; and a second terminal configured to be connected to a valley monitoring circuit and configured to provide a valley signal indicative of valleys in a voltage at the switching node; a comparison circuit configured to generate a switch-off signal by comparing the current measurement signal with a current measurement threshold signal; a valley detection circuit configured to generate a trigger in a trigger signal when the valley signal indicates a valley in the voltage at the switching node; and a blanking circuit configured to generate a switch-on signal by combining the trigger signal with a timer signal provided by a timer circuit, the timer signal indicating whether a blanking time-interval has elapsed, the method comprising: starting the timer circuit in response to the switch-on signal or the switch-off signal; monitoring during each switching cycle a first number of triggers in the trigger signal, wherein the first number is indicative of the number of valleys in the voltage at the switching node until the first electronic switch is closed; and monitoring during each switching cycle a second number of triggers in the trigger signal until the timer signal indicates that the blanking time-interval has elapsed, wherein the second number is indicative of the number of valleys in the voltage at the switching node during the blanking time-interval.

20. The method according to claim 19, further comprising: determining whether the timer signal indicates that the blanking time-interval has elapsed and whether the first number reaches or exceeds a given maximum value, and storing the first number as a new maximum value in response to the first number exceeding the maximum value; disabling the switch-on signal in response to the timer signal indicating that the blanking time-interval has not elapsed or the second number is smaller than the maximum value; and setting the switch-on signal in response to the trigger signal in response to the timer signal indicating that the blanking time-interval has elapsed and the second number reaches or exceeds the maximum value; and selectively resetting the maximum value by comparing the second number with the first number or the maximum value.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The features and advantages of the present disclosure will become apparent from the following detailed description of practical embodiments thereof, shown by way of non-limiting example in the accompanying drawings, in which:

(2) FIG. 1 shows a circuit schematic of a flyback converter;

(3) FIG. 2 shows a circuit schematic of a flyback converter with a clamp circuit;

(4) FIG. 3 shows exemplary waveforms of the converter of FIG. 2;

(5) FIG. 4 shows a circuit schematic of a flyback converter comprising a quasi-resonant control circuit;

(6) FIG. 5 shows a first embodiment of a quasi-resonant control circuit in accordance with the present description;

(7) FIG. 6 shows a second embodiment of a quasi-resonant control circuit in accordance with the present description;

(8) FIG. 7 shows an embodiment of the operation of the control circuits of FIG. 5 or 6; and

(9) FIGS. 8, 9, 10, 11 and 12 show embodiments of various sub-circuits of the control circuits of FIG. 5 or 6.

DETAILED DESCRIPTION

(10) In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(11) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(12) The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(13) In FIGS. 5 to 12 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 4 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(14) FIG. 5 shows an embodiment of a control/driver circuit 210a for a flyback converter according to the present disclosure. For a general description of a quasi-resonant flyback converter, reference can be made to the previous description, in particular with respect to FIGS. 2 and 4.

(15) Specifically, in the embodiment shown in FIG. 5, the control circuit 210a, such as an integrated circuit, comprises: two terminals for receiving a supply voltage, such as a (positive) terminal VDD and a ground terminal GND; a terminal configured to be connected to a feedback circuit 212 providing a feedback signal FB indicative of the output quantity to be regulated, e.g., the output voltage Vout or the output current Iout; a terminal configured to be connected to a current measurement circuit 214 configured to generate a signal CS indicative of (e.g., proportional to) the current Ipri flowing through the primary winding T1 (at least) during the switch-on period T.sub.ON; and a terminal configured to be connected to a valley/demagnetization monitoring circuit 216 configured to generate a signal ZCD indicative of the valleys in the voltage V.sub.SN, e.g., the magnetization and demagnetization of the transformer T (at least) during the switch-off period T.sub.OFF.

(16) In the embodiment considered, the control circuit 210 comprises a terminal for providing the drive signal DRV to an external electronic switch SW, such as the gate terminal of a respective n-channel FET, e.g., a NMOS.

(17) Conversely, FIG. 6 shows an embodiment, wherein the electronic switch SW is integrated in the integrated circuit of the control circuit 210a. In this case, the control circuit 210a may comprise a terminal configured to be connected to the switching node SN. For example, when the electronic switch SW is an n-channel FET, e.g., a NMOS, the drain terminal of this n-channel FET SW may be connected (e.g., directly) to the terminal SN.

(18) In various embodiments, the current measurement circuit 214 may be implemented with a current sensor, such as a resistor RCS, connected in series with the switch SW, e.g., between the source terminal of a respect n-channel FET SW, and the ground terminal GND, wherein the voltage at the resistor RCS is proportional to the current flowing through the switch SW. Also in this case, the current measurement circuit 214, e.g., the resistor RCS, may be internal (see FIG. 6) or external (see FIG. 5) with respect to the integrated circuit of the control circuit 210a.

(19) In various embodiments, the control circuit 210a comprises a comparison circuit 2110 configured to compare the signal CS indicative of the primary side current Ipri with a threshold signal PTH.

(20) Specifically, in various embodiments, the switch SW is switched off when the value CS reaches (or exceeds) the value of the threshold signal PTH. Accordingly, in various embodiments, the comparison circuit 2110 comprises a (preferably analog) comparator 2116 configured to generate a signal S_OFF indicating that the switch SW should be switched off by comparing the signal CS with the threshold signal PTH.

(21) In various embodiments, the comparison circuit 2110 comprises also a second (preferably analog) comparator 2114 configured to generate a signal OCP by comparing the signal CS with a second threshold signal OTH indicative of a maximum value, thereby implementing an over-current protection. In this case, the signals at the output terminals of the comparators 2116 and 2114 may be combined, e.g., via a logic OR gate 2118, in order to generate the signal S_OFF. In case such an over-current protection is not used, the signal S_OFF may correspond directly to the comparison signal at the output of the comparator 2116.

(22) In various embodiments, the threshold signal PTH is generated as a function of an output quantity, i.e., the output voltage Vout or the output current Iout. For example, in various embodiments, the electronic converter comprises for this purpose: a feedback circuit 212 configured to generate a feedback signal FB indicative of the output quantity, such as a voltage or current sensor, optionally comprising also an optocoupler (or other kinds of transmission circuits) for transmitting the feedback signal FB from the secondary side to the primary side of the transformer T; and a regulator circuit 2112 comprising an integral component (I), and optionally a proportional (P) and/or derivative (D) component, configured to generate the threshold signal PTH as a function of the feedback signal FB.

(23) In various embodiments, the feedback signal FB may be proportional to the output quantity or may already represent an error signal indicative of the difference between the output quantity and a requested value for the output quantity.

(24) In various embodiments, at least part of the regulator circuit 2112 and/or the feedback circuit 212 may be implemented in the integrated circuit of the control circuit 210a. For example, in FIGS. 5 and 6, the regulator 2112 is implemented directly within the control circuit 210a.

(25) In the embodiment considered, for switching the switch SW on, the control circuit 210a comprises: a valley/demagnetizing detection circuit 2100 configured to analyze the signal ZCD provided by the valley/demagnetization monitoring circuit 216 and generate a trigger signal T.sub.ZCD where the signal ZCD indicates a valley in the voltage V.sub.SN/demagnetization of the transformer T; and a blanking circuit 2140 configured to generate a signal BLANK used to enable the valley/demagnetizing detection circuit 2100.

(26) For example, in the embodiment considered, the valley/demagnetizing detection circuit 2100 comprises: a comparator 2102 configured to compare the signal ZCD with a reference signal REF, which usually is close to 0 V, wherein the output of the comparator 2102 is set when the signal ZCD falls below the value of the reference signal REF; and an edge detector 2104 configured to generate a pulse in the signal T.sub.ZCD when the signal at the output of the comparator 2100 is set.

(27) In the embodiment considered, the valley/demagnetizing detection circuit 2100 is enabled via a logic gate 2120, such as a AND gate, configured to generate a signal S_ON indicating that the switch SW should be switched on as a function of the trigger signal T.sub.ZCD and the signal BLANK, i.e., the signal BLANK masks the signal T.sub.ZCD.

(28) Accordingly, in the embodiment considered, the signals S_ON and S_OFF may be provided to a latch or flip-flop 2130, e.g., the set and reset input of a respective set-reset latch or flip-flop, and the signal at the output of the latch or flip-flop 2130 may be used to drive the switch SW, e.g., via an optional FET driver circuit 2132 configured to generate the drive signal DRV as a function of the signal at the output of the latch or flip-flop 2130.

(29) Thus, in addition to the circuits 2100-2140, (at least) one or more of the following circuits may also be implemented together with the control circuit 210 in an integrated circuit: the electronic switch SW; the driver circuit 2132; at least part of the feedback circuit 212, such as a respective optocoupler; the current measurement circuit 214, such as the resistor RCS; and/or the valley/demagnetization monitoring circuit 216, such as the voltage divider R1/R2.

(30) FIG. 7 shows a first embodiment of the operation of the blanking circuit 2140.

(31) After a start step 1000, e.g., corresponding to the power-on of the control circuit 210a, the blanking circuit 2140 performs at a step 1002 an initialization operation. During this step, the blanking circuit 1040 determines a value indicative of a requested blanking time T.sub.BLANK. General, the blanking time T.sub.BLANK may be predetermined/constant, or the blanking circuit 1040 may be configured to determine the blanking time T.sub.BLANK as a function of the input or output power level, as indicated, e.g., by the feedback signal FB or the threshold signal PTH used as peak value for the signal CS, i.e., the blanking circuit 1040 may determine the blanking time T.sub.BLANK as a function of (at least one of) the feedback signal FB, the threshold signal PTH or the signal CS. Moreover, the blanking circuit 1040 may initialize other parameters, such as parameters k and k.sub.M.

(32) Next, the blanking circuit 1040 starts at a step 1004 a timer circuit configured to determine when the blanking time T.sub.BLANK elapses. For example, the timer circuit may be stared when the switch SW is opened (instant t.sub.1) or when the switch SW is closed (one of the instants t.sub.3). For example, in the embodiment shown in FIGS. 5 and 6, the blanking circuit 1040 may set the signal BLANK to low while the timer circuit signals that the blanking time T.sub.BLANK has not elapsed yet.

(33) Next, the blanking circuit 1040 monitors at a step 1006 the trigger signal T.sub.ZCD (or the signal at the output of the comparator 2102) in order to determine the number of valleys that occur after the transformer demagnetization until the first valley is detected after the time T.sub.BLANK has elapsed. For example, for this purpose, the blanking circuit 1040 may reset the count value k between the instants t.sub.1 and t.sub.2, and preferably at the instant when the switch SW is opened (instant t.sub.1). Next, while the signal of the timer circuit indicates that the blanking time T.sub.BLANK has not yet elapsed, this count value k may be increased at each valley, e.g., at each trigger in the signal T.sub.ZCD.

(34) Next, the blanking circuit 1040 determines at a step 1008 the value of the parameter k.sub.M. Specifically, in various embodiments, the blanking circuit 1040 compares the current value of the parameter k.sub.M with the count value k, and when the count value k is greater than the parameter k.sub.M, i.e., k>k.sub.M, the blanking circuit 1040 stores the current count value k as parameter k.sub.M, i.e., k.sub.M=k. Thus, essentially, the parameter k.sub.M indicates the maximum value of the count value k.

(35) At a verification step 1010, the blanking circuit 1040 compares the current count value k with the parameter k.sub.M.

(36) In case the count value k does not correspond to the value k.sub.M and is thus smaller than the value k.sub.M (output “N” of the verification step 1010), the blanking circuit 1040 proceeds to a step 1012, where the blanking circuit 1040 signals that the next valley should be skipped, e.g., by maintain the signal BLANK at low. At a following step 1014, the blanking circuit 1040 waits then for the next valley (in line with the description of step 1006), increases the count value k by one, and returns to the step 1008.

(37) In case the count value corresponds to the value k.sub.M (output “Y” of the verification step 1010), the blanking circuit 1040 proceeds to a step 1018.

(38) Substantially, the steps 1004-1014 implement a loop in which the signal BLANK is set to low (thus maintaining switched-off the switch SW) until the blanking time T.sub.BLANK has elapsed and the value k corresponds to the value k.sub.M.

(39) Generally, as schematically shown via a step 1016, instead of determining at the step 1006 the number of valleys during the blanking time T.sub.BLANK, the blanking circuit 1040 could also use directly the steps 1008-1014 in order to sequentially increase the count value k while the blanking time T.sub.BLANK has not elapsed yet. For this purpose, the blanking circuit 1040 may verify at the step 1010 or the additional verification step 1016 whether the blanking time T.sub.BLANK has elapsed. In case the blanking time T.sub.BLANK has not elapsed (output N of the verification step 1012), the blanking circuit 1040 may return to the step 1012. Conversely (output Y of the verification step 1012), the blanking circuit 1040 may proceed to the step 1018.

(40) Thus, the blanking circuit 1040 is configured (via the steps 1006-1016) to monitor the number k of valleys until both of the following conditions are satisfied: the timer circuit of the blanking circuit 1040 indicates that the blanking time T.sub.BLANK has elapsed, and the number k of valleys has reached or exceeds a given maximum value k.sub.M.

(41) In case, the number k is greater than the maximum value k.sub.M (i.e., the number of valleys during the blanking time T.sub.BLANK is greater than the value k.sub.M), the blanking circuit 1040 stores the current number k as new maximum value k.sub.M, thereby, e.g., increasing the value k.sub.M due to a load reduction or an increase of the input voltage Vin.

(42) Assuming that initially no blanking occurs, i.e., k=0, and k.sub.M=0, a load reduction may result in a frequency increase until one or more valleys k fall within the blanking interval and the respective number k of valleys will also be stored as parameter k.sub.M. In case the load increases again, the blanking circuit 1040 will continue to skip k.sub.M valleys, thereby implementing a valley-lock function.

(43) Thus, the steps 1004-10016 essentially follow a load reduction, but do not handle a load increase.

(44) Accordingly, in various embodiments, the blanking circuit 1040 is also configured to reset the value k.sub.M when given conditions are met.

(45) Specifically, in the embodiment shown in FIG. 7, the blanking circuit 1040 is configured to store the number k.sub.QR of valleys during the blanking interval T.sub.BLANK, e.g., by storing the value k at the step 1006. Alternatively, the value k.sub.QR may be increased only during the blanking time, thus indicating the number of valleys the converter would operate at without the valley-lock feature. Thus, in general the blanking circuit 1040 is configured to also monitor the number k.sub.QR of valleys until the timer circuit of the blanking circuit 1040 indicates that the blanking time T.sub.BLANK has elapsed.

(46) Specifically, in case of a load increase, this value k.sub.QR will decrease. Accordingly, in various embodiments, the blanking circuit 1040 is configured to compare at a step 1020 the value k.sub.QR with the value k.sub.M or similarly k (insofar as these values should correspond at the end of the steps 1004-1018).

(47) Specifically, in various embodiments the blanking circuit 1040 is configured to: determine a first condition “A” indicating a fast change by verifying whether the current value k.sub.QR is smaller than the current value of k.sub.M (or k) minus a first threshold value n.sub.H, i.e., k.sub.QR<k.sub.M−n.sub.H; determine a second condition “B” indicating a slow change by verifying whether the current value k.sub.QR is greater than the current value of k.sub.M (or k) minus the first threshold value n.sub.H, but smaller than the current value of k.sub.M (or k) minus a second threshold value n.sub.L, i.e., k.sub.M−n.sub.H≤k.sub.QR<k.sub.M−n.sub.L; and determine a third condition “C” indicating that no substantive change occurred by verifying whether the current value k.sub.QR is greater than the current value of k.sub.M (or k) minus the second threshold value n.sub.L, i.e., k.sub.QR≥k.sub.M−n.sub.L.

(48) For example, in various embodiments, the first threshold n.sub.H is two, i.e., n.sub.H=2 and the second threshold n.sub.L is one, i.e., n.sub.L=1. In this case, the blanking circuit may determine the following conditions:
k.sub.QR<k.sub.M−2;  condition A:
k.sub.QR=k.sub.M−2; and  condition B:
k.sub.QR>k.sub.M−2.  condition C:

(49) In various embodiments, if the blanking circuit 1040 determines the condition “A” (output “A” of the verification step 1018), the blanking circuit 1040 is configured to reset the value k.sub.M at a step 1026.

(50) In various embodiments, the blanking circuit 1040 does not proceed directly to the step 1026, but increases at a step 1022 a fast-change count value FCNT, and compares at a step 1024 this fast-change count value FCNT with a threshold FTH.

(51) Specifically, in the embodiment considered, in case the fast-change count value FCNT reaches the threshold FTH (output “Y” of the verification step 1024) the blanking circuit 1040 proceeds to the step 1026. Conversely (output “N” of the verification step 1024), the blanking circuit 1040 resets at a step 1032 the count value and returns to the step 1004. Thus, if the steps 1022 and 1024 are omitted, essentially the threshold FTH corresponds to one.

(52) Similarly, the blanking circuit 1040 proceeds from the step 1026 to the step 1032 for monitoring the next switching-cycle.

(53) Thus, in case the value k.sub.QR remains in the (fast-change) condition “A” for a given number FTH of switching cycles, the value k.sub.M is reset.

(54) In various embodiments, if the blanking circuit 1040 determines the condition “B” (output “B” of the verification step 1018), the blanking circuit 1040 is configured to similarly reset the value k.sub.M at a step 1026. Specifically, in this case, the blanking circuit 1040 does not proceed directly to the step 1026, but increases at a step 1028 a slow-change count value SCNT, and compares at a step 1030 this slow-change count value SCNT with a threshold STH, wherein the threshold is greater than the threshold FTH (if the optional steps 1022 and 1024 are used).

(55) Specifically, in the embodiment considered, in case the slow-change count value SCNT reaches the threshold STH (output “Y” of the verification step 1028) the blanking circuit 1040 proceeds to the step 1026. Conversely (output “N” of the verification step 1028), the blanking circuit 1040 proceeds to the step 1032 for monitoring the next switching-cycle.

(56) Thus, in case the value k.sub.QR remains in the (slow-change) condition “B” for a given number STH of switching cycles, the value k.sub.M is reset.

(57) Finally, if the blanking circuit 1040 determines the condition “C” (output “C” of the verification step 1018), the blanking circuit 1040 proceeds to the step 1032 for monitoring the next switching-cycle, i.e., the value k.sub.M is not reset when no substantives changes occur, thereby essentially implementing a hysteresis function.

(58) In various embodiments, the blanking circuit 1040 is configured to: optionally, in response to the detection of condition A, e.g., at the step 1022, reset the count value SCNT; in response to the detection of condition B, e.g., at the step 1028, reset the count value FCNT; and in response to the detection of condition C, e.g., at a step 1034, reset the count value FCNT and the count value SCNT.

(59) Thus, in various embodiments, the value k.sub.M is not reset for small load changes, and the value k.sub.M is reset after less switching cycles in case of greater load changes.

(60) FIG. 8 shows an embodiment of an electronic circuit configured to implement the operation of the blanking circuit 2140 described with respect to FIG. 7.

(61) In the embodiment considered, the blanking circuit 2140 comprise a timer circuit 428 configured to monitor a time interval T.sub.BLANK and generate a timer signal BLANK_T when the time interval T.sub.BLANK elapses, e.g., with respect to the switch-on or the switch-off instant of the switch SW. For example, in the embodiment considered, the timer circuit 428 is implemented with a digital counter circuit configured to: reset an internal count value in response to the signal S_ON or S_OFF; increase the internal count value in response to a clock signal CLK; and set the timer signal BLANK_T to a first logic level (e.g., low) when the internal count value is smaller than a reference value C_BLANK indicative of the duration of the time interval T.sub.BLANK and to a second logic level (e.g., high) when the internal count value is greater than the reference value C_BLANK. As described in the foregoing, the value of the time interval T.sub.BLANK, e.g., the value C_BLANK, may be determined as a function of the power requirements, as indicated, e.g., by the signal FB or PTH.

(62) In the embodiment considered, the blanking circuit 2140 comprises also a valley counter 408 configured to count the valleys indicated by the signal ZCD, e.g., by increasing a count value in response to the signal T.sub.ZCD, thereby providing the value k.

(63) As described in the foregoing, the blanking circuit 2140 is configured to provide two additional values: the maximum value k.sub.M of the count value k; and the number of the valleys k.sub.QR during the time interval T.sub.BLANK.

(64) Thus, in general, these values may be determined as a function of the value k.

(65) For example, in various embodiments, a comparison circuit 424 is configured to compare the current value k.sub.M with the value k and generate a trigger signal when the value k is greater than the value k.sub.M. Conversely, a second circuit 422 is configured to store the value k if the comparison circuit 424 generate the trigger signal. Thus, in general, the circuit 424 may be implemented with a memory, such as latches or a register, configured to store the signal/value k in response to the trigger signal generated by the comparison circuit 424. Conversely, in the embodiment considered, the circuit 422 is implemented with a counter configured to increase its count value in response to the trigger signal generated by the comparison circuit 424.

(66) Similarly, a circuit 400 may comprise a memory configured to store the value k in response to (e.g., in response to the rising edge of) the timer signal BLANK_T, thereby providing only the number of valleys k.sub.QR during the blanking interval T.sub.BLANK. Conversely, in the embodiment considered, the circuit 400 comprises a separate counter circuit 404 configured to monitor separately the valleys during the blanking interval T.sub.BLANK. For this purpose, the counter circuit 404 has associated a combinational logic circuit 402 configured to provide a trigger signal by combining the trigger signal T.sub.ZCD with the timer signal BLANK_T. Thus, in various embodiments, the counter circuit 404 is configured to increase the signal/value k.sub.QR in response to the trigger signal T.sub.ZCD only when the signal BLANK_T indicates that the time interval T.sub.BLANK has not elapsed, i.e., when the signal BLANK_T has the first logic level.

(67) Thus, in the embodiment considered, three separate counters are used to generate the signals k, k.sub.M and k.sub.QR, but in general also a single counter (or two counters) could be used.

(68) As described in the foregoing, once the time interval T.sub.BLANK has elapsed, the blanking circuit 2140 should enable the activation of the switch SW with the next valley. For example, in the embodiment considered, a comparison circuit 426 is configured to set the blanking signal BLANK (see, e.g., FIG. 4) to: a first logic level (e.g., low), when the time interval T.sub.BLANK has not elapsed or the values k is smaller than the value k.sub.M, i.e., k<k.sub.M; and a second logic level (e.g., high), when the time interval T.sub.BLANK has elapsed and the values k and k.sub.M correspond, i.e., k=k.sub.M.

(69) For example, in order to determine whether the time interval T.sub.BLANK has elapsed, the comparison circuit 426 may monitor the signal BLANK_T.

(70) Thus, essentially the blocks 402, 403, 408, 422, 424 and 426 implement the steps 1002-1018 of FIG. 18.

(71) Specifically, these blocks determine the values k, k.sub.M and k.sub.QR and follow and increase of the maximum value k.sub.M. However, as described in the foregoing, the value k.sub.QR should be used to decide whether the value k.sub.M should be reset. More specifically, as described in the foregoing, the values k (stored in a counter 408) and k.sub.QR (stored in a counter or only a memory 404) should be reset for each switching cycle prior to the instant of the demagnetization of the transformer. For example, in various embodiments, these circuits 404 and 408 are reset in response to the signals S_ON or S_OFF, e.g., in response to a turn-on of the power switch SW.

(72) Thus, once the signal T.sub.ZCD signals valleys in the signal ZCD, the counter k increases (and similarly the count value k.sub.QR). In parallel, the blanking circuit 4140 performs several operations: the comparison circuit 424 compares the value k with the current value k.sub.M and updates the value k.sub.M (i.e., stores the value k or increases the value k.sub.M), when the value k is greater than the current value k.sub.M; while the blanking interval T.sub.BLANK has not elapsed, the circuit 400 updates the value k.sub.QR (i.e., stores the value k or increases the value k.sub.QR); and the comparison circuit 426 sets the signal BLANK to the second logic level (e.g., high), when the time interval T.sub.BLANK has elapsed and the values k and k.sub.M correspond.

(73) Conversely, the value k.sub.M (stored in a counter or only a memory 422) should be reset as a function of the value k.sub.QR.

(74) In the embodiment considered, the circuit 400 has thus associated a comparison circuit 406, which is configured to implement the comparison operation at step 1020 of FIG. 7.

(75) Specifically, this comparison circuit 406 is configured to compare the value k.sub.QR with the value k.sub.M or k. More specifically, in the embodiment considered the comparison circuit 406 is configured to compare the value k.sub.QR with the value k, because this avoids any additional combinational or sequential logic circuit, because these signals increase during the blanking interval T.sub.BLANK in parallel and only when the blanking interval T.sub.BLANK ends, the value k may further increase. However, the comparison may also be started only when the blanking interval T.sub.BLANK elapses, e.g., by starting the comparison in response to the signal BLANK_T.

(76) In various embodiments, the comparison circuit 406 provides at output one or more comparison signals indicating whether the condition “A”, “B” or “C” (see description of step 1020) is met. For example, in the embodiment considered, two signals S_C and F_C are used, which are set to: F_C=“1” and S_C=“1” for condition A, e.g., for k.sub.QR<k.sub.M−2; F_C=“0” and S_C=“1” for condition B, e.g., for k.sub.QR=k.sub.M−2; and F_C=“0” and S_C=“0” for condition C, e.g., for k.sub.QR>k.sub.M−2.

(77) In the embodiment considered, the signals F_C and S_C are elaborated by a circuit 410 configured to selectively reset the memory or counter 422.

(78) Specifically, in the embodiment considered, the circuit 410 comprises a first sub-circuit 412 configured to implement steps 1028 and 1030, and a second sub-circuit 414 configured to implement steps 1022 and 1024.

(79) For example, FIG. 9 shows an embodiment of the circuit 412.

(80) In the embodiment considered, the circuit 412 is implemented with an automatic reload counter circuit, which is increased in response to the signal S_C. Specifically, in the embodiment considered, the circuit 412 comprises a counter 4126 configured to: increase an internal count value in response to the signal S_C; generate/set a trigger signal S_R when the internal count value reaches a given threshold, e.g., 256 or 512; and

(81) reset the internal count value when the trigger signal S_R is set.

(82) In various embodiments, the circuit 4126 may have associated an additional reset circuit configured to generate an additional reset signal RS for the counter 4126 when the signal S_C is low when the switch SW is turned on. For example, in the embodiment considered, the reset circuit comprises: a latch 4120, such as a set-reset latch, configured to set its output Q to high when the signal S_C is set; this latch 4120 may be reset once during each switching cycle, e.g., in response to the signal S_OFF; and a logic gate 4122, such as a AND gate, configured to set the reset signal RS when the output Q of the latch 4120 is low when the switch is closed, e.g., when the output Q of the latch 4120 is low and the signal S_ON is high.

(83) In the embodiment considered, the reset terminal of the counter 4126 may thus receive, e.g., via a logic OR gate 4124, the trigger signal S_R and the reset signal RS.

(84) Generally, the circuit 414 generates a trigger signal F_R in response to the signal F_C. In various embodiments the signal F_R may correspond to the signal F_C.

(85) Conversely, FIG. 10 shows an embodiment of the circuit 414, which essentially corresponds to the circuit 412.

(86) Specifically, in the embodiment considered, also the circuit 414 is implemented with an automatic reload counter circuit, which is increased in response to the signal F_C. Specifically, in the embodiment considered, the circuit 414 comprises a counter 4146 configured to: increase an internal count value in response to the signal F_C; generate/set the trigger signal F_R when the internal count value reaches a given threshold, e.g., 4 or 8; and reset the internal count value when the trigger signal F_R is set.

(87) In various embodiments, also the circuit 4146 may have associated an additional reset circuit configured to generate an additional reset signal RF for the counter 4146 when the signal F_C is low when the switch SW is turned on. For example, in the embodiment considered, the reset circuit comprises: a latch 4140, such as a set-reset latch, configured to set its output Q to high when the signal F_C is set; this latch 4140 may be reset once during each switching cycle, e.g., in response to the signal S_OFF; and a logic gate 4142, such as a AND gate, configured to set the reset signal RF when the output Q of the latch 4140 is low when the switch SW is closed, e.g., when the output Q of the latch 4140 is low and the signal S_ON is high.

(88) In the embodiment considered, the reset terminal of the counter 4146 may thus receive, e.g., via a logic OR gate 4144 the trigger signal F_R and the reset signal RF.

(89) Accordingly, in the embodiment considered, the memory/counter 422 is reset when the signal S_R is set, e.g., when the signal S_C goes to high during given first number of switching cycles, or when the signal F_R is set, e.g., when the signal F_C goes to high during given second number of switching cycles, where the first number is greater than the second number.

(90) For example, for this purpose a combinational logic circuit 420, such as a OR gate, may generate the reset signal for the memory/counter 422 by combining the signals S_R and F_R.

(91) In various embodiments, the circuit 410 may comprises further sub-circuits, which may generate a reset of the memory/counter 422.

(92) For example, as described in the foregoing, the memory/counter 422 is not reset when the circuit operates in condition C, i.e., k.sub.QR≤k.sub.M−n.sub.L. While this behavior is desired when the control circuit 410a has to avoid jumps between the valleys, this verification operation also blocks a reset of the value k.sub.M, when the switch-off duration increases and the converter could be switched with the first valley, because the above described operation cannot reset the value k.sub.M when k.sub.M≤n.sub.L, e.g., when k.sub.M=1.

(93) Thus, in various embodiments, the circuit 410 may comprise a sub-circuit configured to detect this condition.

(94) For example, the inventors have observed, that this condition may be detected because the converter does not operate with the “optimal” drive conditions, e.g., because: when the feedback signal FB is an error signal, this signal may increase; and/or the peak value of the signal CS may increase.

(95) Accordingly, in various embodiments, the circuit 410 may comprise a feedback-tracking circuit 418 configured to monitor the variation of the feedback signal FB.

(96) For example, FIG. 11 shows a possible embodiment of the circuit 416.

(97) In the embodiment considered, the circuit 416 is configured to sampled at constant rate F.sub.SH the feedback signal FB, and the sampled feedback signal FBs is compared with the current feedback signal FB.

(98) For this purpose, the circuit 416 may comprise: a trigger generator 4186, e.g., implemented with a counter, configured to generate a trigger signal at the rate F.sub.SH; and a sample and hold circuit 4180 configured to sample the feedback signal FB in response to the trigger signal provided by the trigger generator 4186.

(99) In the embodiment considered, the feedback signal FB and the sampled feedback signal FBs are provided to a comparator 4184. Specifically, in the embodiment considered, the signals are not compared directly, but an offset V.sub.fb_h is added at an adder 4182 to the sample feedback value FBs, i.e., the comparator 4184 generates/sets a signal FB_R when FB>FBs+V.sub.fb_h.

(100) Accordingly, in the embodiment considered, the circuit 418 is configured to periodical store the feedback signal FB and generate the trigger signal FB_R when the feedback signal increases more than V.sub.fb_h.

(101) In various embodiments, in this case, the sample-and-hold circuit 4180 may store also immediately the feedback signal FB (as shown via an OR gate 4188) and/or restart the trigger generator 4186.

(102) Accordingly, the combinational logic circuit 420 (FIG. 8) may also receive at input the signal FB_R, i.e., reset the memory/counter 422 in response to the signal FB_R.

(103) Conversely, FIG. 12 shows an embodiment of a circuit 416 configured to monitor the peak value of the signal CS.

(104) In the embodiment considered, the circuit 416 is implemented with an automatic reload counter circuit, which is increased when the signal CS exceeds a given threshold value. For example, in the embodiment considered, the circuit 416 comprises a counter 4166 configured to: increase an internal count value in response to the signal OCP provided by the comparator 2114 (see FIG. 4), insofar as this comparator already compares the signal CS with the threshold OTH; generate/set the trigger signal OCP_R when the internal count value reaches a given threshold, e.g., 4 or 8; and reset the internal count value when the trigger signal OCP_R is set.

(105) In various embodiments, also the circuit 4146 may have associated an additional reset circuit configured to generate an additional reset signal ROCP for the counter 4166, which is used to disable the counter 4146 when the feedback signal FB is smaller than a given threshold value.

(106) For example, in the embodiment considered, the reset circuit comprises: a comparator 4160 configured to determine whether the feedback signal FB is greater that a threshold value V.sub.FB_EN, such as 2.5V, preferably a comparator with a given hysteresis V.sub.FB_EN_HYST, such as 100 mV; and a latch 4162, such as a set-reset latch, configured to set its output Q (providing the signal ROCP) to high when the signal OCP_R is set, and wherein the latch 4140 is reset in response to the signal at the output of the comparator 4160.

(107) In the embodiment considered, the reset terminal of the counter 4166 may thus receive, e.g., via a logic OR gate 4164 the trigger signal OCP_R and the reset signal ROCP.

(108) Thus, when using the signal at the output Q of the latch 4162 as reset signal ROCP, this signal ROCP will be set to high in response to the first trigger in the signal OCP_R, and then will remain set to high until the signal FB is greater than the threshold value V.sub.FB_EN. Thus, when the signal FB is small, the signal ROCP will remain high and the counter 4166 remains reset, thereby inhibiting the generation of further triggers in the signal OCP_R.

(109) Accordingly, the combinational logic circuit 420 (FIG. 8) may also receive at input the signal OCP_R, i.e., reset the memory/counter 422 in response to the signal OCP_R.

(110) Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure, as defined by the ensuing claims.

(111) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.