ZERO CURRENT DETECTION DEVICE

Abstract

A zero current detection device is proposed. The device may include a scaling circuit unit configured to generate a first voltage which is scaled from a target voltage. The device may also include a mirroring circuit unit configured to generate a mirroring current when the first voltage is higher than or equal to a reference voltage. The device may further include a comparator circuit unit configured to compare the target voltage and a ground voltage when the mirroring current is input.

Claims

1. A zero current detection device comprising: a scaling circuit configured to generate a first voltage which is scaled from a target voltage; a mirroring circuit configured to generate a mirroring current when the first voltage is higher than or equal to a reference voltage; and a comparator circuit configured to compare the target voltage and a ground voltage when the mirroring current is input.

2. The zero current detection device of claim 1, further comprising a clock signal generation circuit configured to delay a result of comparing the target voltage and the ground voltage to generate a clock signal for an operation of the comparator circuit unit.

3. The zero current detection device of claim 1, wherein the first voltage has a phase identical to that of the target voltage, and has a maximum magnitude greater than the reference voltage by a preset offset value.

4. The zero current detection device of claim 3, wherein the offset value is configured to cause a magnitude of the first voltage to be greater than or equal to a threshold gate voltage for operating the mirroring circuit when a magnitude of the target voltage is greater than or equal to a preset magnitude.

5. The zero current detection device of claim 3, wherein the scaling circuit is configured to receive a second voltage with a phase that is 90 ahead of the phase of the target voltage and a maximum magnitude that is smaller than the maximum magnitude of the target voltage, and output the first voltage by adjusting the phase and magnitude of the second voltage.

6. The zero current detection device of claim 5, wherein the target voltage is a voltage of a load terminal of the wireless power receiving circuit.

7. The zero current detection device of claim 6, wherein the second voltage is a voltage of a capacitor of the wireless power receiving circuit.

8. A zero current detection device comprising: a comparison signal generation circuit including: a first capacitor having a first terminal connected to a reference voltage, a first switch connected in parallel with the first capacitor, a second switch having one terminal connected to a second terminal of the first capacitor, a D flip-flop configured to delay a clock signal to output a control signal controlling operations of the first switch and the second switch, and an inverter configured to invert a voltage applied to the second terminal of the first capacitor and output the voltage; and a comparator circuit configured to compare a target voltage and a ground voltage based on an output of the comparison signal generation circuit.

9. The zero current detection device of claim 8, further comprising: a counter circuit configured to count a number of times the target voltage is greater than the ground voltage or a number of times the target voltage is smaller than the ground voltage based on the output of the comparator circuit; and a current output digital-to-analog converter connected to the second terminal of the first capacitor, wherein the current output digital-to-analog converter is configured to operate based on the counting result.

10. The zero current detection device of claim 9, wherein the first switch and the second switch are turned on in response to the delayed clock signal being input, wherein the comparison signal generation circuit is configured to set the voltage at the second terminal of the first capacitor to be lowered in response to the first switch and the second switch being turned on, and wherein the inverter is configured to output the reference voltage in response to the voltage at the second terminal of the first capacitor being lower than or equal to a threshold gate voltage.

11. The zero current detection device of claim 10, wherein in response to the inverter outputting the reference voltage, the comparator circuit unit is configured to compare the target voltage and the ground voltage.

12. The zero current detection device of claim 10, wherein the current output digital-to-analog converter is configured to control a rate at which the voltage at the second terminal of the first capacitor is lowered according to the counting result of the counter circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a diagram for describing a wireless power system including a wireless power transmitting device and a wireless power receiving device according to an embodiment of the present disclosure.

[0027] FIG. 2A is a diagram for describing an equivalent circuit of a resonance mode in which a wireless power receiving device according to an embodiment of the present disclosure.

[0028] FIG. 2B is a diagram for describing an equivalent circuit of a charging mode in which a wireless power receiving device according to an embodiment of the present disclosure.

[0029] FIG. 3 is a diagram illustrating the configuration of a switching control device that controls the switch of the wireless power receiving device illustrated in FIG. 1.

[0030] FIG. 4 is a circuit diagram of the zero current detection device according to an embodiment of the present disclosure.

[0031] FIG. 5 is a diagram for describing the operation of the zero current detection device illustrated in FIG. 4.

[0032] FIG. 6 is a circuit diagram of a zero current detection device according to another embodiment of the present disclosure.

[0033] FIG. 7 is a diagram for describing the operation of the zero current detection circuit illustrated in FIG. 6.

[0034] FIG. 8 is a circuit diagram of the -base voltage regulation controller according to the embodiment of the present disclosure.

[0035] FIG. 9 is a diagram for explaining the operation of the -base voltage regulation controller illustrated in FIG. 8.

DETAILED DESCRIPTION

[0036] Most currently commercialized wireless power technologies only allow limited wireless charging when a wireless charging pad and a charging device are in contact with each other, which may cause inconvenience to users in using wireless charging.

[0037] In addition, a zero current detector is a technology widely used in analog circuit design, such as a switching operation of a wireless power receiving device. In order to accurately control the operation of the circuit, the zero current needs to be accurately detected by the zero current detector. When the zero current detector does not properly detect an actual zero current time, a reverse current may flow, which may be a major factor that reduces performance of a circuit system, such as affecting an operation of the circuit system.

[0038] In addition, the zero current detector consumes a lot of power when detecting the zero current of a high frequency signal. For example, when detecting the zero current of a 10 MHz frequency signal, the zero current should be detected by sampling a signal with a clock of a frequency higher than 10 MHz, which causes the problem of increasing the amount of power consumed for the zero current detection, heat generation, etc.

[0039] Various advantages and features of the present disclosure and methods accomplishing them will become apparent from the following description of embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to exemplary embodiments to be described below, but may be implemented in various different forms, these exemplary embodiments will be provided only in order to make the present disclosure complete and allow those skilled in the art to completely recognize the scope of the present disclosure, and the present disclosure will be defined by the scope of the claims.

[0040] In describing embodiments of the present disclosure, detailed descriptions of well-known functions or configurations will be omitted unless they are actually necessary in describing embodiments of the present disclosure. Further, the following terminologies are defined in consideration of the functions in the embodiments of the present disclosure and may be construed in different ways by users, an intention of operators, or conventions. Therefore, the definitions thereof should be construed based on the contents throughout the specification.

[0041] A term unit, or/er, or the like, described below means a unit of processing at least one function or operation and may be implemented by hardware or software or a combination of hardware and software.

[0042] FIGS. 1 and 2 are diagrams for describing a wireless power system according to an embodiment of the present disclosure.

[0043] FIG. 1 illustrates a circuit diagram of a wireless power system 1000 including a wireless power transmitting device 1100 and a wireless power receiving device 1200, FIG. 2A illustrates an equivalent circuit of a resonance mode in which the wireless power receiving device 1200 receives power, and FIG. 2B illustrates an equivalent circuit of a charging mode in which the wireless power receiving device 1200 supplies power to a load.

[0044] In an embodiment, the wireless power system 1000 may operate in a resonance mode at a frequency of 13.56 MHz.

[0045] When a switch S.sub.P in FIG. 1 is open and a switch S.sub.N is shorted, as illustrated in FIG. 2A, the wireless power receiving device 1200 allows energy received in a loop formed by an LC tank and a switch S.sub.N designed to have a high Q-factor to resonate and flow in the form of current. In addition, at a load terminal of the wireless power receiving device 1200, power charged in a capacitor C.sub.L of a load terminal is supplied to the load, so the voltage of the capacitor C.sub.L gradually decreases.

[0046] In one embodiment, the switch S.sub.P may be configured of a single PMOS switch.

[0047] In one embodiment, the switch S.sub.N may be configured of a plurality of NMOS switches.

[0048] In addition, when the voltage of the load terminal, that is, the voltage of the capacitor C.sub.L, becomes low enough to not supply sufficient power to the load, the wireless power receiving device 1200 short-circuits the switch S.sub.P and opens the switch S.sub.N, and thus, operates in the charging mode in which the energy stored in the LC tank supplies power to the load terminal.

[0049] In addition, the energy E.sub.Rx-RES stored in the LC tank of the wireless power receiving device 1200 may be expressed as Equation 1 below.

[00001]$\begin{array}{cc}{E}_{\mathrm{RX}-\mathrm{RES}}=\frac{1}{2}{C_{RX}\left(M\frac{V_{\mathrm{TX}}}{R_1+\frac{{}^2{M}^2}{R_2+R_N}}{Q}_{2-\mathrm{RES}}\right)}^2& \left[\mathrm{Equation}1\right]\end{array}$

[0050] In this case, the quality factor (Q factor) Q.sub.2-RES is L.sub.RX/(R.sub.2+R.sub.N) and R.sub.N represents the resistance of the switch S.sub.N.

[0051] In addition, Equation 1 may be approximated as Equation 2 when condition R.sub.1(R.sub.2+R.sub.N)<<.sup.2M.sup.2 is satisfied.

[00002]$\begin{array}{cc}{E}_{\mathrm{RX}-\mathrm{RES}}\frac{1}{2}{C_{RX}\left(\frac{V_{TX}\left(R_2+R_N\right)}{M}{Q}_{2-\mathrm{RES}}\right)}^2& \left[\mathrm{Equation}2\right]\end{array}$

[0052] That is, in the wireless power system 1000, as a distance between the wireless power receiving device 1200 and the wireless power transmitting device 1100 increases, a coupling coefficient M decreases, and the E.sub.RX-RES stored in the LC tank of the wireless power receiving device 1200 increases.

[0053] Therefore, for the efficiency of the wireless power system 1000 and the user's convenience, even when the distance between the wireless power transmitting device 1100 and the wireless power receiving device 1200 changes, a technology that may supply constant energy is required. The wireless power receiving device 1200 of the present disclosure solves this problem by controlling an operation timing of the switch S.sub.P and switch S.sub.N. To this end, the wireless power receiving device 1200 may include a zero current detection device that detects the time when the current becomes zero and a switching control device (hereinafter referred to as -base voltage regulation controller) that generates signals to control the operations of the switch S.sub.P and the switch S.sub.N based on the zero current detection results.

[0054] Hereinafter, with reference to FIGS. 3 to 9, the zero current detection device and the -base voltage regulation controller will be described in detail.

[0055] FIG. 3 is a diagram illustrating the configuration of a switching control device that controls the switch of the wireless power receiving device illustrated in FIG. 1.

[0056] Referring to FIG. 3, a switching control device 3000 detects the time when the current of the wireless power receiving device 1200 changes from a negative value to a positive value and the time when the current of the wireless power receiving device 1200 changes from the positive value to the negative value to turn off the switch S.sub.P and the switch S.sub.N, and thus, may operate in the resonance mode or the charging mode. To this end, the switching control device 3000 may include an analog block 3100, a switch control signal generation unit 3200, and a switch driving unit (3300).

[0057] The analog block 3100 may generate an analog signal for the switching control device to operate.

[0058] In one embodiment, the analog block 3100 includes a linear low drop out regulator (LDO) connected to a diode, an internal reference generator, and a power-on-reset (POR), each of which may generate VDD, a reference voltage, and a start signal, respectively. Here, VDD is a voltage of 1.2V, which is a voltage for driving the switching control device.

[0059] The switch control signal generation unit 3200 may monitor the voltage of the load terminal to generate a timing signal for the turning on or off operations of the switch S.sub.P and the switch S.sub.N so that the wireless power receiving device 1200 may operate from resonance mode to the charging mode or vice versa.

[0060] In one embodiment, the switch control signal generation unit 3200 may include an attenuator that scales the magnitude of the voltage V.sub.C applied to the capacitor C.sub.RX of the wireless power receiving device 1200, a signal level shifter that shifts the phase of the scaled voltage V.sub.C, the zero current detection device, the -based voltage regulation controller, and the timing signal generator.

[0061] Here, the zero current detection device may include a first zero current detection device that detects the time when the current of the wireless power receiving device 1200 changes from a negative value to a positive value and a second zero current detection device that detects the time when the current of the wireless power receiving device 1200 changes from the positive value to the negative value, and a detailed description of this will be described below with reference to FIGS. 4 to 7.

[0062] In addition, the -based voltage regulation controller determines whether the wireless power receiving device 1200 operates from the resonance mode to the charging mode or vice versa, based on the detection result of the zero current detection device, and a detailed description thereof will be described below with reference to FIGS. 8 and 9.

[0063] The switch driving unit 3300 may turn on or off the switch S.sub.P and the switch S.sub.N according to the timing signal.

[0064] FIG. 4 is a circuit diagram of the zero current detection device according to an embodiment of the present disclosure.

[0065] Referring to FIG. 4, the zero current detection device according to the embodiment of the present disclosure is for detecting the time when the current changes from the negative value to the positive value, and may include a wireless power receiving circuit unit 4100, a scaling circuit unit 4200, a mirroring circuit unit 4300, a comparator circuit unit 4400, and a clock signal generation circuit unit 4500.

[0066] In one embodiment, the wireless power receiving circuit unit 4100 may include an inductor L.sub.RX and a capacitor C.sub.RX connected in series to each other of a general wireless power receiving circuit. One terminal of the inductor L.sub.RX is connected to the load, and one terminal of the capacitor C.sub.RX is connected to a ground. Therefore, one terminal of the inductor L.sub.RX becomes a load voltage V.sub.X applied to the load, and when the wireless power receiving circuit operates in a resonance state, the voltage V.sub.C applied to the capacitor C.sub.RX may have a phase that is 90 ahead of the phase of the load voltage V.sub.X and a maximum magnitude that is smaller than the maximum magnitude of the load voltage V.sub.X.

[0067] In other words, when the voltage of the load voltage V.sub.X becomes zero, the current flowing in the wireless power receiving circuit becomes zero, so detecting the time when the load voltage V.sub.X (hereinafter referred to as the target voltage) becomes zero, that is, the time when the current flowing in the wireless power receiving circuit becomes zero, is described as an example.

[0068] The scaling circuit unit 4200 may generate a first voltage V.sub.C which is scaled from a target voltage. Specifically, the scale circuit unit may generate the first voltage V.sub.C by shifting the phase of the voltage V.sub.C (hereinafter, the second voltage) applied to the capacitor C.sub.RX to have the phase identical to that of the target voltage and by scaling the magnitude to be greater than the reference voltage.

[0069] In one embodiment, the scaling circuit unit 4200 may include a plurality of capacitors connected in series to shift the phase of the second voltage.

[0070] In one embodiment, the scaling circuit unit 4200 may include a plurality of resistors connected in series to scale the magnitude of the second voltage.

[0071] In one embodiment, the first voltage V.sub.C may have the phase identical to that of the target voltage and have a maximum magnitude greater than the reference voltage by a preset offset value. Here, the offset value may be a value that causes the magnitude of the first voltage V.sub.C to be greater than or equal to the threshold gate voltage for operating the mirroring circuit unit 4300 when the magnitude of the target voltage is greater than or equal to a preset magnitude (e.g., 80% of the maximum magnitude of the target voltage). Accordingly, the mirroring circuit unit 4300 operates when the target voltage approaches the peak.

[0072] The mirroring circuit unit 4300 may generate a mirroring current I for the comparator circuit unit 4400 to operate based on the first voltage V.sub.C.

[0073] In one embodiment, the mirroring circuit unit 4300 may generate the mirroring current I when the first voltage V.sub.C is greater than or equal to the threshold gate voltage for driving a MOSFET M of the mirroring circuit unit 4300.

[0074] In one embodiment, the MOSFET M may be an N-MOS transistor.

[0075] The comparator circuit unit 4400 may compare the magnitude of the ground voltage and the target voltage according to the mirroring current I.

[0076] In one embodiment, the comparator circuit unit 4400 may further include a switch in a path through which the mirroring current I of the mirroring circuit unit 4300 is input. Here, the output of the clock signal generation circuit unit 4500 may be input to the switch. Accordingly, the comparator circuit unit 4400 receives the mirroring current I according to the output of the clock signal generation circuit unit 4500, thereby changing the timing when the magnitudes of the ground voltage and the target voltage are compared.

[0077] In one embodiment, the comparator circuit unit 4400 may be a dynamic latch comparator.

[0078] The clock signal generation circuit unit 4500 may generate a clock signal for operating the comparator circuit unit 4400 based on the result of comparing the magnitudes of the ground voltage and the target voltage.

[0079] In one embodiment, the clock signal may be delayed by a delay circuit t.sub.d and input to the switch of the comparator circuit unit 4400. That is, in the present disclosure, the clock signal for operating the comparator circuit unit 4400 is delayed and fed back by the clock signal generation circuit unit 4500.

[0080] In one embodiment, the zero current detector of FIG. 1 may extract the time when the current of the circuit subject to the zero current detection changes from a negative number to a positive number.

[0081] FIG. 5 is a diagram for describing the operation of the zero current detection device illustrated in FIG. 4.

[0082] FIG. 5 illustrates signals output from each component of the zero current detection device illustrated in FIG. 4.

[0083] The following description will be made on the assumption that the wireless power receiving circuit, which is the target of the zero current detection, is operating in the resonance state.

[0084] Since a phase of the second voltage V.sub.C is 90 ahead of the phase of the target voltage V.sub.X, and a maximum magnitude of the second voltage V.sub.C is smaller than that of the target voltage V.sub.X, the phase of the second voltage V.sub.C is adjusted to be 90 slower and the magnitude thereof is adjusted to be greater than the reference voltage, so the second voltage becomes the first voltage V.sub.C, which has the phase identical to that of the load voltage V.sub.X and the maximum magnitude thereof is greater than the reference voltage. The first voltage V.sub.C is applied to a gate terminal of the MOSFET M of the mirroring circuit unit 4300. The mirroring current I is generated in the mirroring circuit unit 4300 when the first voltage V.sub.C becomes greater than or equal to a threshold gate voltage V.sub.TH of the MOSFET M. The comparator circuit may compare the magnitudes of the ground voltage and the target voltage V.sub.X when the mirroring current I is input. The clock signal generator circuit unit may delay the result of comparing the ground voltage of the comparator circuit and the target voltage V.sub.X to generate an operation signal for the switch of the comparator circuit.

[0085] That is, when the first voltage V.sub.C becomes greater than or equal to the threshold gate voltage V.sub.TH (operation range), the comparison is performed between the ground voltage of the comparator circuit and the target voltage V.sub.X. In this case, the result of comparing the ground voltage and the target voltage V.sub.X is output as OUTN and OUTP signals. Here, OUTN indicates a case where the target voltage V.sub.X is lower than the ground voltage, and OUTP indicates a case where the target voltage V.sub.X is greater than the ground voltage. FIG. 2 illustrates the process in which the target voltage V.sub.X changes from a negative voltage to a positive voltage, so a time of a first peak with a non-zero value at OUTP means the time when the target voltage V.sub.X changes from a negative number to a positive number. CLK.sub.ZCS has a peak from the time when the target voltage V.sub.X changes from a negative number to a positive number.

[0086] In addition, when the first voltage V.sub.C is greater than or equal to the threshold gate voltage V.sub.TH (operation range), the result of comparing the target voltage V.sub.X and the ground voltage is delayed, so a time interval input to the comparator circuit unit 4400 becomes shorter as the first voltage V.sub.C approaches the maximum value and becomes longer as it decreases after the maximum value. That is, since the comparison operation interval of the comparator circuit unit 4400 becomes very fast at the point where the target voltage V.sub.X, which is the time when the first voltage V.sub.C reaches its maximum value, becomes 0, it becomes possible to accurately detect the zero current point. When the zero current detection target circuit of the present disclosure operates at a frequency of 13.56 MHz, the frequency of the clock signal generated in the comparator circuit unit 4400 may be up to 1.25 GHz at the point when the target voltage V.sub.X of the comparator is 0.

[0087] FIG. 6 is a circuit diagram of a zero current detection device according to another embodiment of the present disclosure.

[0088] Referring to FIG. 6, the zero current detection device according to another embodiment of the present disclosure is for detecting the time when the current changes from a positive value to a negative value, and may include a comparison signal generation circuit unit 6100, a comparator circuit unit 6200, a counter circuit unit 6300, and a current output digital-to-analog converter 6400 (IDAC).

[0089] The comparison signal generation circuit unit 6100 may include a first capacitor C.sub.INT that is connected to the reference voltage VDD, a first switch that is connected in parallel with the first capacitor C.sub.INT, a second switch that is connected in series with the first capacitor C.sub.INT and the first switch connected in parallel, a D flip-flop that outputs a signal controlling the operations of the first switch and the second switch, and an inverter that inverts a voltage between the first capacitor and the first switch and outputs the inverted voltage.

[0090] In one embodiment, when the first switch is turned off, that is, in an open state, the same voltage as the reference voltage is applied to the first capacitor C.sub.INT.

[0091] In one embodiment, the first switch may be an N-MOS transistor and the second switch may be a P-MOS transistor. Accordingly, when the first switch is turned on (or off), the second switch may be turned off (or on).

[0092] In one embodiment, the inverter may output a ground voltage when the voltage between the first capacitor and the first switch exceeds the threshold gate voltage, and output a reference voltage when the voltage between the first capacitor and the first switch is less than or equal to the threshold gate voltage.

[0093] In one embodiment, the D flip-flop may delay and output the reference voltage VDD according to the clock signal. In this case, the delayed output signal may be applied to the gate terminals of the first switch and the second switch to control the switching operation.

[0094] In one embodiment, the D flip-flop may be reset by inputting the reference voltage to a reset terminal when the reference voltage is output from the inverter.

[0095] In one embodiment, the reference voltage output from the inverter may be a clock signal (comparison signal) for the operation of the comparator circuit unit 6200.

[0096] The comparator circuit unit 6200 may compare the magnitudes of the target voltage and the ground voltage according to the output of the comparison signal generation circuit unit.

[0097] In one embodiment, the comparator circuit unit 6200 may be an inverting comparator.

[0098] The counter circuit unit 6300 may collect the result of comparing the target voltage and the ground voltage in the comparator circuit unit 6200.

[0099] In one embodiment, the counter circuit unit 6300 may count the number of times the target voltage is greater than the ground voltage and the number of times the target voltage is smaller than the ground voltage.

[0100] In one embodiment, the counter circuit unit 6300 may be the digital DE-based voltage regulation controller.

[0101] The current output digital-to-analog converter 6400 may control the amount of current flowing in the first switch based on the counting result of the counter circuit unit 6300.

[0102] In one embodiment, the power output digital-to-analog converter may control the amount of current flowing through the first switch to control a rate at which the voltage between the first capacitor and the first switch decreases.

[0103] In one embodiment, the zero current detector of FIG. 2 may extract the time when the current of the circuit subject to the zero current detection changes from a negative number to a positive number.

[0104] FIG. 7 is a diagram for describing the operation of the zero current detection circuit illustrated in FIG. 6.

[0105] Referring to FIG. 7, the reference voltage is applied to a node V.sub.INT, and a clock signal CLK.sub.RST applied to the D flip-flop is a 13.56 MHz signal, but may be input as a distorted signal due to a small jitter. When the signal CLK.sub.Delay delayed by the D flip-flop becomes logic high, the voltage of node V.sub.INT gradually decreases from the reference voltage toward the threshold gate voltage due to the current flow of the current output digital-to-analog converter 6400. Since the voltage of the node V.sub.INT is a signal applied to the inverter, when the voltage of the node V.sub.INT of the inverter is lower than or equal to the threshold gate voltage, the output of the inverter changes from the ground voltage to the reference voltage. In this case, the output of the inverter is again applied to the reset terminal of the D flip-flop, and the D flip-flop is reset, thereby setting CLK.sub.Delay to 0 and outputting the CLK.sub.Falling signal. When the CLK.sub.Falling signal is output, the comparator circuit unit 6200 compares the target voltage and the ground voltage to determine whether the CLK.sub.Falling signal is faster or slower than the point at which it passes the zero current, so the rate at which the voltage of the node V.sub.INT is lowered may be adjusted using the counter circuit unit 6300 and the current output digital-to-analog converter 6400. Therefore, by adjusting the rate at which the voltage of the node V.sub.INT is lowered and matching the time when the CLK.sub.Falling signal passes the zero current, it is possible to detect the time when the zero current is detected.

[0106] FIG. 8 is a circuit diagram of the -base voltage regulation controller according to the embodiment of the present disclosure.

[0107] Referring to FIG. 8, the -base voltage regulation controller monitors the voltage at the load terminal of the wireless power receiving device 1200 operating at 13.56 MHz, and when the voltage at the load terminal becomes greater (or lower) than the reference load voltage, by controlling the operation of the switch S.sub.P and the switch S.sub.N, the time of operating in charging mode until the voltage at the load terminal reaches the reference load voltage may decrease (or increase).

[0108] The -base voltage regulation controller according to the embodiment of the present disclosure may include a comparator circuit unit that compares the measurement voltage V.sub.SENSE with the reference voltage V.sub.REF according to the clock signal CLK.sub.RST, an up/down counter (UP/DN counter) that counts the comparison result between the measurement voltage V.sub.SENSE and the reference voltage V.sub.REF, a delay signal generator (Delay gen) that generates the delay signal CLK.sub.BB based on the counting result, a timing signal generation unit that generates a timing signal SW to control the switch by delaying the zero current detection signal CLK.sub.ZCS according to the delay signal CLK.sub.BB, and a non-overlapping clock signal generator that generates a non-overlapping clock signal to operate the switch S.sub.P and the switch S.sub.N in different states (e.g., when one side is turned on and the other side is turned off).

[0109] In one embodiment, the comparator circuit unit may be a dynamic comparator that operates according to the clock signal CLK.sub.RST.

[0110] In one embodiment, the measured voltage V.sub.SENSE may be the voltage acquired by scaling the voltage of the load terminal of the wireless power receiving device 1200 using the voltage divider.

[0111] In one embodiment, the up/down counter (UP/DN Counter) may count and store the number of times the measurement voltage V.sub.SENSE is greater or less than the reference voltage V.sub.REF.

[0112] In one embodiment, the delayed signal generator may include a capacitor C.sub.INT having one terminal connected to VDD, a transistor connected in parallel with the capacitor C.sub.INT, and the current output digital-to-analog converter (IDAC) having a transistor connected in parallel with the capacitor C.sub.INT, and a current output digital-to-analog converter (IDAC) connected between the other terminal of the capacitor C.sub.INT and a battery. The current output digital-to-analog converter (IDAC) may control the rate at which the capacitor C.sub.INT is discharged by adjusting the amount of current flowing in ground based on the number stored in the up-down counter. In this case, the voltage at the other terminal of the capacitor C.sub.INT is inverted and becomes the delay signal CLK.sub.BB input to the timing signal generation unit. In this case, the delay signal CLK.sub.BB is inverted by the inverter and input to the gate terminal of the transistor connected in parallel with the capacitor C.sub.INT.

[0113] In one embodiment, the timing signal generation unit may include a first D flip-flop, a second D flip-flop, and a third D flip-flop. The first D flip-flop receives the VDD as input to the data terminal, and outputs a signal EN.sub.BB that delays VDD using the delay signal CLK.sub.BB as a clock signal. The second D flip-flop receives the signal EN.sub.BB as input to the data terminal, delays the signal EN.sub.BB using the signal inverted by the zero current detection signal CLK.sub.ZCS by the inverter as the clock signal, and outputs the first signal. In this case, the first signal, which is the output of the second D flip-flop, is inverted by the inverter to become a timing signal for controlling the switch, and is transmitted to the non-overlapping clock signal generator. The third D flip-flop receives the first signal as input to the data terminal and outputs a second signal in which the first signal is delayed using the zero current detection signal CLKZCS as the clock signal. In this case, the second signal may be inverted by the inverter and input to the reset terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop, and the output of the first D flip-flop, the second D flip-flop, and the third D flip-flop may be reset.

[0114] FIG. 9 is a diagram for explaining the operation of the -base voltage regulation controller illustrated in FIG. 8.

[0115] As illustrated in FIG. 8, the -base voltage regulation controller may measure the voltage V.sub.SENSE to which the load voltage V.sub.L is scaled using a voltage divider. The -based voltage regulation controller may compare the voltage V.sub.SENSE and the reference voltage V.sub.REF using the dynamic comparator that operates according to the clock signal CLK.sub.RST. The -based voltage regulation controller may store the results of comparing the voltage V.sub.SENSE and the reference voltage V.sub.REF as the digital information using the up/down counter (UP/DN counter). The -based voltage regulation controller may control the current of the current output digital-to-analog converter (IDAC) based on the information stored in the up-down counter, thereby controlling the rate at which the capacitor C.sub.INT of the delay signal generator (Delay gen) is discharged. The -based voltage regulation controller may generate a delay signal CLK.sub.BB by controlling the rate at which the capacitor C.sub.INT is discharged. When the delay signal CLK.sub.BB is generated, the -based voltage regulation controller transmits the zero current detection signal CLK.sub.ZCS generated by the zero current detection device to the non-overlapping clock signal generator, thereby generating a switching signal SW.sub.P to control the operation of the switch S.sub.P and a switching signal SW.sub.N to control the operation of switch S.sub.N.

[0116] Combinations of steps in each flowchart attached to the present disclosure may be executed by computer program instructions. Since the computer program instructions can be mounted on a processor of a general-purpose computer, a special purpose computer, or other programmable data processing equipment, the instructions executed by the processor of the computer or other programmable data processing equipment create a means for performing the functions described in each step of the flowchart. The computer program instructions can also be stored on a computer-usable or computer-readable storage medium which can be directed to a computer or other programmable data processing equipment to implement a function in a specific manner. Accordingly, the instructions stored on the computer-usable or computer-readable recording medium can also produce an article of manufacture containing an instruction means which performs the functions described in each step of the flowchart. The computer program instructions can also be mounted on a computer or other programmable data processing equipment. Accordingly, a series of operational steps are performed on a computer or other programmable data processing equipment to create a computer-executable process, and it is also possible for instructions to perform a computer or other programmable data processing equipment to provide steps for performing the functions described in each step of the flowchart.

[0117] In addition, each step may represent a module, a segment, or a portion of codes which contains one or more executable instructions for executing the specified logical function(s). It should also be noted that in some alternative embodiments, the functions mentioned in the steps may occur out of order. For example, two steps illustrated in succession may in fact be performed substantially simultaneously, or the steps may sometimes be performed in a reverse order depending on the corresponding function.

[0118] The above description is merely exemplary description of the technical scope of the present disclosure, and it will be understood by those skilled in the art that various changes and modifications can be made without departing from original characteristics of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are intended to explain, not to limit, the technical scope of the present disclosure, and the technical scope of the present disclosure is not limited by the embodiments. The protection scope of the present disclosure should be interpreted based on the following claims and it should be appreciated that all technical scopes included within a range equivalent thereto are included in the protection scope of the present disclosure.