SYSTEM AND METHOD FOR CALIBRATING WEIGHTING ERRORS IN SPLIT CAPACITANCE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Abstract

The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch S.sub.M to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array C.sub.A including a binary array of P-bit unit capacitors, a calibration structure C.sub.fraq, and a ground switch S.sub.k. The calibration structure C.sub.fraq includes four unit capacitors and two switches S.sub.1 and S.sub.2. By controlling the switches S.sub.1 and S.sub.2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.

Claims

1. A system for calibrating weighting errors in an analog-to-digital converter (ADC), comprising: a comparator, a P-terminal array, a N-terminal array and a control logic unit; wherein the comparator has a positive input terminal and a negative input terminal switchably connectable to a common mode reference voltage; the positive input of the comparator is connected to the P-terminal array; the P-terminal array comprises a least significant bit (LSB) array having L bits, a bridge capacitor C.sub.BR, and a most significant bit (MSB) array having M bits; the negative input of the comparator is connected to the N-terminal array; the MSB array contains 2.sup.M1 unit capacitances, wherein a first capacitor corresponding to the unit capacitances has a first plate connected directly to the comparator, each remaining capacitor corresponding to the unit capacitances has a first plate switchably connected to the comparator, and each of the capacitors corresponding to the unit capacitances has a lower plate with a common connection that is switchably connected to a positive reference voltage, a negative reference voltage, or a differential positive input voltage; the LSB array contains 2.sup.L unit capacitors, wherein each of the unit capacitors has an upper plate connected to the comparator and a lower plate switchably connected to the positive reference voltage, the negative reference voltage, or the differential positive input voltage; the bridge capacitor is between a common connection point of the upper plates of the LSB array unit capacitors and an upper plate common connection point of the capacitors corresponding to the unit capacitances in the MSB array; the system further comprises a calibration digital-to-analog converter (DAC) array connected to the upper plates of the LSB array unit capacitors, wherein the calibration DAC array comprises a binary array of P-bit unit capacitors, a calibration structure, and a ground switch group, and the calibration structure includes (i) a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor connected in series and (ii) a first switch and a second switch configured to generate a plurality of capacitance values from the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and the control logic unit outputs the positive reference voltage, the negative reference voltage, or the differential positive input voltage.

2. The system of claim 1, having an effective number of ADC bits equal to M+L.

3. The system of claim 1, wherein the ADC is a split capacitance successive approximation analog-to-digital converter.

4. The system of claim 1, wherein the N-terminal array is a mirror image of the P-terminal array.

5. The system of claim 1, wherein the capacitors corresponding to the unit capacitances comprise a first plurality of capacitors having a first unit capacitance, a second unit capacitance, a third unit capacitance and a fourth unit capacitance.

6. The system of claim 5, wherein the second unit capacitance is twice the first unit capacitance, the third unit capacitance is four times the first unit capacitance, and the fourth unit capacitance is eight times the first unit capacitance.

7. The system of claim 1, wherein the LSB array contains a second plurality of capacitors having a fifth unit capacitance, a sixth unit capacitance, a seventh unit capacitance and an eighth unit capacitance.

8. The system of claim 7, wherein the second plurality of capacitors comprises two capacitors having the fifth unit capacitance, the sixth unit capacitance is twice the fifth unit capacitance, the seventh unit capacitance is four times the fifth unit capacitance, and the eighth unit capacitance is eight times the fifth unit capacitance.

9. The system of claim 1, wherein the binary array of P-bit unit capacitors comprises a third plurality of capacitors having a ninth unit capacitance, a tenth unit capacitance, an eleventh unit capacitance and a twelfth unit capacitance.

10. The system of claim 9, wherein the tenth unit capacitance is twice the ninth unit capacitance, the eleventh unit capacitance is four times the ninth unit capacitance, and the twelfth unit capacitance is eight times the ninth unit capacitance.

11. The system of claim 9, wherein each of the third plurality of capacitors has a lower plate switchably connectable to a ground potential.

12. The system of claim 1, wherein the calibration structure comprises a first unit capacitor, a second unit capacitor, a third unit capacitor, and a fourth unit capacitor connected in series and two switches.

13. The system of claim 12, wherein each of the first through fourth unit capacitors has a first plate and a second plate, the first plate of the first unit capacitor is connected to the second plate of the second unit capacitor, the first plate of the second unit capacitor is connected to the second plate of the third unit capacitor, and the first plate of the third unit capacitor connects to the second plate of the fourth unit capacitor.

14. The system of claim 12, wherein the two switches are connected to the second plate of the first unit capacitor, one of the two switches is connected between the second unit capacitor and the third unit capacitor, and the other of the two switches is connected between the third unit capacitor and the fourth unit capacitor.

15. The system of claim 12, wherein the first plate of the fourth unit capacitor and a first plate of each capacitor in the binary array of P-bit unit capacitors are connected in common and to the LSB array.

16. The system of claim 1, wherein the calibration DAC array further comprises a plurality of control switches configured to adjust an equivalent capacitance value of the calibration DAC array and/or the calibration structure.

17. A method of calibrating weighting errors due to parasitic capacitance in an analog-to-digital converter, comprising: disconnecting P-terminal and N-terminal switches; connecting a first plate of a most significant bit (MSB) array to a common mode voltage, connecting the second plate of a unit capacitor to a first reference voltage, and connecting a second plate of a plurality of least significant bit (LSB) array capacitors to a second reference voltage; disconnecting a common mode voltage switch from the first plate of the MSB array; switching a second plate of the unit capacitor in the MSB array to the second reference voltage, and switching a second plate of the LSB array capacitors to the first reference voltage; stabilizing a voltage at ends of a comparator, such that a voltage difference between the ends of the comparator is a voltage difference caused by the weighting error; and repeating (i) connecting the first plate of the MSB array to the common mode voltage, connecting the second plate of the unit capacitor to the first reference voltage, and connecting the second plate of the plurality of LSB array capacitors to the second reference voltage, (ii) switching the second plate of the unit capacitor in the MSB array to the second reference voltage and switching the second plate of the LSB array capacitors to the first reference voltage, and (iii) stabilizing the voltage at the ends of the comparator to converge the digital value and/or the output of the calibration capacitor array to a fixed value, thereby completing the calibration.

18. The method of claim 17, further comprising inputting a comparator result to successive-approximation-register (SAR) control logic, and controlling a plurality of switches in a calibration DAC array according to the comparator result to adjust a capacitance value of the calibration DAC array.

19. The method of claim 18, wherein the SAR control logic reads the digital value and controls the plurality of switches.

20. The method of claim 18, further comprising repeating inputting the comparator result to the SAR control logic and controlling the plurality of switches to converge the calibration DAC array to a fixed value, completing the calibration.

Description

FIGURES DESCRIPTION

[0024] FIG. 1 shows an overall structure diagram of an 8-bit split SAR ADC structure in accordance with the invention.

[0025] FIG. 2 shows a simplified structure diagram of an 8-bit single-ended capacitor array in accordance with the invention (Step 2).

[0026] FIG. 3 shows an alternative configuration of the simplified structure diagram of the 8-bit single-ended capacitor array in accordance with the present invention (Step 3).

[0027] FIG. 4 shows an equivalent circuit diagram of position {circle around (1)} input and switch S.sub.M off.

[0028] FIG. 5 shows an equivalent circuit diagram of position {circle around (2)} input and switch S.sub.M off.

[0029] FIG. 6 shows an equivalent circuit diagram of position {circle around (1)} input and switch S.sub.M on.

[0030] FIG. 7 shows an equivalent circuit diagram of position {circle around (2)} input and switch S.sub.M on.

[0031] FIG. 8 shows a structure diagram of a 16-bit split SAR ADC in accordance with the invention.

[0032] FIGS. 9A-B show a comparison of FFT plots before and after calibration of the 16-bit split SAR ADC weighting error in accordance with this invention.

DETAILED DESCRIPTION

[0033] The 8-bit split capacitive SAR ADC is used as an example to illustrate the implementation of the present invention. As shown in FIG. 1, the 8-bit ADC is divided into two parts: an MSB array (4 bits) and an LSB array (4 bits). The MSB array contains four capacitors with values of 8C.sub.u, 4C.sub.u, 2C.sub.u, and 1C.sub.u, while the LSB array contains five capacitors with values of 8C.sub.u, 4C.sub.u, 2C.sub.u, 1C.sub.u, and 1C.sub.u. The bridging capacitor between the MSB capacitor array and the LSB capacitor array is C.sub.BR. As described in step two, and shown in FIG. 2, the unit capacitor 1C.sub.u in the MSB array is connected to the reference voltage V.sub.REFP, and the remaining capacitors in the MSB array are disconnected from the main signal path. The lower plates of all (weighting) capacitors in the LSB array (excluding the calibration DAC array) are connected to the reference voltage V.sub.REFN. C.sub.P_L in the figures represents the total parasitic capacitance from the upper plates of the LSB array to ground. C.sub.P_B represents the parasitic capacitance in parallel at terminals of the bridging capacitor. The parasitic capacitance from the upper plates of the MSB array to ground does not affect the linearity between the MSB and LSB arrays, so it is not shown in the figure.

[0034] After the voltage (e.g., on various nodes such as V.sub.L_P and V.sub.M_P in the MSB and LSB arrays, across the input terminals of the comparator, etc.) stabilizes, the state shown in FIG. 3 (Step 3) is switched. After switching in step two and step three, the change of V.sub.M_P compared to V.sub.CM is set to V.sub.M_P. According to the superposition principle, V.sub.M_P is equivalent to the difference between the fluctuation of the V.sub.M_P voltage V.sub.M_P1 due to input V.sub.REFP in position {circle around (1)} and the fluctuation of V.sub.M_P voltage V.sub.M_P2 due to input V.sub.REFP in position {circle around (2)} in FIG. 3 when V.sub.CM is disconnected:

[00001]$\begin{array}{cc}{V}_{M\_P}=V_{M\_P1}-V_{M\_P2}& \left(1\right)\end{array}$

[0035] FIG. 4 shows a simplified equivalent circuit for the position {circle around (1)} input V.sub.REFP in FIG. 3. To simplify the analysis of the equation and derive it to apply to an arbitrary number of bits (not limited to 8 bits), several parameters are defined here. CLI is the total LSB weight capacitance:

[00002]$\begin{array}{cc}{C}_{Lt}=8C_u+4C_u+2C_u+C_u+C_u=16C_u& \left(2\right)\end{array}$

[0036] Since C.sub.BR and C.sub.P_B are connected in parallel, let:

[00003]$\begin{array}{cc}{C_{BR}}^{}=C_{BR}+C_{P\_B}& \left(3\right)\end{array}$

[0037] Let C.sub.eq be the equivalent capacitance seen from the MSB end to the LSB end:

[00004]$\begin{array}{cc}\begin{array}{c}{C}_{eq}=\left(C_{Lt}+C_A+C_{P\_L}\right)//\left({C_{BR}}^{}\right)\\ =\frac{\left(C_{Lt}+C_A+C_{P\_L}\right){C_{BR}}^{}}{\left(C_{Lt}+C_A+C_{P\_L}\right)+{C_{BR}}^{}}\end{array}& \left(4\right)\end{array}$

[0038] According to the above setting, V.sub.M_P1 can be obtained by the capacitor series voltage division formula:

[00005]$\begin{array}{cc}{V}_{M\_P1}=\frac{C_u}{C_{eq}+C_u}{V}_{\mathrm{REFP}}& \left(5\right)\end{array}$

[0039] FIG. 5 shows the simplified equivalent circuit V.sub.M_P2 for the position {circle around (2)} input V.sub.REFP in FIG. 3, which needs to be obtained by dividing the capacitance twice, first by dividing the voltage across the C.sub.A and then by dividing the voltage to obtain V.sub.M_P2:

[00006]$\begin{array}{cc}\begin{array}{c}{V}_{M\_P2}=\frac{C_{Lt}}{C_{Lt}+C_A+C_{P\_L}+C_{BR}\text{'}//C_u}\frac{C_{BR}\text{'}}{{C_{BR}}^{}+C_u}{V}_{\mathrm{REFP}}\\ =\frac{C_{Lt}.Math.C_{BR}\text{'}}{\left(C_{Lt}+C_A+C_{P\_L}\right)\left(C_{BR}\text{'}+C_u\right)+{C_{BR}}^{}{C}_u}{V}_{\mathrm{REFP}}\\ =\frac{C_{Lt}.Math.C_{BR}\text{'}}{\left(C_{Lt}+C_A+C_{P\_L}\right).Math.C_{BR}\text{'}+\left(C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}\right)C_u}{V}_{\mathrm{REFP}}\end{array}& \left(6\right)\end{array}$

[0040] In Equation (6), the numerator and the denominator at the same time are divided by

[00007]$\begin{array}{cc}{C}_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}:& \left(7\right)\end{array}$$V_{M\_P2}=\frac{\frac{C_{Lt}.Math.C_{BR}\text{'}}{\left(C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}\right)}}{\frac{\left(C_{Lt}+C_A+C_{P\_L}\right).Math.C_{BR}\text{'}}{\left(C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}\right)}+C_u}{V}_{\mathrm{REFP}}$$=\frac{\frac{C_{Lt}.Math.C_{BR}\text{'}}{\left(C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}\right)}}{C_{\mathrm{eq}}+C_u}{V}_{\mathrm{REFP}}$

[0041] Bringing Equation (5) and Equation (7) into Equation (1), it yields:

[00008]$$\begin{gathered} \begin{array}{cc}{V}_{M\_P}=V_{M\_P1}-V_{M\_P2}= \\ \frac{1}{C_{\mathrm{eq}}+C_u}\left(C_u-\frac{C_{Lt}.Math.C_{BR}\text{'}}{C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}}\right)V_{\mathrm{REFP}}& \left(8\right)\end{array} \end{gathered}$$

[0042] V.sub.M_P is the differential voltage of the comparator input after one calibration round, and V.sub.CM is the common mode voltage of the comparator input. Analysis of Equation (8) shows that the magnitude of the differential input voltage is determined by two aspects: the attenuation factor 1/(C.sub.eq+C.sub.u) and the term in parentheses characterizing the weighting error.

[0043] Firstly, analyzing the attenuation factor part, if the switch S.sub.M is not open during the calibration process, as shown in FIG. 6 and FIG. 7, then Equations (5), (7) and (8) should be changed to Equations (9), (10) and (11):

[00009]$\begin{array}{cc}{V_{M\_P1}}^{}=\frac{C_u}{C_{eq}+C_u+C_{Mt}}{V}_{REFP}& \left(9\right)\end{array}$$\begin{array}{cc}{V_{M\_P2}}^{}=\frac{\frac{C_{Lt}.Math.C_{BR}\text{'}}{\left(C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}\right)}}{C_{eq}+C_u+C_{Mt}}{V}_{REFP}& \left(10\right)\end{array}$$\begin{array}{cc}{V_{M\_P}}^{}={V_{M\_P1}}^{}-{V_{M\_P2}}^{}=\frac{1}{C_{eq}+C_u+C_{Mt}}\left(C_u-\frac{C_{Lt}.Math.C_{BR}\text{'}}{C_{Lt}+C_A+C_{P\_L}+{C_{BR}}^{}}\right)V_{REFP}& \left(11\right)\end{array}$

[0044] From Equation (11), it can be seen that the term characterizing the weight error remains unchanged, but the C.sub.Mt term is added to the denominator of the decay factor. Therefore, the differential voltage (error voltage) of the comparator input becomes smaller, and the phenomenon becomes more pronounced as the number of bits of the ADC increases. Therefore, disconnecting the switch S.sub.M during calibration can amplify the error voltage of the comparator input and greatly reduce the comparator design requirements.

[0045] Next, the weight error term is analyzed again. To ensure quadraticity, the design should ensure that in the absence of parasitic capacitance (e.g., C.sub.P_L=C.sub.P_B=C.sub.A=0), the weight error term should be 0, so the bridge capacitor C.sub.BR should satisfy:

[00010]$\begin{array}{cc}{C}_{BR}=\frac{C_{Lt}.Math.C_u}{C_{Lt}+C_u}& \left(12\right)\end{array}$

[0046] When there is a parasitic capacitance C.sub.P_L and C.sub.P_B is not 0, according to the output voltage of the comparator, the value of C.sub.A is selected sequentially in each round so that the weight error term gradually approaches 0. But the closer the weight error term is to 0, the lower the error voltage drops, and the higher the comparator gain requirement is. If the comparator gain requirement is too high, it will consume too much power and reduce the advantage of ADC calibration. Therefore, the present invention adopts the form of C.sub.A in FIG. 1, which can generate 8C.sub.u, 4C.sub.u, 2C.sub.u, C.sub.u, 3C.sub.u/2, C.sub.u/2 and C.sub.u/4, reducing the error to LSB/4.

TABLE-US-00001 TABLE 1 C.sub.fraq switching state and corresponding equivalent capacitance value C.sub.fraq S.sub.1 S.sub.2 3C.sub.u/2 ON ON C.sub.u/2 ON OFF C.sub.u/4 OFF OFF

[0047] As shown in FIG. 8, the two-segment 16-bit (8-bit LSB+8-bit MSB) ADC built with the above calibration scheme, the first 3 bits of the MSB array use a thermometer code to reduce the differential nonlinearity (DNL) of the ADC. FIGS. 9A-B show the results of a fast Fourier transform (FFT, 16384 points) done on the ADC before and after calibration to get the data in Table 2. It is easy to see that the SFDR (Spurious-Free Dynamic Range) is improved by 25.6976 dB, SNDR (Signal-to-Noise and Distortion Ratio) is improved by 13.5106 dB, and ENOB (Effective Number of Bits) is improved by 2.2442 bits.

TABLE-US-00002 TABLE 2 Comparison of 16-bit ADC performance before and after calibration Before After calibration calibration Improvements SFDR (dB) 86.0826 111.7802 25.6976 SNDR (dB) 82.6493 96.1599 13.5106 ENOB (bits) 13.4368 15.681 2.2442