Interdigitated back contact solar cell and method for producing an interdigitated back contact solar cell

Abstract

Provided are an interdigitated back contact solar cell (10,a,b,c), comprising a monocrystalline, n-doped wafer (101), a first contact area (40) which is formed by a first stack on the surface of said monocrystalline wafer (101), said first stack comprising a thin silicon oxide layer (201) and a highly n-doped polycrystalline silicon layer (301), and a second contact area (20) which is formed by a second stack on the same surface of said monocrystalline wafer (101) as said first stack, said second stack comprising a thin silicon oxide layer (202) and a highly p-doped polycrystalline silicon layer (701), wherein a p-doped monocrystalline silicon region (801) is located in a gap (30) between said first contact area (40) and said second contact area (20) and a method for producing such an interdigitated back contact solar cell (10,a,b,c).

Claims

1. Interdigitated back contact solar cell (10,a, b, c), comprising a monocrystalline, n-doped wafer (101), a first contact area (40) which is formed by a first stack on the surface of said monocrystalline wafer (101), said first stack comprising a thin silicon oxide layer (201) and a highly n-doped polycrystalline silicon layer (301), and a second contact area (20) which is formed by a second stack on the same surface of said monocrystalline wafer (101) as said first stack, said second stack comprising a thin silicon oxide layer (202) and a highly p-doped polycrystalline silicon layer (701), characterized in that a p-doped monocrystalline silicon region (801) is located in a gap (30) between said first contact area (40) and said second contact area (20).

2. Interdigitated back contact solar cell (10,a,b,c) according to claim 1, characterized in that the gap (30) is formed by a trench (112).

3. Interdigitated back contact solar cell (10,a,b,c) according to claim 2, characterized in that the height of the opposite side walls of the trench (112) is different.

4. Interdigitated back contact solar cell (10, a, b, c) according to claim 1, characterized in that the interdigitated back contact solar cell (10,a,b, c) further comprises a p-doped floating emitter (801) on the side of the wafer (101) that is opposite to the side on which the first and second contact areas (20, 40) are located.

5. Interdigitated back contact solar cell (10, a, b, c) according to claim 1, characterized in that the width of the gap (30) is equal or wider than half of the widths of at least one of the first contact area (40) or the second contact area (20).

6. Method for producing an interdigitated back contact solar cell (10, a, b, c) according to claim 1, said method comprising the steps of creating a first contact area (40) which is formed by a first stack on the surface of a monocrystalline, n-doped wafer (101), said first stack comprising a thin silicon oxide layer (201) and a highly n-doped polycrystalline silicon layer (301), creating a second contact area (20) which is formed by a second stack on the same surface of said monocrystalline, n-doped wafer (101) as said first stack, said second stack comprising a thin silicon oxide layer (202) and a highly p-doped polycrystalline silicon layer (701), creating a gap (30) between the said first contact area and said second contact area, and creating a p-doped monocrystalline silicon region (801) located in the gap (30) between said first contact area (40) and said second contact area (20).

7. Method according to claim 6, characterized in that after the first contact area (40) has been created, alkaline etching is performed in an area of the surface of the monocrystalline, n-doped wafer (101) outside of the first contact area (40) but comprising the area in which the second contact area (20) is to be created, so that the thickness of the monocrystalline, n-doped silicon wafer (101) is reduced in the area where the alkaline etching is performed.

8. Method according to claim 6, characterized in that the second contact area (20) is created by modifying the etching resistance of an intrinsic polycrystalline layer by locally diffusing p-dopant into the layer only where the second contact area (20) is to be created to obtain a local highly doped region, which is not etched in a subsequent alkaline etching step creating a gap region (30).

9. Method according to claim 6, characterized in that when creating the p-doped monocrystalline silicon region (801) located in the gap (30) between said first contact area (40) and said second contact area (20), a front floating emitter structure is created simultaneously.

10. Method according to claim 6, characterized in that when creating the p-doped monocrystalline silicon region (801) located in the gap (30) between said first contact area (40) and said second contact area (20), the p-doping of the highly p-doped polycrystalline silicon layer (701) of the second contact area (20) is modified.

Description

[0034] FIG. 1: A possible solar cell processing sequence according to one embodiment of the invention,

[0035] FIG. 2: three bypass diode functional structures of IBC solar cells according to embodiments of the invention, and

[0036] FIG. 3: reverse bias curves of a solar cell according to one embodiment of the invention and reverse bias curves of a homogeneous diffused IBC solar cell (ZEBRA) and of a solar cell without a doped p+ region in a gap between the two polarity polysilicon regions.

[0037] It should be noted that in the Figures schematic cross sec-tions, which are not to scale, of the solar cells or solar cell precursors, respectively, are displayed with their front side, i.e. the side that is to be facing the sun, pointing down and their back side, i.e. the side that is opposite to the side that is to be facing the sun, is pointing up.

[0038] Likewise, it should be noted that in FIGS. 1 and 2 only a part of a complete wafer 101 is shown, but only a unit cell comprising one second contact area as well of half of each of the two neighboring first contact areas arranged next to it and the gaps separating the first contact areas from the second contact areas. Placing a large number of these unit cells next to each other leads to a corresponding schematic cross section, which is not to scale, through a complete solar cell wafer.

[0039] FIG. 1 schematically describes various intermediate stages 1-9 (i.e. solar cell precursors) and the final interdigitated back contact solar cell 10 obtained by one possible embodiment of a method according to the invention.

[0040] In this example, the processing of the solar cell according to this invention starts with providing a pre-processed solar wafer 101, typically an n-type mono-crystalline substrate, after saw damage removal and cleaning. Intermediate stage 1 shows this wafer 101 on which a first layer stack, a part of which will be used to form the first contact area, has been deposited on at least one side.

[0041] The layer stack consists in this example of a thin thermal silicon oxide layer 201, an n-type amorphous or polycrystalline silicon layer 301 and an etching and diffusion mask 401, e.g. SiOx or SiNx deposited by PECVD. Depending on the processing sequence that is applied, at this stage the n-type doping does not yet have to be completed; it is also possible to provide the Si layer and a dopant source layer and drive in the dopant atoms from the dopants source layer at a later point of time.

[0042] In the intermediate stage 2, the mask is locally removed. This can be done, as illustrated, by laser ablation, but also in different ways, e.g. by applying a suitable etching paste.

[0043] Forming a first trench 111 by alkaline etching leads to intermediate stage 3. In this stage, the first contact areas 10 are already pre-formed.

[0044] The intermediate stage 4 is then reached by deposition of a second stack of a thin interface silicon oxide 202, and an intrinsic amorphous or polycrystalline silicon layer 501 with a p+ dopant layer on top 601 on at least the same side of the wafer 101.

[0045] This stack which is subsequently treated, as illustrated in intermediate stage 5 by a laser, the width of which is adapted so that the entire laser beam is within the first trench 111, but with a width that is smaller than the width of said trench 111, because the first contact areas 40 and the second contact areas are arranged at different heights.

[0046] By doing so, as seen in intermediate stage 6, a highly p-doped polysilicon layer 701 is formed on top of the thin silicon oxide layer 202, thus forming the second contact areas 20 and defining the gaps 30 between first contact areas 40 and second contact areas 20. Well-known alternative methods for localized doping application may also be considered such as masked ion implantation or local screen printing of solid doping layers

[0047] The highly p-doped polysilicon layer 701 is more etch re-sistant against alkaline solutions compared to the undoped polysilicon layer 501. Therefore, an alkaline solution is then used to remove the non-treated areas including the surface of the first contact area, which leads to the formation of trenches 112 in the gap region 30. The opposing walls of these trenches 112 have a different height. The alkaline solution may also be used to create a textured surface in a second trench 112 and also of the front side of the wafer (not shown).

[0048] Next, intermediate stage 8 is created by a diffusion of the same dopant type as used for the polysilicon layer 701 of the second contact areas 20 is employed (e.g. a tube furnace diffusion of BBr.sub.3, BCl.sub.3 or another type of dopant source for the same type of doping), thus creating a highly p-doped monocrystalline silicon region 801 located in the gaps 30 between said first contact areas 40 and said second contact areas 20 by a homogenous in-diffusion of emitter type dopant into the bulk of wafer 101 that forms the bottom of the trench. This also creates the bypass active area.

[0049] At the same time this dopant may also be used to dope the front side of the sample creating a so called front floating emitter structure, which is not shown in intermediate stage 8.

[0050] Then at least the back side, but typically both sides of the wafer are coated with dielectric layers e.g. SiNx or AlOx/SiNx 402, leading to intermediate stage 9. Alternatively, a stack of SiOx in-situ (in the diffusion furnace grown oxide) or sepa-rately grown, covered by SiNx may be used to passivate the sur-faces.

[0051] The final interdigitated back side contact solar cell 10 also comprises metal contacts 911, 912 on the respective first and second contact areas 40,20. These are typically created by screen printing a metal paste onto these regions and firing. In this context, it is noted that due to the different height of first contact area 40 and second contact area 20, respectively, separate screen printing processes can be used selectively for the respective first and second contact areas 40,20.

[0052] In one embodiment of the invention, which is not shown in FIG. 1, the etching and diffusion mask 401 may be removed at one stage in the process flow, preferably after intermediate stage 7 has been reached.

[0053] Small alteration in the processing sequence can lead to different embodiments of the invention, such as the interdigitated back contact solar cells a, b and c that are shown in FIG. 2, using the same reference numerals of FIG. 1 for the various constituent parts of the IBC solar cells.

[0054] Specifically, in FIG. 2 the bypass diode functional structure 1001,1002 is indicated by a square with broken lines. Depending on choice of etching medium, the doped surface may textured as in diode functional structure 1001, or flat etched as in diode functional structure 1002 according to known alkaline etching steps.

[0055] In the embodiments of the invention shown as b and c, instead of a front floating emitter 801, a front surface field diffusion (of the same type as the base) 802 may be employed. To achieve these three variations, additional masking layers or single side treatments may be necessary which are well-known to people skilled in the art.

[0056] Also, in FIG. 2 the respective first contact areas 40, second contact areas 20, and gaps 30 are indicated.

[0057] FIG. 3 indicates the superior reverse bias behaviour with a very early breakdown voltage without affecting the shunt resistance (and light IV parameters) of the solar cell according to an embodiment of the invention in comparison of state-of the art homogeneous diffusion based IBC solar cells, specifically a ZEBRA solar cell, and a structure with a trench-shaped, but undoped gap between the first and the second contact area.