Diode/Superionic Conductor/Polymer Memory Structure

Abstract

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Claims

1-39. (canceled)

40. A method of forming a semiconductor device comprising: forming a first electrode over a substrate; forming an insulative material over the first electrode; forming an opening extending through the insulative material to the first electrode; forming a polymer material in contact with said first electrode; forming a diode comprising a first metal-chalcogenide layer of a first conductivity type within the opening and in contact with said polymer material; and forming a second electrode in contact with said diode.

41. The method of claim 40 wherein the second electrode extends perpendicularly relative to the first electrode.

42. A method of forming a semiconductor device comprising: forming an insulative material over a substrate; forming an opening extending through the insulative material to the substrate; forming a first electrode within the opening; forming a polymer material within the opening in contact with said first electrode; forming a diode comprising a first metal-chalcogenide layer of a first conductivity type within the trench; and forming a second electrode in contact with said diode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a plan view of a memory cell constructed in accordance with the present invention;

[0007] FIG. 1A is a cross-section of the memory cell of FIG. 1, taken along line 1A-1A;

[0008] FIG. 1B is a cross-section of the memory cell of FIG. 1, taken along line 1B-1B;

[0009] FIG. 1C is a plan view of the memory cell of FIG. 1 cut back at two levels;

[0010] FIG. 2 illustrates a preform for the memory cell of FIG. 1 at an initial stage of fabrication;

[0011] FIG. 2A is a plan view of the memory cell preform of FIG. 2 at a subsequent stage of fabrication;

[0012] FIG. 2B is a cross-section of the memory cell preform of FIG. 2A, taken along line 2B-2B;

[0013] FIG. 3 illustrates the memory cell preform of FIG. 2A at a subsequent stage of fabrication;

[0014] FIG. 4 illustrates the memory cell preform of FIG. 3 at a subsequent stage of fabrication;

[0015] FIG. 5 illustrates the memory cell preform of FIG. 4 at a subsequent stage of fabrication;

[0016] FIG. 5A is a plan view of the memory cell preform of FIG. 5 at a subsequent stage of fabrication, cut back at one level;

[0017] FIG. 5B is a cross-section of the memory cell preform of FIG. 5A, taken along line 5B-5B;

[0018] FIG. 6 illustrates the memory cell preform of FIG. 5 at a subsequent stage of fabrication;

[0019] FIG. 7 illustrates the memory cell preform of FIG. 6 at a subsequent stage of fabrication;

[0020] FIG. 8 illustrates the memory cell preform of FIG. 7 at a subsequent stage of fabrication;

[0021] FIG. 9 illustrates the memory cell preform of FIG. 8 at a subsequent stage of fabrication;

[0022] FIG. 10 illustrates the memory cell preform of FIG. 9 at a subsequent stage of fabrication;

[0023] FIG. 11 is a plan view of another embodiment of the present invention;

[0024] FIG. 11A is a cross-section of the embodiment of FIG. 11, taken along line 11A-11A;

[0025] FIG. 11B is a cross section of the embodiment of FIG. 11, taken along line 11B-11B;

[0026] FIG. 12 is a block diagram of a memory device of the present invention.

[0027] FIG. 13 is a schematic diagram of processing system employing a memory device of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0028] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

[0029] The term substrate used in the following description may include any supporting structure including but not limited to a glass, plastic, or semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures which may not be silicon-based. When reference is made to a semiconductor substrate in the following description, previous process steps may have been utilized to form regions or junctions in and/or over the base semiconductor or foundation.

[0030] The term metal is intended to include not only the elemental metal employed, but the elemental metal with other trace metals or in various alloyed combinations with other metals as is known in the semiconductor industry, as long as such metal alloy is conductive, and as long as the physical and electrical properties of the elemental metal remain unchanged.

[0031] Referring now to the drawings where like elements are designated by like reference numerals, there is shown in FIG. 1 a memory cell 15 constructed in accordance with the present invention. The memory cell 15 has a substrate 10 and two insulating layers 20 and 22. There are openings 26a and 26b in the insulating layers 22 and 20, respectively. The opening 26a is a trench in insulating layer 22 and contains a bottom conductive electrode layer 35. The opening 26b is a hole in insulating layer 20 and contains a first metal-chalcogenide layer 45 and a second metal-chalcogenide layer 55. The first metal-chalcogenide layer 45 is located over the conductive electrode layer 35. The insulating layers 20 and 22 are preferably Si.sub.3N.sub.4 to prevent migration of metals through the insulating layers 20 and 22.

[0032] The first metal-chalcogenide layer 45 has a first conductivity type. The second metal-chalcogenide layer 55 is located over the first metal-chalcogenide layer 45. The second metal-chalcogenide layer 55 has a second conductivity type. The top of the second metal-chalcogenide layer 55 is flush with the top surface of the insulating layer 20. A polymer layer 60 is located over the second metal-chalcogenide layer 55. A top electrode 70 is located over the polymer layer 60 and insulating layer 20. FIG. 1C shows in plan view the memory cell 15 with two levels cut back to reveal the substrate 10 at one level and the bottom electrode layer 35 in the insulating layer 22 at another level. The top electrode 70 runs perpendicularly to the bottom electrode layer 35.

[0033] In operation, the memory cell 15 stores data based on the resistivity of the conjugated polymer layer 60. The resistivity of the conjugated polymer layer 60 changes from a high resistance to a low resistance when ions are donated from the second metal-chalcogenide layer 55.

[0034] The combination of first metal-chalcogenide layer 45 of a first conductivity in contact with second metal-chalcogenide layer 55 of a second conductivity creates a diode 80 (FIG. 1A) built into the memory cell 15. The diode 80 operates the memory cell 15 by creating a threshold voltage at which the resistivity of the conjugated polymer layer 60 will change. Building the diode 80 into the memory cell 15, instead of providing a separate component connected in series with the memory cell, improves the switching properties of the memory cell 15, while maintaining a relatively small structure.

[0035] The bottom conductive electrode layer 35 may comprise, for example, a metal such as Al or Ti, an oxide compound, such as indium-tin-oxide (TIP), or copper, or a semiconductor or a conducting polymer. Al and Ti may be preferred over Cu for certain products, where the Cu may tend to diffuse through an Ag-rich layer to a Cu.sub.2Se or Cu.sub.2S layer (to be described below), which could affect the operation of the memory device. Other suitable conductive materials which cannot diffuse through the Ag-rich layer and affect the mechanism of the device may also be used.

[0036] The first metal-chalcogenide layer 45 may comprise an n-type semiconductor such as Ag.sub.2Se or Ag.sub.2S. The Ag.sub.2Se or Ag.sub.2S may be provided in a superionic conductor phase or in an n-type semiconductor phase.

[0037] The second metal-chalcogenide layer 55 may comprise a p-type semiconductor such as Cu.sub.2Se or Cu.sub.2S in a p-type semiconductor phase or in a superionic conductor phase. If the first metal-chalcogenide layer 45 comprises Ag.sub.2Se, then the second metal-chalcogenide layer 55 preferably comprises Cu.sub.2Se. If the first metal-chalcogenide layer 45 comprises Ag.sub.2S, then the second metal-chalcogenide layer 55 preferably comprises Cu.sub.2S.

[0038] Even when the metal-chalcogenide layers are provided in their semiconductor phases, they possess superionic properties. The high temperatures at which they are deposited (above the phase transition temperature of the material) change the material properties entirely to the superionic conducting phase. Although the materials return to a semiconductor phase when the temperature is lowered, they still retain some superionic defects, making them capable of donating ions to the conjugated polymer layer 60.

[0039] The polymer layer 60 may comprise materials such as polymethylphenylacetylene, copperphtalocyanine, polyparaphenylene, polyphenylenevinylene, polyaniline, polythiophene and polypyrrole. Other suitable conjugated polymer materials that adhere to the copper content of the second metal-chalcogenide layer 55 may be used as well. In a preferred embodiment of the invention, the material of the polymer layer 60 adheres only, or at least preferentially, to the material of the second superionic conductor layer 55.

[0040] FIG. 2 illustrates a cross-sectional view of a memory cell preform 3 at an initial stage of fabrication. A first insulating layer 22 is deposited over the substrate 10. As shown in FIGS. 2A and 2B, a masking layer 27 is deposited in a trench pattern over the insulating layer 22 and etched to form the trench opening 26a. The masking layer 27 is then removed.

[0041] As shown in FIG. 3, at a subsequent stage of fabrication, conductive material 30 is deposited in the opening 26a. As discussed above, the conductive material 30 may be, for example, a metal such as Al or Ti, an oxide compound, such as indium-tin-oxide (ITO), or copper, or a semiconductor or a conducting polymer. The conductive material 30 is etched or planarized to produce a conductive electrode layer 35 in the trench opening 26a as shown in FIG. 4.

[0042] FIG. 5 illustrates a cross-sectional view of a memory cell preform 3 at a subsequent stage of fabrication. A second insulating layer 20 is deposited over the first insulating layer 22 and conductive electrode layer 35. As shown in FIGS. 5A and 5B, a masking layer 28 is deposited in a hole-shaped pattern over the insulating layer 20 and etched to form the hole-shaped opening 26b. The masking layer 28 is then removed.

[0043] Subsequently, the first metal-chalcogenide material 40 (FIG. 6) is deposited in the opening 26b. The first metal-chalcogenide material 40 is preferably an n-type semiconductor such as Ag.sub.2Se or Ag.sub.2S. The Ag.sub.2Se or Ag.sub.2S may be provided in an n-type semiconductor phase or in a superionic conductor phase. First metal-chalcogenide material 40 may be formed by known methods such as sputtering. The first metal-chalcogenide material 40 is etched to produce a first metal-chalcogenide layer 45 (FIG. 7) in the bottom of opening 26b, over and in contact with the conductive electrode layer 35.

[0044] The second metal-chalcogenide material 50 (FIG. 8) is then deposited in the opening 26b. As discussed above, the second metal-chalcogenide material 50 is preferably a p-type semiconductor such as Cu.sub.2Se or Cu.sub.2S in a p-type semiconductor phase or in a superionic conductor phase. If Ag.sub.2Se is used as the first metal-chalcogenide material 40, then it is preferable to use Cu.sub.2Se as the second metal-chalcogenide material 50. If Ag.sub.2S is used as the first metal-chalcogenide material 40, then it is preferable to use Cu.sub.2S as the second metal-chalcogenide material 50. Second metal-chalcogenide material 50 may be formed by known methods such as sputtering. The second metal-chalcogenide material 50 is then etched to produce a second metal-chalcogenide layer 55 (FIG. 9) in the bottom of opening 26b, over and in contact with first metal-chalcogenide layer 45. The top of second metal-chalcogenide layer 51 is at the same level as the top of insulating layer 21.

[0045] A conjugated polymer material is then selectively deposited over the second metal-chalcogenide layer 55 to form a polymer layer 60 (FIG. 10). As discussed above, the second metal-chalcogenide layer 55 acts as an adhesion layer so that the polymer layer 60 to be deposited thereon will adhere to it. The copper content of the second metal-chalcogenide layer 55 is suitable to serve as an adhesion layer for a number of different polymer materials, such as polymethylphenylacetylene, or copperphtalocyanine. Other conjugated polymer materials such as such as polyparaphenylene, polyphenylenevinylene, polyaniline, polythiophene and polypyrrole may also be deposited.

[0046] In order to selectively deposit the conjugated polymer material over the second metal-chalcogenide layer 55, the memory cell preform 3 is located in a relatively large chamber where a relatively small volume of liquid monomer is provided (not shown). A monomer gas is also provided with the large volume. The memory cell preform 3 is held in this chamber for a period of time and maintained at a desired temperature range. The period of time and temperature range may vary depending on the particular materials used. The polymerization creates a polymeric film of the conjugated polymer material that takes place at the monomer gas-solid interface. The type of conjugated polymer material that will polymerize over the surface of the second metal-chalcogenide layer 55 is dependant on the type of monomer gas used.

[0047] FIG. 1 is a plan view of the memory cell preform 3 of FIG. 10 at a final stage of fabrication. As shown in FIGS. 1A and 1B, a conductive material is deposited over the top surface of polymer layer 60 to form a top electrode 70.

[0048] In another embodiment of the invention, the layers may be deposited in a reverse order, as shown in FIG. 11. As shown in FIGS. 1A and 1B, a bottom electrode 170 lies in a trench in a first insulating layer. A polymer layer 160, a first metal-chalcogenide layer 155, and a second metal-chalcogenide layer 145 are formed in a hole in a second insulating layer 120 over the bottom electrode 170 and the first insulating layer 122. The first metal-chalcogenide layer 155 is deposited over and in contact with the polymer layer 160. First metal-chalcogenide layer 155 is preferably a p-type semiconductor such as Cu.sub.2Se or Cu.sub.2S in a superionic conductor phase. The second metal-chalcogenide layer 145 is deposited over and in contact with the first metal-chalcogenide layer 155 and is preferably an n-type semiconductor such as Ag.sub.2Se or Ag.sub.2S. If Cu.sub.2Se is used as the p-type semiconductor, then Ag.sub.2Se is preferably used as the n-type semiconductor. If Cu.sub.2S is used as the p-type semiconductor, then Ag.sub.2S is preferably used as the n-type semiconductor. The Ag.sub.2Se or Ag.sub.2S may be provided in an n-type semiconductor phase or in a superionic conductor phase.

[0049] A top electrode 135 is patterned over and in contact with the second metal-chalcogenide layer 145 such that it runs perpendicularly to the bottom electrode 170. The top electrode 130 is a conductive material and may be, for example, a metal such as Al or Ti, an oxide compound, such as indium-tin-oxide (ITO), a semiconductor or a conducting polymer. As described above, Cu may tend to diffuse through an Ag-rich layer to a Cu.sub.2Se or Cu.sub.2S layer, which could affect the operation of the memory device. Thus, Al and Ti may be preferred over Cu for certain products. Similarly, any other conductive material which cannot diffuse through the Ag-rich layer and affect the mechanism of the device is preferable.

[0050] FIG. 12 illustrates a memory device 300 of the present invention. The memory device 300 includes a plurality of memory blocks 301. Each block 301 includes one or more memory cells 15. The plurality of blocks 301 are coupled to a row control circuit 302 and a column control circuit 303, for addressing and controlling reading and writing of one or more memory cells 15 of a selected block 301. The column control circuit 303 is also coupled to a write buffer 304, which holds data to be written and to input/output buffers 305 for buffering off-device communications. A controller 306, coupled to the row control circuit 302, column control circuit 303, and input/output buffers 305, coordinates the activities of the device.

[0051] FIG. 13 illustrates a processing system 400 which may utilize the memory device 300 of the present invention. The processing system 400 includes one or more processors 401 coupled to a bus 404. The memory device 300 is controlled by the processor 401. Input device 402 and output device 403 are also coupled to the bus 404 to communicate with the processor 401.

[0052] The above description and drawings illustrate preferred embodiments which achieve the features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention. AMENDMENTS TO THE CLAIMS