Radio frequency switching circuit

Abstract

A radio frequency (RF) switching circuit is provided. The RF switching circuit includes a low-figure-of-merit (FOM) switching path that requires a longer duration to be switched on and off and a high-FOM switching path having a higher FOM than the low-FOM switching path but that can be switched on and off faster than the low-FOM switching path. In one aspect, the RF switching circuit passes an RF signal via the high-FOM switching path while toggling the low-FOM switching path to help reduce overall switching time of the RF switching circuit. In another aspect, the RF switching circuit passes the RF signal via the low-FOM switching path whenever the low-FOM switching path is switched on to help improve overall FOM of the RF switching circuit. As a result, the RF switching circuit may achieve a good overall response time and a reasonable overall FOM.

Claims

1. A radio frequency (RF) switching circuit comprising: a signal input to receive an RF signal; a signal output to output the RF signal; a hybrid switch circuit comprising: a low-figure-of-merit (FOM) switching path coupled between the signal input and the signal output; and a high-FOM switching path coupled in parallel to the low-FOM switching path between the signal input and the signal output; and a control circuit configured to: cause the high-FOM switching path to be switched on earlier than the low-FOM switching path in a switch-on operation and remain switched on until the low-FOM switching path is switched off; and cause the high-FOM switching path to be switched off later than the low-FOM switching path in a switch-off operation.

2. The RF switching circuit of claim 1 wherein the hybrid switch circuit is configured to pass the RF signal from the signal input to the signal output via the low-FOM switching path when the low-FOM switching path is switched on.

3. The RF switching circuit of claim 1 wherein the hybrid switch circuit is configured to pass the RF signal from the signal input to the signal output via the high-FOM switching path when the low-FOM switching path is switched off.

4. The RF switching circuit of claim 1 wherein: the low-FOM switching path comprises a first low-FOM switch coupled between the signal input and the signal output, the first low-FOM switch having a first FOM and corresponding to a first switching duration; and the high-FOM switching path comprises: a second low-FOM switch coupled to the signal input, the second low-FOM switch having the first FOM and corresponding to the first switching duration; and a high-FOM switch coupled between the second low-FOM switch and the signal output, the high-FOM switch having a second FOM higher than the first FOM and corresponding to a second switching duration shorter than the first switching duration.

5. The RF switching circuit of claim 4 wherein in the switch-on operation, the control circuit is further configured to: close the first low-FOM switch to switch on the low-FOM switching path; and close the second low-FOM switch and the high-FOM switch to switch on the high-FOM switching path.

6. The RF switching circuit of claim 5 wherein the control circuit is further configured to: toggle the second low-FOM switch at a first switch-on time to cause the second low-FOM switch to close at a second switch-on time after the first switch-on time; and toggle the high-FOM switch and the first low-FOM switch concurrently at the second switch-on time.

7. The RF switching circuit of claim 5 wherein the control circuit is further configured to: toggle the second low-FOM switch at a first switch-on time to cause the second low-FOM switch to close at a second switch-on time after the first switch-on time; toggle the high-FOM switch at the second switch-on time; and toggle the first low-FOM switch at a third switch-on time in between the first switch-on time and the second switch-on time.

8. The RF switching circuit of claim 7 wherein the third switch-on time is determined to prevent the first low-FOM switch from being fully closed at the second switch-on time.

9. The RF switching circuit of claim 4 wherein the control circuit is further configured to: open the first low-FOM switch to switch off the low-FOM switching path; and open at least one of the second low-FOM switch and the high-FOM switch to switch off the high-FOM switching path.

10. The RF switching circuit of claim 9 wherein the control circuit is further configured to: toggle the first low-FOM switch at a first switch-off time to cause the first low-FOM switch to open at a second switch-off time after the first switch-off time; and toggle the high-FOM switch and the second low-FOM switch concurrently at the second switch-off time.

11. The RF switching circuit of claim 9 wherein the control circuit is further configured to: toggle the first low-FOM switch at a first switch-off time to cause the first low-FOM switch to open at a second switch-off time after the first switch-off time; and toggle the high-FOM switch and the second low-FOM switch concurrently at a third switch-off time after the first switch-off time and before the second switch-off time.

12. The RF switching circuit of claim 11 wherein the third switch-off time is determined to prevent the first low-FOM switch from being fully open at the third switch-off time.

13. The RF switching circuit of claim 4 wherein the first low-FOM switch and the second low-FOM switch are microelectromechanical systems (MEMS) switches.

14. The RF switching circuit of claim 13 wherein the second low-FOM switch comprises a lesser number of switchlets than the first low-FOM switch.

15. The RF switching circuit of claim 4 wherein the high-FOM switch comprises a silicon-on-insulator (SOI) switch.

16. The RF switching circuit of claim 15 wherein the SOI switch is provided in a complementary metal-oxide semiconductor (CMOS) die.

17. The RF switching circuit of claim 16 wherein the CMOS die comprises an SOI shunt switch coupled between the signal output and a ground.

18. The RF switching circuit of claim 16 wherein the CMOS die comprises a charge pump configured to generate an operating voltage for closing the first low-FOM switch and the second low-FOM switch.

19. The RF switching circuit of claim 16 wherein the CMOS die comprises: an SOI shunt switch coupled between the signal output and a ground; and a charge pump configured to generate an operating voltage for closing the first low-FOM switch and the second low-FOM switch.

20. The RF switching circuit of claim 1 further comprising: at least one second signal output to output the RF signal; and at least one second hybrid switch circuit coupled between the signal input and the at least one second signal output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1A is a schematic diagram of a microelectromechanical systems (MEMS) switch that typically exhibits a lower figure-of-merit (FOM) but a longer switching duration;

(3) FIG. 1B is a schematic diagram of a silicon-on-insulator (SOI) switch that exhibits a higher FOM but a shorter switching duration;

(4) FIG. 2 is a schematic diagram of an exemplary radio frequency (RF) switching circuit configured according to an embodiment of the present disclosure to achieve a balance between overall FOM and switching duration;

(5) FIG. 3A is a graphic diagram providing an exemplary illustration of the RF switching circuit of FIG. 2 configured to perform switch-on and switch-off operations based on one embodiment of the present disclosure;

(6) FIG. 3B is a graphic diagram providing an exemplary illustration of the RF switching circuit of FIG. 2 configured to perform switch-on and switch-off operations based on another embodiment of the present disclosure;

(7) FIG. 4 is a schematic diagram of an exemplary high-FOM switch that may be provided in the RF switching circuit of FIG. 2; and

(8) FIG. 5 is a schematic diagram of an exemplary single-pole multi-throw (SPMT) RF switching circuit.

DETAILED DESCRIPTION

(9) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(10) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(11) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(12) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(13) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(14) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(15) Aspects disclosed in the detailed description include a radio frequency (RF) switching circuit. In examples disclosed herein, the RF switching circuit includes a low-figure-of-merit (FOM) switching path having a lower FOM but requires a longer duration to be switched on and off. The RF switching circuit also includes a high-FOM switching path having a higher FOM than the low-FOM switching path but can be switched on and off faster than the low-FOM switching path. In one aspect, the RF switching circuit passes an RF signal via the high-FOM switching path while toggling the low-FOM switching path (e.g., from “off” to “on” or from “on” to “off”) to help reduce overall switching time of the RF switching circuit. In another aspect, the RF switching circuit passes the RF signal via the low-FOM switching path whenever the low-FOM switching path is switched on to help improve overall FOM of the RF switching circuit. As a result, the RF switching circuit may achieve a good overall response time and a reasonable overall FOM.

(16) Before discussing an RF switching circuit of the present disclosure starting at FIG. 2, a brief overview of a microelectromechanical systems (MEMS) switch and a silicon-on-insulator (SOI) switch is first provided with reference to FIGS. 1A and 1B to help understand pros and cons of the MEMS switch and the SOI switch.

(17) In this regard, FIG. 1A is a schematic diagram of an exemplary MEMS switch 10 that typically exhibits a lower FOM but a longer switching duration. The MEMS switch 10 includes a number of switchlets 12(1)-12(N) coupled in parallel between a signal input 14 and a signal output 16. Each of the switchlets 12(1)-12(N) includes a respective MEMS switch 18 that can be closed by a respective operating voltage V.sub.OP1 of approximately 30 volts. Each MEMS switch 18 exhibits an on-resistance (R.sub.ON) when closed and an off-capacitance (C.sub.OFF) when open. Accordingly, the MEMS switch 10 can exhibit a lower overall FOM that is typically less than 30 femtoseconds (fs). However, the MEMS switch 10 may require approximately 10 to 25 microseconds (μs) to be switched on or off.

(18) FIG. 1B is a schematic diagram of an exemplary SOI switch 20 that typically exhibits a higher FOM but a shorter switching duration. The SOI switch 20 includes a number of field-effect transistors (FETs) 22(1)-22(M) coupled in series between a signal input 24 and a signal output 26. The FETs 22(1)-22(M) can be closed by a respective operating voltage V.sub.OP2 of approximately 2.5 volts. Each of the FETs 22(1)-22(M) has a respective on-resistance (R.sub.ON) when closed and a respective off-capacitance (C.sub.OFF) when open. The FETs 22(1)-22(M) may be coupled in parallel to a number of resistors 28(1)-28(M), respectively. Each of the resistors 28(1)-28(M) has a respective resistance R. The SOI switch 20 can be switched on or off in approximately 0.2 μs. However, the SOI switch 20 can exhibit a higher overall FOM that is typically around 100 fs.

(19) As discussed above, the MEMS switch 10 exhibits the lower FOM that can help reduce insertion loss but may be too slow to meet a more stringent switching time requirement (e.g., <2 μs) of some communication technologies, such as the fifth-generation new-radio (5G-NR) technology. On the other hand, the SOI switch 20 can meet the stringent switching time requirement of the 5G-NR technology but may introduce a higher insertion loss. As such, it may be necessary to make a proper trade-off between the FOM and the switching duration in an RF switching circuit used for the 5G-NR technology.

(20) In this regard, FIG. 2 is a schematic diagram of an exemplary RF switching circuit 30 configured according to an embodiment of the present disclosure to achieve a balance between overall FOM and switching duration. As discussed in detail below, the RF switching circuit 30 includes a hybrid switch circuit 32 configured to capitalize on the lower FOM of the MEMS switch 10 in FIG. 1A and the shorter switching duration of the SOI switch 20 in FIG. 1B.

(21) In a non-limiting example, the hybrid switch circuit 32 includes a low-FOM switching path SP.sub.1 having a lower FOM but a longer switching duration and a high-FOM switching path SP.sub.2 having a shorter switching duration but a higher FOM.

(22) In one aspect, the RF switching circuit 30 passes an RF signal 34 via the high-FOM switching path SP.sub.2 before the low-FOM switching path SP.sub.1 is switched on. In this regard, the RF switching circuit 30 is able to achieve the shorter switching duration at an expense of the higher FOM. In another aspect, the RF switching circuit 30 passes the RF signal 34 via the low-FOM switching path SP.sub.1 whenever the low-FOM switching path SP.sub.1 is switched on, thus helping to improve an overall FOM of the RF switching circuit 30. By capitalizing on the shorter switching duration of the high-FOM switching path SP.sub.2 and the lower FOM of the low-FOM switching path SP.sub.1, it may be possible for the RF switching circuit 30 to meet the stringent switching time requirement of the 5G-NR technology with reasonable overall FOM.

(23) The low-FOM switching path SP1 and the high-FOM switching path SP2 are coupled in parallel between a signal input 36, which receives an RF signal 34, and a signal output 38, which outputs the RF signal 34. The low-FOM switching path SP.sub.1 includes a first low-FOM switch 40 coupled between the signal input 36 and the signal output 38. The high-FOM switching path SP.sub.2 includes a second low-FOM switch 42 and a high-FOM switch 44. The second low-FOM switch 42 is coupled to the signal input 36 and the high-FOM switch 44 is coupled between the second low-FOM switch 42 and the signal output 38.

(24) In a non-limiting example, the first low-FOM switch 40 and the second low-FOM switch 42 are identical to the MEMS switch 10 of FIG. 1A, which can be closed by the operating voltage V.sub.OP1. Accordingly, the first low-FOM switch 40 and the second low-FOM switch 42 both exhibit the lower FOM (e.g., <40 fs) and the longer switching duration (e.g., 10-25 μs). Like the MEMS switch 10, each of the first low-FOM switch 40 and the second low-FOM switch 42 is associated with an on-resistance R.sub.ONL and an off-capacitance C.sub.OFFL. In a non-limiting example, the second low-FOM switch 42 is configured to have a lesser number of the switchlets 12(1)-12(N) in FIG. 1A than the first low-FOM switch 40. Accordingly, the second low-FOM switch 42 may have a smaller footprint than the first low-FOM switch 40.

(25) The high-FOM switch 44 may be identical to the SOI switch 20 of FIG. 1B, which can be closed by the operating voltage V.sub.OP2. Accordingly, the high-FOM switch 44 exhibits the higher FOM (e.g., 100 fs) and the shorter switching duration (e.g., 0.2 μs). Like the SOI switch 20, the high-FOM switch 44 is associated with an on-resistance R.sub.ONH and an off-capacitance C.sub.OFFH. It should be appreciated that the high-FOM switch 44 can also be any other type of switch that can achieve a similar switching duration as the SOI switch 20.

(26) The RF switching circuit 30 can further include a control circuit 46, which can be a field-programmable gate array (FPGA), as an example. As described in detail in FIGS. 3A and 3B below, the control circuit 46 can be configured to cause the high-FOM switching path SP.sub.2 to be switched on earlier than the low-FOM switching path SP.sub.1 in a switch-on operation and to cause the high-FOM switching path SP.sub.2 to be switched off later than the low-FOM switching path SP.sub.1 in a switch-off operation.

(27) In examples discussed herein, the switch-on operation refers to an operation to close both the low-FOM switching path SP.sub.1 and the high-FOM switching path SP.sub.2. Specifically, the low-FOM switching path SP.sub.1 is considered as being closed when the first low-FOM switch 40 is closed, and the high-FOM switching path SP.sub.2 is considered as being closed when both the second low-FOM switch 42 and the high-FOM switch 44 are closed. In contrast, the switch-off operation refers to an operation to open both the low-FOM switching path SP.sub.1 and the high-FOM switching path SP.sub.2. Specifically, the low-FOM switching path SP.sub.1 is considered as being open when the first low-FOM switch 40 is open, and the high-FOM switching path SP.sub.2 is considered as being open when at least one of the second low-FOM switch 42 and the high-FOM switch 44 is open.

(28) FIG. 3A is a graphic diagram providing an exemplary illustration of the RF switching circuit 30 of FIG. 2 configured to perform switch-on and switch-off operations based on one embodiment of the present disclosure. In examples discussed herein, the RF switching circuit 30 is performing the switch-on operation between time T.sub.0 and T.sub.3 and the switch-off operation between time T.sub.3 and T.sub.5.

(29) Prior to the switch-on operation, the first low-FOM switch 40, the second low-FOM switch 42, and the high-FOM switch 44 are all in an “open” state. In this regard, the first low-FOM switch 40 and the second low-FOM switch 42 each exhibit the off-capacitance C.sub.OFFL, and the high-FOM switch 44 exhibits the off-capacitance C.sub.OFFH. Accordingly, the low-FOM switching path SP1 and the high-FOM switching path SP2 can have respective off-capacitances C.sub.OFF-SP1 and C.sub.OFF-SP2 as expressed in equations (Eq. 1.1 and 12) below.
C.sub.OFF-SP1=C.sub.OFFL  (Eq. 1.1)
C.sub.OFF-SP2=1/[(1/C.sub.OFFH)+(1/C.sub.OFFL)]  (Eq. 1.2)

(30) Accordingly, the RF switching circuit 30 can have an overall off-capacitance C.sub.OFF-ALL as expressed in equation (Eq. 1.3) below.
C.sub.OFF-ALL=C.sub.OFFL+1/[(1/C.sub.OFFH)+(1/C.sub.OFFL)]  (Eq. 1.3)

(31) At time T.sub.0 (also referred to as “first switch-on time” herein), the control circuit 46 toggles the second low-FOM switch 42 from the “open” state to a “closed” state such that the second low-FOM switch 42 becomes fully closed at time T.sub.1 (also referred to as “second switch-on time” herein). In this regard, the duration from the time T.sub.0 to the time T.sub.1 may correspond to the switching duration (e.g., 10-25 μs) of the second low-FOM switch 42. Notably, the time T.sub.1 may correspond to a desired switch-on time of the RF switching circuit 30. As such, the control circuit 46 actually causes the second low-FOM switch 42 to close ahead of the desired switch-on time to help reduce overall response time of the RF switching circuit 30.

(32) At the time T.sub.1, which corresponds to the desired switch-on time of the RF switching circuit 30, the control circuit 46 concurrently toggles both the first low-FOM switch 40 and the high-FOM switch 44 from the “open” state to the “closed” state. According to earlier discussions, the high-FOM switch 44 has a shorter switching duration than the first low-FOM switch 40. Therefore, the high-FOM switch 44 becomes fully closed at time T.sub.ON, while the first low-FOM switch 40 is still in the transition from the “open” state to the “closed” state. In this regard, the duration from the time T.sub.1 to the time T.sub.ON may correspond to the switching duration (e.g., 0.2 μs) of the high-FOM switch 44. As a result, the high-FOM switching path SP.sub.2 is switched on at the time T.sub.ON. Accordingly, the RF signal 34 can pass from the signal input 36 to the signal output 38 via the high-FOM switching path SP.sub.2. As both the high-FOM switch 44 and the second low-FOM switch 42 are in the “closed” state, the high-FOM switching path SP.sub.2 exhibits a respective on-resistance R.sub.ON-SP2 as expressed in equation (Eq. 2) below.
R.sub.ON-SP2=R.sub.ONH+R.sub.ONL  (Eq. 2)

(33) Accordingly, the high-FOM switching path SP.sub.2 can correspond to a respective FOM.sub.SP2 (also referred as “second FOM”) as expressed in equation (Eq. 3.1) below.
FOM.sub.SP2=R.sub.ON-SP2*C.sub.OFF-SP2  (Eq. 3.1)

(34) Thus, according to equations (Eq. 1.2, 2, and 3.1), the FOM.sub.SP2 can be further expressed as in equation (Eq. 3.2) below.

(35) $\begin{array}{cc}\begin{array}{cc}{\mathrm{FOM}}_{\mathrm{SP}2}=& \left(R_{\mathrm{ONH}}+R_{\mathrm{ONL}}\right)*1\text{/}[\left(1\text{/}{C}_{\mathrm{OFFH}}\right)+\\ & \left(1\text{/}{C}_{\mathrm{OFFL}}\right)]\\ =& \left(R_{\mathrm{ONH}}+R_{\mathrm{ONL}}\right)*C_{\mathrm{OFFH}}*C_{\mathrm{OFFL}}\text{/}\\ & \left(C_{\mathrm{OFFH}}+C_{\mathrm{OFFL}}\right)\end{array}& \left(\mathrm{Eq}.3.2\right)\end{array}$

(36) At the time T.sub.2, the first low-FOM switch 40 becomes fully closed. Accordingly, the low-FOM switching path SP.sub.1 is switched on. In this regard, the duration from the time T.sub.1 to the time T.sub.2 may correspond to the switching duration (e.g., 10-25 μs) of the first low-FOM switch 40. In this regard, the low-FOM switching path SP.sub.1 exhibits a respective on-resistance R.sub.ON-SP1 and a respective FOM.sub.SP1 (also referred to as “first FOM”) as expressed in equations (Eq. 4.1 and 4.2) below.
R.sub.ON-SP1=R.sub.ONL  (Eq. 4.1)
FOM.sub.SP1=R.sub.ONL*C.sub.OFFL  (Eq. 4.2)

(37) Based on equations (Eq. 2 and 4.1), the low-FOM switching path SP.sub.1 has a lower on-resistance than the high-FOM switching path SP.sub.2. As a result, at least a majority of the RF signal 34 will be passing from the signal input 36 to the signal output 38 via the low-FOM switching path SP.sub.1 as soon as the low-FOM switching path SP.sub.1 is switched on. By comparing equations (Eq. 3.2 and 4), it can be seen that the FOM.sub.SP2 of the high-FOM switching path SP.sub.2 is higher than the FOM.sub.SP1 of the low-FOM switching path SP.sub.1. In a non-limiting example, the FOM.sub.SP2 can be at least two times of the FOM.sub.SP1 (FOM.sub.SP2≥2 FOM.sub.SP1). For example, the FOM.sub.SP1 can be 40 fs and the FOM.sub.SP2 can be 100 fs. As such, the RF switching circuit 30 temporarily exhibits the higher FOM.sub.SP2 between the time T.sub.ON and the time T.sub.2 and will exhibit the lower FOM.sub.SP1 at the time T.sub.2. In this regard, the RF switching circuit 30 can achieve the shorter switching duration between the time T.sub.1 and the time T.sub.ON at an expense of the temporarily higher FOM.sub.SP2 between the time T.sub.ON and the time T.sub.2.

(38) As both the low-FOM switching path SP.sub.1 and the high-FOM switching path SP.sub.2 are switched on, the RF switching circuit 30 can exhibit an overall on-resistance R.sub.ON-ALL as expressed in equation (Eq. 5) below.
R.sub.ON-ALL=(1/R.sub.ONL)+1/(R.sub.ONL+R.sub.ONH)  (Eq. 5)

(39) Thus, based on equations (Eq. 1.3 and 5), the RF switching circuit 30 can have an overall FOM.sub.ALL as expressed in equation (Eq. 6) below.

(40) $\begin{array}{cc}\begin{array}{cc}{\mathrm{FOM}}_{\mathrm{ALL}}=& R_{\mathrm{ON}\text{-}\mathrm{ALL}}*C_{\mathrm{OFF}\text{-}\mathrm{ALL}}\\ =& \left\{\left(1\text{/}{R}_{\mathrm{ONL}}\right)+1\text{/}\left(R_{\mathrm{ONL}}+R_{\mathrm{ONH}}\right)\right\}*\\ & \left\{C_{\mathrm{OFFL}}+1\text{/}\left[\left(1\text{/}{C}_{\mathrm{OFFH}}\right)+\left(1\text{/}{C}_{\mathrm{OFFL}}\right)\right]\right\}\end{array}& \left(\mathrm{Eq}.6\right)\end{array}$

(41) Prior to the switch-off operation performed between time T.sub.3 and T.sub.5, the first low-FOM switch 40, the second low-FOM switch 42, and the high-FOM switch 44 are all in a “closed” state. As such, the RF signal 34 is passed from the signal input 36 to the signal output 38 via the low-FOM switching path SP.sub.1 and the RF switching circuit 30 thus exhibiting the lower FOM.sub.SP1 between the time T.sub.2 and the time T.sub.3.

(42) At the time T.sub.3 (also referred to as “first switch-off time” herein), the control circuit 46 toggles the first low-FOM switch 40 from the “closed” state to the “open” state such that the first low-FOM switch 40 becomes fully open at time T.sub.4 (also referred to as “second switch-off time” herein). In this regard, the duration from the time T.sub.3 to the time T.sub.4 may correspond to the switching duration (e.g., 10-25 μs) of the first low-FOM switch 40. Notably, the time T.sub.4 may correspond to a desired switch-off time of the RF switching circuit 30. As such, the control circuit 46 actually causes the first low-FOM switch 40 to close ahead of the desired switch-off time to help reduce overall response time of the RF switching circuit 30.

(43) By toggling the first low-FOM switch 40, the low-FOM switching path SP.sub.1 is switched off. As such, the RF switching circuit 30 reroutes the RF signal 34 to pass from the signal input 36 to the signal output 38 via the high-FOM switching path SP.sub.2.

(44) At the time T.sub.4, the control circuit 46 concurrently toggles both the second low-FOM switch 42 and the high-FOM switch 44 from the “closed” state to the “open” state. According to earlier discussions, the high-FOM switch 44 has a shorter switching duration than the second low-FOM switch 42. Therefore, the high-FOM switch 44 becomes fully open at time T.sub.OFF, while the second low-FOM switch 42 is still in the transition from the “closed” state to the “open” state. In this regard, the duration from the time T.sub.4 to the time T.sub.OFF may correspond to the switching duration (e.g., 0.2 μs) of the high-FOM switch 44. As the high-FOM switch 44 is open at the time T.sub.OFF, the high-FOM switching path SP.sub.2 is switched off and the RF signal 34 is blocked. In this regard, the RF switching circuit 30 exhibits the higher FOM.sub.SP2 between the time T.sub.3 and the time T.sub.OFF. In this regard, the RF switching circuit 30 temporarily exhibits the higher FOM.sub.SP2 between the time T.sub.3 and the time T.sub.OFF in exchange for the shorter switching duration between the time T.sub.4 and the time T.sub.OFF.

(45) At the time T.sub.5, the second low-FOM switch 42 also becomes fully closed. At this point, the RF switching circuit 30 is completed switched off.

(46) As discussed above, the RF switching circuit 30 is able to achieve the shorter switch-on and switch-off durations at the expense of exhibiting the higher FOM.sub.SP2 between the time T.sub.ON and the time T.sub.2 as well as between the time T.sub.3 and the time T.sub.OFF. As such, it may be desirable to further reduce the duration of the higher FOM.sub.SP2 in the RF switching circuit 30, while maintaining the shorter switch-on and switch-off durations.

(47) In this regard, FIG. 3B is a graphic diagram providing an exemplary illustration of the RF switching circuit 30 of FIG. 2 configured to perform switch-on and switch-off operations based on another embodiment of the present disclosure. Prior to the switch-on operation, the first low-FOM switch 40, the second low-FOM switch 42, and the high-FOM switch 44 are all in an “open” state.

(48) At time T.sub.0 (also referred to as “first switch-on time” herein) the control circuit 46 toggles the second low-FOM switch 42 from the “open” state to a “closed” state such that the second low-FOM switch 42 becomes fully closed at time T.sub.1 (also referred to as “second switch-on time” herein). In this regard, the duration from the time T.sub.0 to the time T.sub.1 may correspond to the switching duration (e.g., 10-25 μs) of the second low-FOM switch 42. Notably, the time T.sub.1 may correspond to a desired switch-on time of the RF switching circuit 30. As such, the control circuit 46 actually causes the second low-FOM switch 42 to close ahead of the desired switch-on time to help reduce overall response time of the RF switching circuit 30.

(49) At time T.sub.0-1 (also referred to as “third switch-on time” herein), which is in between the time T.sub.0 and the time T.sub.1, the control circuit 46 begins to toggle the first low-FOM switch 40 from the “open” state to the “closed” state. Notably, the time T.sub.0-1 is so determined to prevent the first low-FOM switch 40 from becoming fully closed at the time T.sub.1. In this regard, the first low-FOM switch 40 remains in the “open” state at the time T.sub.1.

(50) At the time T.sub.1, which corresponds to the desired switch-on time of the RF switching circuit 30, the control circuit 46 toggles the high-FOM switch 44 from the “open” state to the “closed” state. According to earlier discussions, the high-FOM switch 44 has a shorter switching duration than the first low-FOM switch 40. Therefore, the high-FOM switch 44 becomes fully closed at time T.sub.ON, while the first low-FOM switch 40 is still in the transition from the “open” state to the “closed” state. In this regard, the duration from the time T.sub.1 to the time T.sub.ON may correspond to the switching duration (e.g., 0.2 μs) of the high-FOM switch 44. As a result, the high-FOM switching path SP.sub.2 is switched on at the time T.sub.ON. Accordingly, the RF signal 34 can pass from the signal input 36 to the signal output 38 via the high-FOM switching path SP.sub.2 and the RF switching circuit 30 exhibits the higher FOM.sub.SP2 at the time T.sub.ON.

(51) At the time T.sub.2, the first low-FOM switch 40 becomes fully closed and the low-FOM switching path SP.sub.1 is switched on. In this regard, at least a majority of the RF signal 34 will be passing from the signal input 36 to the signal output 38 via the low-FOM switching path SP.sub.1 as soon as the low-FOM switching path SP.sub.1 is switched on. As a result, the RF switching circuit 30 exhibits the lower FOM.sub.SP1 at the time T.sub.2. Notably, since the control circuit 46 begins to toggle the first low-FOM switch 40 ahead of the desired switch-on the time T.sub.1, the first low-FOM switch 40 can thus become fully closed earlier than the first low-FOM switch 40 does in FIG. 3A. As such, the duration in which the RF switching circuit 30 exhibits the higher FOM.sub.SP2 can be shortened.

(52) Prior to the switch-off operation performed between the time T.sub.3 and time T.sub.5, the first low-FOM switch 40, the second low-FOM switch 42, and the high-FOM switch 44 are all in a “closed” state. As such, the RF signal 34 is passed from the signal input 36 to the signal output 38 via the low-FOM switching path SP.sub.1 and the RF switching circuit thus exhibiting the lower FOM.sub.SP1 between the time T.sub.2 and the time T.sub.3.

(53) At the time T.sub.3 (also referred to as “first switch-off time” herein), the control circuit 46 toggles the first low-FOM switch 40 from the “closed” state to the “open” state such that the first low-FOM switch 40 becomes fully open at time T.sub.4 (also referred to as “second switch-off time” herein). Notably, the time T.sub.3 in FIG. 3B is delayed from the time T.sub.3 in FIG. 3A. Accordingly, the time T.sub.4 in FIG. 3B is also delayed from the time T.sub.4 in FIG. 3A.

(54) The control circuit 46 concurrently toggles the high-FOM switch 44 and the second low-FOM switch 42 at time T.sub.3-4 (also referred to as “third switch-off time” herein) that is in between of the time T.sub.3 and the time T.sub.4. Notably, the time T.sub.3-4 may correspond to a desired switch-off time of the RF switching circuit 30. The time T.sub.3-4 may be so determined to prevent the first low-FOM switch 40 from becoming fully open at the time T.sub.3-4. In other words, the first low-FOM switch 40, and thus the low-FOM switching path SP.sub.1, remains closed at the time T.sub.3-4 to pass the RF signal 34. As a result, the RF switching circuit 30 would exhibit the lower FOM.sub.SP1 longer than in FIG. 3A.

(55) At the time T.sub.3-4, the control circuit 46 concurrently toggles both the second low-FOM switch 42 and the high-FOM switch 44 from the “closed” state to the “open” state. According to earlier discussions, the high-FOM switch 44 has a shorter switching duration than the second low-FOM switch 42. Therefore, the high-FOM switch 44 becomes fully open at time T.sub.OFF, while the second low-FOM switch 42 is still in the transition from the “closed” state to the “open” state. In this regard, the duration from the time T.sub.3-4 to the time T.sub.OFF may correspond to the switching duration (e.g., 0.2 μs) of the high-FOM switch 44. As the high-FOM switch 44 is open at the time T.sub.OFF, the high-FOM switching path SP.sub.2 is switched off and the RF signal 34 is blocked. In this regard, the RF switching circuit 30 exhibits the higher FOM.sub.SP2 between the time T.sub.3-4 and the time T.sub.OFF, which is shorter than the higher FOM.sub.SP2 exhibited between the time T.sub.3 and the time T.sub.4 in FIG. 3A. At the time T.sub.5, the second low-FOM switch 42 also becomes fully closed. At this point, the RF switching circuit 30 is completed switched off.

(56) As mentioned earlier, the high-FOM switch 44 in the RF switching circuit 30 can be an SOI switch or any other type of switch that exhibits a shorter switching duration. FIG. 4 is a schematic diagram of an exemplary high-FOM switch 48 that may be provided in the RF switching circuit 30 of FIG. 2 as the high-FOM switch 44. Common elements between FIGS. 2 and 4 are shown therein with common element numbers and will not be re-described herein.

(57) In a non-limiting example, the high-FOM switch 48 includes an SOI switch 50, which may be identical to the SOI switch 20 of FIG. 1B. The high-FOM switch 48 may also include a SOI shunt switch 52 coupled between the signal output 38 and a ground GND. Both the SOI switch 50 and the SOI shunt switch 52 may be closed by the operating voltage V.sub.OP2. In a non-limiting example, the high-FOM switch 48 may be provided in a complementary metal-oxide semiconductor (CMOS) die 54.

(58) The CMOS die 54 may be further configured to incorporate a charge pump 56. The charge pump 56 may be configured to generate the operating voltage V.sub.OP1 for closing the first low-FOM switch 40 and the second low-FOM switch 42. The charge pump 56 may also be configured to generate the operating voltage V.sub.OP2 for closing the SOI switch 50 and the SOI shunt switch 52.

(59) Although the RF switching circuit 30 of FIG. 2 is illustrated as a single-pole single-through (SPST) switching circuit, it should be appreciated that the RF switching circuit 30 can be configured to operate as a single-pole multi-throw (SPMT) switching circuit as well. In this regard, FIG. 5 is a schematic diagram of an exemplary SPMT RF switching circuit 58 configured according to an embodiment of the present disclosure. Common elements between FIGS. 2 and 5 are shown therein with common element numbers and will not be re-described herein.

(60) In a non-limiting example, the SPMT RF switching circuit 58 includes at least one second signal output 60 to output the RF signal 34. The SPMT RF switching circuit 58 also includes at least one second hybrid switch circuit 62 coupled between the signal input 36 and the second signal output 60. The second hybrid switch circuit 62 may be identical to the hybrid switch circuit 32.

(61) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.