METHOD FOR MANUFACTURING A HIGH-VOLTAGE FINFET DEVICE HAVING LDMOS STRUCTURE

Abstract

A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

Claims

1. A method for manufacturing a high-voltage FinFET device having LDMOS structure, comprising steps of: providing a substrate with a fin structure thereon, the fin structure has a first-type well region and a second-type well region adjacent to the first-type well region; forming a trench in the first-type well region of the fin structure and separating the fin structure into a first part and a second part; forming a shallow trench isolation (STI) structure in the trench; forming a first polycrystalline silicon gate stack structure in the trench and on the STI structure, and a second polycrystalline silicon gate stack structure on the fin structure, the second polycrystalline silicon gate stack being separated from the first polycrystalline silicon gate stack structure; forming a plurality of discontinuous openings on an exposed portion of the fin structure in the first part in the first-type well region and in the second part in the second-type well region; growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain doped layer in the first part in the first-type well region and a source doped layer in the second part in the second-type well region; and performing a replacement metal gate (RMG) process to replace the first polycrystalline silicon gate stack structure and the second polycrystalline silicon gate stack structure with a first metal gate stack structure and a second metal stack structure respectively, wherein the first metal gate stack structure is disposed in the trench in the first-type well region and positioned between the drain doped layer and the second metal gate stack structure, the second metal gate stack structure disposed in the second-type well region and positioned between the source doped layer and the first metal gate stack structure.

2. The method as claimed in claim 1, wherein the first polycrystalline silicon gate stack structure and the second polycrystalline silicon gate stack structure include a gate oxide layer and a polycrystalline silicon gate layer respectively, the replacement metal gate (RMG) process comprises: removing the polycrystalline silicon gate layer of the first polycrystalline silicon gate stack structure and polycrystalline silicon gate layer of the second polycrystalline silicon gate stack structure, to form a groove; forming a high-k dielectric material layer in the groove; and forming a metal gate material layer on the high-k dielectric material layer in the groove.

3. The method as claimed in claim 2, wherein the material of the metal gate material layer is Aluminum or Wolfram, and the material of the high dielectric material layer is Hafnium Oxide (HfO.sub.2).

4. The method as claimed in claim 1, wherein the second polycrystalline silicon gate stack structure is located on the fin structure across the first-type well region and the second-type well region.

5. The method as claimed in claim 1, in the step of forming the first polycrystalline silicon gate stack structure and the second polycrystalline silicon gate stack structure, further comprising: forming a plurality of third polycrystalline silicon gate stack structures on the fin structure on the fin structure in the first part and in the second-type well region, wherein the third polycrystalline silicon gate stack structures individually comprise a gate oxidizing layer and a polycrystalline silicon gate layer.

6. The method as claimed in claim 5, wherein the step of performing the RMG process is further to replace the polycrystalline silicon gate layers of the third polycrystalline silicon gate stack structures with a metal gate material layer and a high-k dielectric material layer surrounding the metal gate material layer to replace the third polycrystalline silicon gate stack structure with a third metal gate stack structure.

7. The method as claimed in claim 6, wherein the source doped layer is positioned between the third metal gate stack structure and the second metal gate stack structure, the drain doped layer is positioned between the first metal gate stack structure and the other third metal gate stack structure.

8. The method as claimed in claim 1, wherein in the step of doping the epitaxial material layer doping process, further includes forming a plurality of discontinuous first type doped layers, at least one of the first type doped layers disposes in the first-type well region and between the drain doped layer and the source doped layer.

9. The method as claimed in claim 8, wherein the first-type well region is a N-type well region, the second-type well region is a P-type well region, and the first type doped layer, the drain doped layer and the source doped layer are P-type doped layers.

10. The method as claimed in claim 9, wherein the epitaxial material layer is a Phosphorus-doped-Silicon epitaxial layer.

11. The method as claimed in claim 8, wherein the first-type well region is a P-type well region, the second-type well region is a N-type well region, and the first type doped layer, the drain doped layer and the source doped layer are N-type doped layers.

12. The method as claimed in claim 11, wherein the epitaxial material layer is a Silicon-Germanium epitaxial layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIGS. 1 A to 1J are a plurality of diagrams of a method for manufacturing a high-voltage FinFET device having LDMOS structure according to an embodiment of the present invention.

[0015] FIG. 2 is a diagram of a high-voltage FinFET device having LDMOS structure according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENT

[0016] The present invention will be apparent to those skilled in the art by reading the following description thereof, with reference to the attached drawings.

[0017] FIGS. 1A to 1J are a plurality of diagrams of a method for manufacturing a high-voltage FinFET device having LDMOS structure according to an embodiment of the present invention. The detailed steps of the method for manufacturing the high-voltage FinFET device having LDMOS structure will be described as follows.

[0018] Referring to FIG. 1A, firstly, a substrate 110 is provided with (at least one) a Fin structure 120 thereon. The Fin structure 120 has a first-type well region Z1 and a second-type well region Z2 adjacent to the first type well region Z1. The substrate 110 can be, for example, a semiconductor substrate.

[0019] Referring to FIG. 1B and 1C, then, a trench ST is formed on the Fin structure 120 by means of photo-mask process and etching process. The trench ST separates the Fin structure 120 into a first part 122 and a second part 124, in which the trench ST is located in the first-type well region Z1 of the fin structure 120 (FIG. 1B). Therefore, the first part 122 can be completely located within the first-type well region Z1, the second part 124 is located partially in the first well region Z1 and entirely within the second well region Z2. Then, a shallow trench isolation (STI) structure 130 is formed in the trench ST, wherein the shallow trench isolation structure 130 only fills up a (partial) (bottom) portion of the space of the trench ST (FIG. 1C).

[0020] Referring to FIG. 1D, after the process of forming a shallow trench isolation structure 130 in the trench ST, then a first polycrystalline silicon gate stack structure 142, a second polycrystalline silicon gate stack structure 144 and a plurality of third polycrystalline silicon gate stack structures 146 and 149 are formed on the Fin structure 120. The first polycrystalline silicon gate stack structure 142 is located in the first-type well region Z1. The second polycrystalline silicon gate stack structure 144 is located in and across both the first-type well region Z1 and the second-type well region Z2. The third polycrystalline silicon gate stack structure 146 is located in the first-type well region Z1, and the third polycrystalline silicon gate stack structures 149 are located in the second type well region Z2. The third polycrystalline silicon gate stack structure 146 is located on a side of the first polycrystalline silicon gate stack structure 142 away from the second polycrystalline silicon gate stack structure 144; and the third polycrystalline silicon gate stack structures 149 are located on a side of the second polycrystalline silicon gate stack structure 144 away from the first polycrystalline silicon gate stack structure 142. Moreover, there is no third polycrystalline silicon gate stack structure formed in between the first polycrystalline silicon gate stack structure 142 and the second polycrystalline silicon gate stack structure 144 as shown in FIG. 1D; however, in other embodiments of the present invention, at least one third polycrystalline silicon gate stack structure can be formed therein-between.

[0021] Referring to FIG. 1D, the method of forming the first polycrystalline silicon gate stack structure 142 includes the step of: firstly, forming a gate oxide layer 1422 conformally in the trench ST and on the shallow trench isolation structure 130; and then forming a polycrystalline silicon gate layer 1424 on the gate oxide layer 1422. The polycrystalline silicon gate layer 1424 is not only filling up the trench ST, but also disposed above the Fin structure 120. Moreover, because the first polycrystalline silicon gate stack structure 142 is formed in the trench ST and disposed on the shallow trench isolation structure 130, the first polycrystalline silicon gate stack structure 142 has a vertical extension portion P1 and a horizontal extension portion P2. The vertical extension portion P1 fills up the trench ST and is positioned on the shallow trench isolation structure 130. The horizontal extension portion P2 is positioned on the Fin structure 120, and an extending direction of the horizontal extension portion P2 is perpendicular to an extending direction of the Fin structure 120, as similar to that of a conventional FinFET having a gate electrode formed across on a fin, and the two (namely, the gate electrode and the fin) having two extending directions perpendicular to each other.

[0022] Moreover, the second polycrystalline silicon gate stack structure 144 and the third polycrystalline silicon gate stack structures 146 and 149 respectively include a gate oxide layer 141 and a polycrystalline silicon gate layer 148, in which the gate oxide layer 141 is formed on the Fin structure 120 and the polycrystalline silicon gate layer 148 is formed on the gate oxide layer 141. Furthermore, each of the second polycrystalline silicon gate stack structure 144 and the plurality of the third polycrystalline silicon gate stack structures 146 and 149 only have a horizontal extension portion P3 respectively, wherein an extending direction of the horizontal extension portion P3 is also perpendicular to the extending direction of the Fin structure 120.

[0023] Referring to Fig. 1E and FIG. 1F, after forming the first polycrystalline silicon gate stack structure 142, the second polycrystalline silicon gate stack structure 144 and the third polycrystalline silicon gate stack structures 146 and 149, a plurality of (discontinuous) openings OP1 (FIG. 1E) are formed on the Fin structure 120 by removing a portion of the Fin structure 120 not covered by the first polycrystalline silicon gate stack structure 142, the second polycrystalline silicon gate stack structure 144 and the third polycrystalline silicon gate stack structures 146 and 149. Then, a plurality of (discontinuous) epitaxial material layers 152, 154, 156 are grown in the plurality of openings OP1. Upper surfaces of the epitaxial material layers 152, 154, 156 are flush with the lower surface of the gate oxide layer 141 (FIG. 1F).

[0024] Referring to FIG. 1G, after forming the epitaxial material layer 152, 154, 156, then a doping process is performed toward the epitaxial material layer 152, 154, 156 in the openings OP1 in order to form a drain doped layer D1 from the epitaxial material layer 152 disposed in the first type well region Z1, a source doped layer S1 from the epitaxial material layer 154 disposed in the second type well region Z2, and a first type doped layer DP1 from the plurality of (discontinuous) epitaxial material layers 156. In the description of the embodiment of the present invention hereafter, the first polycrystalline silicon gate stack structure 142 is also referred to as a first dummy gate 142, the second polycrystalline silicon gate stack structure 144 is also referred to as a working gate 144, and the third polycrystalline silicon gate stack structures 146, 149 are also referred to the second dummy gates 146, 149. Then, an isolation layer 160 is formed on the epitaxial material layer 152, 154, 156. The upper surface of the isolation layer 160 is flush with the upper surfaces of the working gate 144, the first dummy gate 142, and the second dummy gates 146 and 149. Wherein the space between the drain doped layer D1 and the source doped layer S1 includes at least one first type doped layer DP1. The first type doped layer DP1 positioned between the drain doped layer D1 and the source doped layer S1 is located in the first type well region Z1. Referring to FIG. 1G, one first type doped layer DP1 is disposed between the drain doped layer D1 and the source doped layer S1, and it is just an example embodiment for illustration. However, in an alternative embodiment, a plurality of the first type doped layers DP1 disposed between the drain doped layer D1 and the source doped layer S1 is also feasible. It is not intended to limit the invention to the precise form disclosed.

[0025] Referring to FIG. 1H to FIG. 1J, after forming the drain doped layer D1, the source doped layer S1 and the plurality of first type doped layer DP1, then performing a RMG (replacement metal gate) process, in order to replace the first polycrystalline silicon gate stack structure 142 with the first metal gate stack structure 192, replace the second polycrystalline silicon gate stack structure 144 with the second metal gate stack structure 194, and replace the third polycrystalline silicon gate stack structures 146, 149 with the third metal gate stack structures 196, 198.

[0026] Referring to FIG. 1H to FIG. 1J, the above RMG process include following steps: firstly, removing the polycrystalline silicon gate layer 1424 of the first polycrystalline silicon gate stack structure 142 to form a groove OP2, and removing the polycrystalline silicon gate layer 148 of the second polycrystalline silicon gate stack structure 144 and the third polycrystalline silicon gate stack structures 146, 149 to form a plurality of grooves OP3 (FIG. 1H). Meanwhile, it is optionally to remove the gate oxide layers 1422, 141 positioned under the polycrystalline silicon gate layers 1424, 148, respectively, in the RMG process. The present invention takes FIG. 1H as an example or exemplified embodiment to describe the RMG process without removing the gate oxide layers 1422, 141. However, it is not intended to limit the invention to the precise form disclosed. If the gate oxide layers 1422, 141 are removed in the RMG process, then after removing the gate oxide layers 1422, 141, either a thinner or thicker gate oxide layer is further deposited on the Fin structure 120 where the gate oxide layers 1422, 141 is as shown in FIG. 1F.

[0027] After removing the polycrystalline silicon gate layers 1424, 148, then a high-k dielectric material layer 172 is formed conformally on the inner wall of the groove OP2, and a plurality of high-k dielectric material layers 174 are formed conformally on the inner wall of the grooves OP3 respectively (FIG. 1I). Then, a metal gate material layer 182 is formed in the groove OP2 on the high-k dielectric material layer 172, and meanwhile a plurality of metal gate material layers 184 are formed in the grooves OP3 respecitvely on the high-k dielectric material layers 174 (FIG. 1J). The RMG process is finished when completing the first metal gate stack structure 192, the second metal gate stack structure 194 and the third metal gate stack structures 196, 198. The material of the metal gate material layers 182, 184 can be, for example, Aluminum or Wolfram. The material of the high-k dielectric material layers 172, 174 can be, for example, dHfO.sub.2 (Hafnium Oxide).

[0028] If the first type well region Z1 is a N-type well region, the second type well region Z2 is a P-type well region, and the first type doped layer DP1, the drain doped layer D1 and the source doped layer S1 are N-type doped layers, and the epitaxial material layers 152, 154, 156 are Phosphorus-doped-Silicon epitaxial layers, then the present invention defines the high-voltage FinFET device as a N-type high-voltage FinFET device.

[0029] However, If the first type well region Z1 is a P-type well region, the second type well region Z2 is a N-type well region, and the first type doped layer DP1, the drain doped layer D1 and the source doped layer S1 are P-type doped layer, and the epitaxial material layers 152, 154, 156 are Silicon-Germanium epitaxial layers, then the present invention defines the high-voltage FinFET device as a P-type high-voltage FinFET device.

[0030] The first metal gate stack structure 192 includes the gate oxide layer 1422, the high-k dielectric material layer 172 and the metal gate material layer 182. The second metal gate stack structure 194 and the third metal gate stack structures 196, 198 individually include the gate oxide layer 141, the high dielectric material layer 174 and the metal gate material layer 184. The first metal gate stack structure 192 is disposed between the drain doped layer D1 and the second metal gate stack structure 194. The second metal gate stack structure 194 is disposed between the source doped layer S1 and the first metal gate stack structure 192.

[0031] Moreover, referring to FIG. 1J, the source doped layer S1 is disposed between the third metal gate stack structure 198 and the second metal gate stack structure 194. The drain doped layer D1 is disposed between the first metal gate stack structure 192 and the third metal gate stack structure 196. Furthermore, the second metal gate stack structure 194 and the first metal gate stack structure 192 can be partitioned by zero, one, or a plurality of the third metal gate stack structures 196. Referring to FIG. 1J, in the space between the second metal gate stack structure 194 and the first metal gate stack structure 192, there is no third metal gate stack structure being disposed in this space, the present invention take it as an example for illustration. However, it is not intended to limit the invention to the precise form disclosed.

[0032] Noticeably, referring to FIG. 1G1J, between the second metal gate stack structure 194 and the first metal gate stack structure 192 is spaced out by at least one of the first type doped layer DP1, formed from the epitaxial material layer 156, and the isolation layer 160 disposed thereon (FIG. 1G).

[0033] On the operation of the high-voltage FinFET device having LDMOS structure, because the second metal gate stack structure 194 spans on the first type well region Z1 and the second type well region Z2, the second metal gate stack structure 194 is generally functioned as a working gate. The first gate stack structure 192 and the third metal gate stack structure 196 are functioned as a dummy gate structure. For promoting the ability of bearable voltage of the drain doped layer D1, the present invention provides a solution of having at least one first metal gate stack structure 192 and a shallow trench isolation 130 therebeneath, disposed between the drain doped layer D1 and the working gate (the second metal gate stack structure 194), and having the first metal gate structure 192 disposed on and contacting with one side of the drain doped layer D1. Then the present invention can promote the ability of bearable voltage of the drain doped layer D1 by virtue of the shallow trench isolation structure 130 beneath the first metal gate stack structure 192.

[0034] FIG. 2 is the sectional view of a high-voltage FinFET device having LDMOS structure according to an embodiment of the present invention. The embodiment of present invention provides a high-voltage FinFET device 200 having LDMOS structure which includes at least one Fin structure 220, a shallow trench isolation structure 230, a drain doped layer 252, a source doped layer 254, a plurality of first type doped layers 256, 258, an isolation layer 260, a first dummy gate 292, a working gate 294, a plurality of second dummy gates 296, 298.

[0035] Referring to FIG. 2, the Fin structure 220 is disposed on the substrate 210, the Fin structure 220 has a first type well region Z1 and the second type well region Z2 adjacent to the first type well region Z1. Furthermore, the Fin structure 220 further include a first part 222 and a second part 224, wherein the first part 222 and the second part 224 is spaced apart by a trench ST. The trench ST is located in the first type well region Z1 of the fin structure 220. The shallow trench isolation structure 230 is disposed in the trench ST.

[0036] Referring to FIG. 2, the drain doped layer 252, the source doped layer 254, the plurality of the first type doped layers 256, 258 are disposed on the Fin structure 220, wherein at least one or a plurality of the first type doped layers 256 is disposed between the drain doped layer 252 and the source doped layer 254. In FIG. 2, one first type doped layer 256 is disposed between the drain doped layer 252 and the source doped layer 254, and it is used as an example to illustrate the present invention. However, it is not intended to limit the invention to the precise form disclosed.

[0037] The first type doped layer 256, the drain doped layer 252 and the source doped layer 254 are spaced from each other by the Fin structure 220. In addition, the drain doped layer 252 and at least one first type doped layer 256 are disposed in the first type well region Z1 on the Fin structure 220, the source doped layer 254 and the first type doped layers 258 are disposed in the second type well region Z2 on the Fin structure 220. The drain doped layer 252 is disposed on the first part 222 of the Fin structure 220. The first type doped layers 256, 258, the source doped layer 254 are all disposed on the second part 224 of the Fin structure 220.

[0038] Referring to FIG. 2, the working gate 294, the first dummy gate 292 and the second dummy gates 296, 298 are all disposed on the Fin structure 220. Moreover, an isolation layer 260 is disposed between the working gate 294 and the first dummy gate 292, between the first dummy gate 292 and the second dummy gate 296, and between the working gate 294 and the second dummy gate 298, respectively. Moreover, the isolation layer 260 is disposed on the drain doped layer 252, the source doped layer 254 and the first type doped layers 256, 258, individually. The first dummy gate 292 is adjacent to the isolation layer 260 positioned on the drain doped layer 252, the working gate 294 is adjacent to the isolation layer 260 positioned on the source doped layer 254.

[0039] The working gate 294 spans in both the first type well region Z1 and the second type well region Z2, and is positioned on the Fin structure 220. The first dummy gate 292 is disposed on the shallow trench isolation structure 230, and disposed in the trench ST the first type well region Z1. The second dummy gate 296 is positioned in the first type well region Z1. The second dummy gate 298 is positioned in the second type well region Z2. The first dummy gate 292 is positioned between the drain doped layer 252 and the working gate 294. The working gate 294 is positioned between the first dummy gate 292 and the source doped layer 254. The source doped layer 254 is positioned between the second dummy gate 298 and the working gate 294. The drain doped layer 252 is positioned between the first dummy gate 292 and the second dummy gate 296.

[0040] The first dummy gate 292 has a vertical extension portion P1 and a horizontal extension portion P2, wherein the horizontal extension portion P2 is disposed on both the first part 222 and the second part 224 of the Fin structure 220, the vertical extension portion P1 is disposed in the trench ST and located on the shallow trench isolation structure 230. The working gate 294 and the plurality of second dummy gates 296, 298 only include a horizontal extension portion P3, respectively. In addition, the first dummy gate 292 include a gate oxide layer 2422, a metal gate material layer 282 and a high dielectric material layer 272 surrounding the metal gate material layer 282 and covering conformally on a side of the metal gate material layer 282 adjacent to the Fin structure 220.

[0041] The gate oxide layer 2422 is disposed on the Fin structure 220. The working gate 294 and the plurality of second dummy gates 296, 298 individually include a gate oxide layer 241, a metal gate material layer 284 and a high-k dielectric material layer 274 surrounding the metal gate material layer 284, wherein the gate oxide layer 241 is disposed on the Fin structure 220.

[0042] In addition, the material of the metal gate material layers 282, 284 can be, for example, Aluminum (Al) or Wolfram (W). The material of the high dielectric material layers 274, 284 can be, for example, Hafnium Oxide (HfO.sub.2).

[0043] Noticeably, if the high-voltage FinFET device 200 having LDMOS structure of the embodiment of present invention is defined as a N-type high-voltage FinFET, then the first type well region Z1 is a N-type well region, the second type well region Z2 is a P-type well region, the first type doped layer 256, 258, the drain doped layer 252 and the source doped layer 254 are N-type doped layer. The drain doped layer 252, the source doped layer 254 and the first type doped layers 256, 258 are Phosphorus-doped-Silicon epitaxial layer respectively.

[0044] Moreover, if the high-voltage FinFET device 200 having LDMOS structure of the embodiment of present invention is defined as a P-type high-voltage FinFET, then the first type well region Z1 is a P-type well region, the second type well region Z2 is a N-type well region, the first type doped layers 256, 258, the drain doped layer 252 and the source doped layer 254 are P-type doped layer. The drain doped layer 252, the source doped layer 254 and the first type doped layers 256, 258 are Silicon-Germanium epitaxial layer respectively.

[0045] In addition, referring to FIG. 2, because the high-voltage FinFET device 200 having LDMOS structure of the embodiment of present invention further includes a shallow trench isolation structure 230 disposed beneath the first dummy gate 292, which is between the drain doped layer 252 and the working gate 294, and neighboring/adjacent to the drain doped layer 252, it can not only widen the distance between the drain doped layer 252 and the source doped layer 254, but also promote the bearable voltage of the drain doped layer 252 by virtue of the shallow trench isolation structure 230.

[0046] Therefore, between the first dummy gate 292 and the working gate 294, zero, one or a plurality of the second dummy gates 296, 298 can be disposed. If there is a a second dummy gate 296 disposed between the first dummy gate 292 and the working gate 294, then the first dummy gate 292, the second dummy gate 296 and the working gate 294 are separated from each other by the isolation layer 260.

[0047] If there is no second dummy gate disposed between the first dummy gate 292 and the working gate 294, then the first dummy gate 292 and the working gate 294 are separated by the isolation layer 260. In FIG. 2, there is no second dummy gate being disposed between the first dummy gate 292 and the working gate 294, it is used as an example to illustrate the present invention. However, it is not intended to limit the invention to the precise form disclosed. Noticeably, if there is one or more second dummy gates 296 disposed between the first dummy gate 292 and the working gate 294, then the distance between the drain doped layer 252 and the source doped layer 254 will be wider, so as to correspondingly promote the bearable voltage of the drain doped layer 252.

[0048] As described above, the present invention provides a high-voltage FinFET device having LDMOS structure and method for manufacturing the same. By defining a shallow trench isolation structure beneath the first dummy gate, which is located between the drain doped layer and the working gate and adjacent to the drain doped layer, it can not only widen the distance between the drain doped layer and the source doped layer, but also promote the ability of raising the bearable voltage of the drain. Furthermore, because the first dummy gate, the working gate, the drain doped layer and the source doped layer are designed into the same high-voltage FinFET device, the present invention can avoid the problem of lowering device density.

[0049] The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. Such modifications and variations that may be apparent to those skilled in the art are intended to be included within the scope of this invention as defined by the accompanying claims.