AUTOMATIC GAIN COMPRESSION DETECTION AND GAIN CONTROL FOR ANALOG FRONT-END WITH NONLINEAR DISTORTION

Abstract

Methods and systems are provided for gain control in circuits. Gain applied in a circuit may be set to a baseline set gain. A first baseline parameter, associated with a first feature of a particular pattern of a signal at said baseline set gain, and a second baseline parameter, associated with a second feature of said particular pattern of the signal at said baseline set gain, may be determined. The gain is then set a current set gain, and a gain compression ratio may be determined based on one or more of said first baseline parameter, said second baseline parameter, a first current parameter associated with said first feature of at said current set gain, and a second current parameter associated with said second feature at said current set gain. Said current set gain may then be adjusted until said gain compression ratio reaches a predefined limit.

Claims

1-20. (canceled)

21. A method comprising: setting a gain applied in a circuit to a baseline set gain; determining a first baseline parameter associated with a first feature of a particular pattern of a signal at said baseline set gain, and a second baseline parameter associated with a second feature of said particular pattern of said signal at said baseline set gain; setting said gain to a current set gain that is different than said baseline set gain; determining a gain compression ratio based on one or more of said first baseline parameter, said second baseline parameter, a first current parameter associated with said first feature of said particular pattern at said current set gain, and a second current parameter associated with said second feature of said particular pattern at said current set gain; and adjusting said current set gain until said gain compression ratio reaches a predefined limit.

22. The method according to claim 21, wherein determining each one of said first baseline parameter, said second baseline parameter, said first current parameter, and said second current parameter comprises: determining each of a corresponding positive voltage and a corresponding negative voltage by adjusting a corresponding threshold voltage until a proportion of samples of said signal in a sampling period exceeding said threshold voltage reaches a target proportion.

23. The method according to claim 22, wherein a target proportion for each parameter associated with said first feature is different than a target proportion for a parameter associated with said second feature.

24. The method according to claim 21, wherein each one of said first baseline parameter, said second baseline parameter, said first current parameter, and said second current parameter comprises is a median value.

25. The method according to claim 21, wherein determining said gain compression ratio comprises: determining a compression-free estimate of said second current parameter without gain compression; and determining said gain compression ratio based on said compression-free estimate and said second current parameter.

26. The method according to claim 25, wherein said gain compression ratio is a quotient of said compression-free estimate of said second current parameter without gain compression and said second current parameter.

27. The method according to claim 25, wherein determining said compression-free estimate of said second current parameter comprises: determining a compression-free gain response based on said first current parameter and said first baseline parameter; and determining said compression-free estimate of said second current parameter based on said compression-free gain response and said second baseline parameter.

28. The method according to claim 27, wherein said compression-free gain response is a quotient of said first current parameter and said first baseline parameter.

29. The method according to claim 27, wherein said compression-free estimate of said second current parameter is a product of said compression-free gain response and said second baseline parameter.

30. The method according to claim 21 comprising selecting said set baseline gain to produce said first baseline parameter and said second baseline parameter below a nonlinear gain threshold of said circuit.

31. A system comprising: a processing circuit operable to process analog signals; and a gain control circuit operable to control a gain applied in said processing circuit; wherein said gain control circuit comprises: a first control circuit operable to set said gain to a baseline set gain or a current set gain that is different than said baseline set gain; a second control circuit operable to determine: a first feature parameter associated with a first feature of a particular pattern of an intermediate signal that is generated by said processing circuit based on an input analog signal; and a second feature parameter associated with a second feature of said particular pattern of said intermediate signal; and a third control circuit operable to determine a gain compression ratio of said intermediate signal based on one or more of: said first feature parameter at said baseline set gain, said second feature parameter at said baseline set gain, said first feature parameter at said current set gain, and said second feature parameter at said current set gain.

32. The system according to claim 31, wherein said first control circuit is operable to adjust said current set gain until said gain compression ratio reaches a predefined limit.

33. The system according to claim 31, wherein said gain control circuit comprises a fourth control circuit that is operable to: sample said intermediate signal based on a threshold voltage; and determine, for each first feature parameter and each second feature parameter, a corresponding positive voltage and a corresponding negative voltage, by adjusting said threshold voltage until a proportion of samples of said intermediate signal in a sampling period exceeding said threshold voltage reaches a target proportion based on a target count.

34. The system according to claim 33, wherein a target proportion for said first feature parameter is different than a target proportion for said second feature parameter.

35. The system according to claim 31, wherein each of said first feature parameter and said second feature parameter is a median parameter.

36. The system according to claim 31, wherein said third control circuit is operable to determine said gain compression ratio by: determining a compression-free estimate of said second feature parameter at said current set gain without gain compression; and determining said gain compression ratio based on said compression-free estimate and said second feature parameter at said current set gain.

37. The system according to claim 36, wherein said gain compression ratio is a quotient of said compression-free estimate of said second feature parameter at said current set gain without gain compression and said second feature parameter at said current set gain.

38. The system according to claim 36, wherein said third control circuit is operable to determine said compression-free estimate of said second feature parameter at said current set gain by: determining a compression-free gain response based on said first feature parameter at said current set gain and said first feature parameter at said baseline set gain; and determining said compression-free estimate of said second feature parameter at said current set gain based on said compression-free gain response and said second feature parameter at said baseline set gain.

39. The system according to claim 38, wherein said compression-free gain response is a quotient of said first feature parameter at said current set gain and said first feature parameter at said baseline set gain.

40. The system according to claim 38, wherein said compression-free estimate of said second feature parameter at said current set gain is a product of said compression-free gain response and said second feature parameter at said baseline set gain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Embodiments of the present disclosure will now be described, by way of example only, with reference to the attached Figures.

[0029] FIG. 1 is a block diagram of a known AFE circuit.

[0030] FIG. 2 is a chart illustrating gain compression.

[0031] FIG. 3 is a block diagram of an AFE circuit having an automatic compression detection and gain control (ACDGC).

[0032] FIG. 4 is a flowchart illustrating a method of operating the AFE circuit of FIG. 3.

[0033] FIG. 5 is a chart illustrating a determination of inner and outer signal eye amplitudes at a baseline set gain without gain compression.

[0034] FIG. 6 is a chart illustrating a determination of inner and outer signal eye amplitudes at a current set gain with gain compression of the outer signal eye.

[0035] FIG. 7 is a block diagram of a specific embodiment of the AFE circuit of FIG. 3.

[0036] FIG. 8 is a block diagram of a sampler block of an amplitude block of the ACDGC block of the embodiment of FIG. 7, configured to determine median positive voltages.

[0037] FIG. 9 is a block diagram of a sampler block of an amplitude block of the ACDGC block of the embodiment of FIG. 7, configured to determine median negative voltages.

[0038] FIG. 10 is a block diagram of a threshold block of an amplitude block of the ACDGC block of the embodiment of FIG. 7.

[0039] FIG. 11 is a block diagram of a compression calculation block of the ACDGC block of the embodiment of FIG. 7.

[0040] FIG. 12 is a block diagram of a gain control block of the ACDGC block of the embodiment of FIG. 7.

DETAILED DESCRIPTION

[0041] The techniques provide gain compression detection and automatic gain control for an AFE receiver to minimize nonlinear distortion of an analog signal. The techniques may be termed automatic compression detection and gain control (ACDGC).

[0042] AFE Circuit with ACDGC Block

[0043] An AFE circuit 300 including an ACDGC block 305 is shown in FIG. 3.

[0044] The AFE circuit 300 comprises one or more AFE stages 310 connected in a sequential chain. The AFE stages 310 considered collectively may be termed the AFE stages. Each AFE stage 310 in the chain modifies an analog signal as received from a preceding AFE stage 310, and outputs the modified analog signal to a next AFE stage 310 in the chain, hi other words: a first AFE stage receives an incoming analog signal 315, modifies the incoming analog signal 315, and outputs the modified analog signal; each subsequent AFE stage 310 in the chain receives an incoming modified analog signal from a preceding AFE stage 310 in the chain, further modifies the incoming modified analog signal, and outputs the further modified analog signal; and a last AFE stage 310 in the chain outputs the further modified analog signal, as modified by all of the AFE stages in the chain, as a conditioned analog signal 320. Each AFE stage 310 receives a gain control signal 325 from the ACDGC block 305, the gain control signal 325 including a set gain. Each AFE stage 310 is characterized by a gain response, such that a current gain of the AFE stage is related to the set gain by the gain response. For example, one or more of the AFE stages 310 may comprise a corresponding VGA. Each AFE stage 310 may also contain signal conditioning circuitry. The AFE stages 310 collectively are characterized by a collective gain response, which may be termed, simply, the gain response of the AFE stages when referenced collectively.

[0045] The conditioned analog signal 320 output by the last AFE stage 310 is received by an analog-to-digital converter (ADC) block 330 which generates an outgoing digital signal 335. A clock recovery block 340 may receive the digital signal 335 to recover a clock 345 encoded in the incoming analog signal 315, and to control a phase control block 350 which generates a phase signal 355 to control a phase of the analog-to-digital conversion by the ADC block 330, according to methods known in the art.

[0046] When amplifying an incoming signal 315 with one or more AFE stages 310, the set gain 325 of the AFE stages 310 may be adjusted until an average amplitude of the conditioned analog signal 320 equals a target amplitude. The target amplitude may be chosen at design time. If the amplitude of any analog signal received by an AFE stage exceeds a linear range of the gain response of the AFE stage, nonlinear amplification may result in the conditioned analog signal 320 received by the ADC 330 being compressed which causes signal distortion. The compression typically occurs at the largest (negative and positive) voltages of the signal, namely, the outer eye portion of the signal. Due to chip process, power supply voltage, and temperature (PVT) differences, the compression may be significant.

[0047] Thus, alternatively, the ACDGC block 305 may control a set gain 325 sent to the AFE stages 310, and measure amplitudes of each of the inner and outer portions of a signal eye of the conditioned analog signal 320 at different set gains 310. The ACDGC block 305 may calculate a gain compression ratio by comparing a change in the inner eye amplitude (which does not experience compression) at different set gains 325 with a change in the outer eye amplitude (which may experience compression at a higher gain) at the different set gains 325. The ACDGC block 305 may control the gain control signal 325 based on the calculated compression ratio, for example so as to maintain the compression ratio at or below a threshold value.

[0048] ACDGC Operation

[0049] A method 400 of controlling a gain of an AFE circuit 300 using the ACDGC block 305 is now described with reference to FIGS. 4-6.

[0050] The ACDGC block 305 outputs a gain control signal 325 to set a baseline set gain g.sub.1 to the AFE g.sub.1g.sub.1stages 310 (step 405). The ACDGC block 305 then receives from the last AFE stage 310 the conditioned analog signal 320 and determines an amplitude of the inner eye, which may be a median inner eye amplitude A.sub.i(g.sub.1), and similarly an outer eye amplitude, which may be a median outer eye amplitude A.sub.o(g.sub.1) of the conditioned analog signal 320 at the baseline set gain g.sub.1 (step 410). FIG. 5 shows an example conditioned analog signal 500 at a baseline set gain g.sub.1. As shown, the baseline set gain g.sub.1 may be selected such that the median inner eye amplitude A.sub.i(g.sub.1) 505 falls within a non-compressed, linear region 510 of the gain response 515 of the AFE stages 310. Similarly, the baseline set gain g.sub.1 may also be set such that the median outer eye amplitude A.sub.o(g.sub.1) 520 falls within the non-compressed, linear region 510 of the gain response 515 of the AFE stages 310.

[0051] The ACDGC block 305 may then increase the set gain 325 to a current set gain (step 415). The increase may be a predefined increment in the set gain 325. Optionally, if the current set gain g.sub.m is determined to be equal to or less than a minimum set gain, or is equal to or greater than a maximum set gainor, in other words, if the current set gain g.sub.m is determined not the be within predefined minimum and maximum values (decision 420)then the method ends. Otherwise, the ACDGC block 305 determines a median inner eye amplitude A.sub.i(g.sub.m) and a median outer eye amplitude A.sub.o(g.sub.m) at the current set gain g.sub.m (step 425). FIG. 6 shows an example conditioned analog signal 600 at a current set gain g.sub.m. As shown the current set gain g.sub.m may be selected such that the median inner eye amplitude A.sub.i(g.sub.m) 605 continues to fall within the non-compressed, linear region 510 of the gain response 515 of the AFE stages 310. At some threshold value of the current set gain g.sub.m, however, the median outer eye amplitude A.sub.o(g.sub.m) 610 will fall outside of the non-compressed, linear region 510, or in other words within a compressed, nonlinear region 615 of the gain response 515 of the AFE stages 310.

[0052] The ACDGC block 305 may then determine a compression ratio at the current set gain g.sub.m (step 430) based on the median inner eye amplitude A.sub.i(g.sub.m) and median outer eye amplitude A.sub.o(g.sub.m) at the current set gain g.sub.m, and the median inner eye amplitude A.sub.i(g.sub.1) and the median outer eye amplitude A.sub.o(g.sub.1) at the baseline set gain g.sub.1. One method of determining the compression ratio is to estimate the theoretical gain response of the AFE stages in the absence of compression based on the change of the median inner eye amplitude between the baseline set gain g.sub.1 and the current set gain g.sub.m, by calculating:

[00001]$\begin{array}{cc}{k}_i=\frac{A_i\left(g_m\right)}{A_i\left(g_1\right)}& \left(1\right)\end{array}$

[0053] As shown in FIG. 6, an estimate of the outer eye amplitude at the current set gain g.sub.m without compression .sub.o(g.sub.m) 620 may then be calculated by:

.sub.o(g.sub.m)=k.sub.iA.sub.o(g.sub.1) (2)

[0054] The compression ratio c(g.sub.m) at the current set gain g.sub.m may then be calculated as the ratio between the estimate of the outer eye amplitude .sub.o(g.sub.m) and the median outer eye amplitude A.sub.o(g.sub.m) at the current set gain g.sub.m:

[00002]$\begin{array}{cc}c\left(g_m\right)=\frac{{\hat{A}}_o\left(g_m\right)}{A_o\left(g_m\right)}=\frac{k_i.Math.A_o\left(g_1\right)}{A_o\left(g_m\right)}=\frac{A_i\left(g_m\right)}{A_i\left(g_1\right)}/\frac{A_o\left(g_m\right)}{A_o\left(g_1\right)}& \left(3\right)\end{array}$

[0055] The ACDGC block 305 then determines whether the compression ratio c(g.sub.m) at the current set gain g.sub.m has reached a predefined limit c.sub.max (decision 435), in which case the method ends. Otherwise, if the compression ratio c(g.sub.m) has not yet reached the predefined limit, that is c(g.sub.m)c.sub.max, then the ACDGC block 305 increases the current set gain g.sub.m, which increase may be by a predefined increment in the set gain, method steps 415 to 435 repeat.

[0056] In this way, the ACDGC block 305, beginning at a baseline set gain g.sub.1 with no gain compression, incrementally increases the current set gain until a predefined compression ratio limit c.sub.max is reached. The predefined compression ratio limit c.sub.max may be a design parameter, and may be selected based on a predetermined tolerable level of gain compression, which may be determined with reference to any suitable standard such as an error rate of ADC block 330 or otherwise.

Specific Embodiment

[0057] The ACDGC block 305 may be implemented in any suitable embodiment to perform the functionality described herein. With reference to FIG. 7, AFE circuit 301 is a specific instance of AFE circuit 300, and has an ACDGC block 306 which is a specific instance of the ACDGC block 305 is now described with reference to FIGS. 7-12 by way of example only and without limitation to other possible embodiments and implementations.

[0058] FIG. 7 shows the AFE circuit 301 with an ACDGC block 306 including a finite state machine (FSM) block 705, one or more amplitude blocks 710, a gain control block 715, and a compression calculation block 720. The FSM block 705 controls the gain control block 715 and the amplitude block(s) 710 to measure the amplitudes of each of the inner and outer portions of the signal eye of the conditioned analog signal 320 at the different set gains. The compression calculation block 720 receives the measured amplitudes 725 from the amplitude block(s) 710 and calculates the gain compression ratio as described above. The FSM block 705 controls the gain control block 715 based on the calculated compression ratio to control the set gain included in the gain control signal 325 output to the AFE stages 310. The set gain may be limited so as to maintain the compression ratio at or below a threshold value.

[0059] Amplitude Block

[0060] The ACDGC block 306 may include one or more amplitude blocks 710 to measure median positive and negative voltages of the amplitude of the inner and outer eyes of the conditioned analog signal 320 at a given set gain.

[0061] In other words, and with reference to FIGS. 5 & 6, the amplitude block(s) measure: V.sub.i.sup.P and V.sub.i.sup.N, the median positive and negative voltages, respectively, of the amplitude of the inner signal eye of the conditioned analog signal 320; and, V.sub.o.sup.P and V.sub.o.sup.N, the median positive and negative voltages, respectively, of the amplitude of the outer signal eye of the conditioned analog signal 320.

[0062] In one alternative, the ACDGC block 306 may have a single amplitude block 710 controlled by the FSM bock 705 to determine alternatively, one at a time and in any desired order, the median positive and negative voltages of the respective amplitudes of the inner and outer signal eyes of the conditioned analog signal 320, or in other words to determine each one of V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N at a time in turn and in any desired order. The single amplitude block 710 may output sequentially to the compression calculation block 720 the voltages thus alternatively determined.

[0063] Alternatively, the ACDGC block 306 may have a plurality of amplitude blocks 710, each amplitude block 710 determining a different one of voltages V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N and at a given time. For example, the ACDGC block 306 may have four amplitude blocks, 710 each one determining a corresponding different one of V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N. In this way, the four voltages characterizing the median amplitudes of the inner and outer signal eyes of the conditioned analog signal 320 may be determined simultaneously and output to the compression calculation block 720, which may be configured to receive all of the voltages at once.

[0064] Each amplitude block 710 may include a sampler block 730 and a threshold control block 735 which cooperate to determine and output to the compression calculation block 720 one of voltages V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N given a target count and a calculated period received from the FSM block 705.

[0065] Each sampler block 730 may be a single bit sampler (or slicer) with a programmable threshold voltage controlled by the threshold control block 735 to measure a preconfigured median voltage.

[0066] For example, to detect the inner and outer portions of the signal eye, a threshold voltage 725 received by the sampler block 730 may be positive or negative, and may be varied by the threshold control block 735 until a certain proportion of the samples, as specified by the FSM block 705, are above (for positive voltages) or below (for negative voltages) the threshold voltage in a given time window. Different target proportions may be set corresponding to the inner and outer portions of the signal eye. In each case, when a current threshold voltage generates the target proportion of samples, the threshold voltage indicates the median positive voltage (for positive voltages) or median negative voltage (for negative voltages) of the amplitude of the inner or outer portion of the signal eye, as the case may be.

[0067] For example, for the inner eye of the conditioned analog signal, the threshold voltages may be determined so as to find median positive and negative voltages V.sub.i.sup.P and V.sub.i.sup.N such that the proportion p of voltages V at baseline set gain g.sub.1 is given by:

p(V>V.sub.i.sup.P|g=g.sub.1)=p.sub.i

p(V<V.sub.i.sup.N|g=g.sub.1)=p.sub.i

[0068] Similarly, for the outer eye of the conditioned analog signal, the threshold voltages may be determined so as to find median positive and negative voltages V.sub.o.sup.P and V.sub.o.sup.N such that the proportion p of voltages V at baseline set gain g.sub.1 is given by:

p(V>V.sub.o.sup.P|g=g.sub.1)=p.sub.o

p(V<V.sub.o.sup.N|g=g.sub.1)=p.sub.o

[0069] And further similarly, the corresponding median voltages at the current set gain g.sub.m may be given by:

p(V>V.sub.i.sup.P|g=g.sub.m)=p.sub.i

p(V<V.sub.i.sup.N|g=g.sub.m)=p.sub.i

p(V>V.sub.o.sup.P|g=g.sub.m)=p.sub.o

p(V<V.sub.o.sup.N|g=g.sub.m)=p.sub.o

[0070] For the detection of inner eye amplitude, the target proportion p.sub.i of samples above the positive threshold voltage V.sub.i.sup.P, or below the negative threshold voltage V.sub.i.sup.N, may be chosen in the range of 35% to 45% in order to have an inner portion of signal eye without compression. For the detection of outer eye amplitude, the target proportion p.sub.o of samples above the positive threshold voltage V.sub.o.sup.P, or below the negative threshold voltage V.sub.o.sup.N, may be chosen in the range of 3% to 10% in order to have good sensitivity to gain compression without requiring a long period of detection window. The foregoing ranges are presented by way of non-limiting example only, and other ranges are possible.

[0071] FIGS. 8-10 show embodiments of sampler blocks 730 and a threshold control block 735 by way of example only and without limitation to other possible embodiments and implementations.

[0072] Sampler Block

[0073] FIGS. 8 & 9 shown sampler blocks 731, 732 are instances of sampler block 730, and which are identical except in that the sampler block 731 shown in FIG. 8 is configured to sample positive voltages and the sampler block 732 shown in FIG. 9 is configured to sample negative voltages. In each case, the sampler block 730 compares the conditioned analog signal to a threshold voltage received from the threshold control block.

[0074] The sampler block 730 includes a digital-to-analog converter (DAC) 805, a comparator block 810, and a D flip-flop (IFF) 815. The threshold control block 735 sends a digitally encoded threshold voltage 725 to the sampler block 730. This multi-bit threshold voltage 725 is converted to an analog reference voltage (VREF) 820 by the DAC 805, which is received by the comparator block 810. The comparator block 810 compares the input conditioned analog signal 320 to the analog reference voltage VREF 820. The threshold voltage 725 may encode both positive and negative values, and for example may be a 4-bit, two complement number, although other configurations are possible,

[0075] If the sampler block 730 is the sampler block 731 which is sampling for a positive threshold voltage, such as a median positive voltage of the amplitude of the inner or outer signal eye, and the conditioned analog signal voltage is greater than the analog reference voltage VREF, then the output 823 of the comparator block 810 will be the maximum supply voltage Vpos 825, and otherwise it will be the negative supply voltage Vneg 830. Alternatively, if the sampler block 730 is the sampler block 732 which is sampling for a negative threshold voltage, such as a median negative voltage of the amplitude of the inner or outer signal eye, then either the inputs or supply voltages of the comparator block 810 in FIG. 8 may be reversed, for example as shown in FIG. 9; in this case, if the conditioned analog signal 320 voltage is less than the analog reference voltage VREF 820, then the output 823 of the comparator block will be the positive supply voltage Vpos 825, and otherwise it will be the negative supply voltage Vneg 823. A range of the analog reference voltage VREF 820 may be configured to span the positive supply voltage Vpos 825 and the negative supply voltage Vneg 823.

[0076] In either case, the output 823 of the comparator block is sampled by the DFF 815. The DFF 815 will output a sample bit 835 of 1 if the output 823 received from the comparator block 810 is above the midpoint of the supply voltages 825, 830, and will output a sample bit 835 of 0 if the comparator block 810 output 823 is below the midpoint of the supply voltages 825, 830. The output of the DFF 815 only changes when the sample clock 840 input changes from a Vneg to Vpos voltage.

[0077] The sampling is repeated over many sampling docks in order to provide statistics on the voltage of the conditioned analog signal. The timing of the sampling is done such that the measurement of the signal occurs in the middle of the signal eye. The sampling rate can be less than or equal to the bit rate of the received signal.

[0078] Threshold Control Block

[0079] The threshold control block 735 generates a digitally encoded threshold voltage 725 given an input calculation period 1005 and target count 1010 received from the FSM block 705. An embodiment of a threshold control block 735 is shown in FIG. 10.

[0080] A sample bit 835 from the sampler block 730 is received by a sample counter 1015. A sample counter value 1020 is initially set to zero and increments by one at every rising edge of the sample clock 840 when the sample bit 835 is a 1, or remains at a current value if the sample bit 835 is a 0. The sample counter value 1020 is cleared to zero by a dear signal 1025 from a period compare block 1030.

[0081] The sample counter value 1020 is received by a count compare block 1035 which compares a target count 1010 received from the FSM block 705 to the sample counter value 1020. The output 1040 of the count compare block 1035 is a 1 when the sample counter value 1020 is greater than the target count 1010 and 0 otherwise.

[0082] A period counter value 1045 of a period counter block 1050 starts at zero and increments by one at every rising edge of the sample dock 840. The period counter value 1045 is received by the period compare block 1030. The period counter value 1045 is cleared to zero by a dear signal 1025 from the period compare block 1030.

[0083] The period compare block 1030 compares a calculation period 1005 received from the FSM block 705 to the period counter value 1045 received from the period counter block 1050. The period compare block 1030 generates at its output a period compare value 1025 of 0 when the period counter value 1045 is less than the calculation period 1005 and a 1 when the period counter value 1045 is greater than or equal to the calculation period 1005.

[0084] A threshold voltage 725 generated by an incrementer/decrementer block 1055 is initially set to one-haft of a maximum value of a maximum threshold voltage. The threshold voltage 725 is updated on a rising edge of the period compare value 1025 output from the period compare block 1030, which occurs once every calculation period dock cycles. During the update the threshold voltage 725 is increased or decreased by a current delta value 1060 if a count compare value 1040 input from the count compare block 1035 is 1 or decremented by the current delta value 1060 if the count compare value 1040 is 0. Specifically, the threshold voltage 725 is increased by the current delta value 1060 if a positive voltage threshold is being determined, e,g. a median positive voltage of the inner or outer eye amplitude; alternatively, the threshold voltage 725 is decreased by the current delta value 1060 (or the delta value 1060 is negative) if a negative voltage threshold is being determined, e.g. a median negative voltage of the inner or outer eye amplitude. A delta block 1065 determines delta value 1060, that is, by how much the output threshold voltage 725 will be changed when the calculation period is reached. The delta value 1060 is initially set to one-haft of the maximum range of the threshold. The delta value 1060 is reduced by one-half of its previous value when the calculation period is reached. The done signal 1070 is set to 1 when the delta value 1060 has been reduced to the value 1.

[0085] As noted above, the threshold incrementer/decrementer block 1055 controls the threshold voltage 725. The threshold voltage 725 is initially set to one-half of an absolute maximum value. Every time the calculation period 1005 is reached the threshold voltage 725 is incremented by the input delta value 1060 if the count compare value 1040 is a 1, or decremented by the input delta value 1060 if the count compare value 1040 is a 0.

[0086] As noted above, a single amplitude block 710 may be used alternatively to determine the respective median positive and negative voltages of the inner and outer signal eyes sequentially, and thus configured alternatively depending on whether a positive or a negative threshold voltage is being determined. Alternatively, a number, such as four, amplitude blocks 710 may be used simultaneously to determine all four median voltages simultaneously, and in this case the four corresponding threshold control blocks 735 receive from the FSM block 705 corresponding target counts, and each controls its incrementer/decrementer block 1055 as described above depending on whether the threshold control block 735 determines a positive or negative threshold voltage. Each threshold control block 735 may receive the outgoing digital signal 335 from the ADC 330, as shown in FIG. 7, and in particular the data sign bit of the digital signal 335 which indicates whether a positive or negative threshold voltage is being determined. The sign bit may be received by and enable or disable each of the sample counter 1015 and period counter 1050.

[0087] Compression Calculation Block

[0088] The compression calculation block 720 computes the compression ratio of the conditioned analog signal 320 at a current set gain g.sub.m. An embodiment of a compression calculation block 720 is shown in FIG. 11.

[0089] The compression calculation block 720 receives the threshold voltages 725 from the threshold control block 735, and saves them into registers on a rising edge of a done signal 1070 received from the threshold control block 735. An initialization signal 1105 switches the threshold voltage 725 input from a baseline values register 1110 (or registers) to a current values register 1115 (or registers). Thus, when the median amplitude voltages V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N are determined at the baseline set gain they are stored in the baseline values register 1110. Subsequently, when the median amplitude voltages V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N are determined at a current set gain g, they are stored in the current values register 1115.

[0090] As indicated above, if the ACDGC block 306 has a single amplitude block 710 which determines the median amplitude voltages sequentially, the compression calculation block 720 may receive and store them sequentially, and in this case the compression calculation block 720 may further include one or more buffers to hold the median amplitude voltages until all of them are determined and received. Alternatively, if the ACDGC block 306 has multiple amplitude blocks 710 which determine different median amplitude voltages simultaneously, the compression calculation block 720 receives and stores them simultaneously.

[0091] The compression calculation block 720 has a compression ratio calculation block 1120 to calculate the compression ratio c(g.sub.m) at the current set gain g.sub.m as described above, based on the median inner eye amplitude A.sub.i(g.sub.1) and median outer eye amplitude A.sub.o(g.sub.1) at the baseline set gain g.sub.1, and median inner eye amplitude A.sub.i(g.sub.m) and a median outer eye amplitude A.sub.o(g.sub.m) at the current set gain g.sub.m.

[0092] Specifically, the compression ratio calculation block 1120 calculates the median inner eye amplitudes A.sub.i and outer eye amplitudes A.sub.o at the baseline set gain g.sub.1 and the current set gain g.sub.m based on the positive median amplitude voltage V.sub.i.sup.P and the negative median amplitude voltage V.sub.i.sup.N at the baseline set gain g.sub.1 and the current set gain g.sub.m, as follows:

A.sub.i(g.sub.1)=V.sub.i.sup.P(g.sub.1)V.sub.i.sup.N(g.sub.1)

A.sub.o(g.sub.1)=V.sub.o.sup.P(g.sub.1)V.sub.o.sup.N(g.sub.1)

A.sub.i(g.sub.m)=V.sub.i.sup.P(g.sub.m)V.sub.i.sup.N(g.sub.m)

A.sub.o(g.sub.m)=V.sub.o.sup.P(g.sub.m)V.sub.o.sup.N(g.sub.m)

[0093] The compression ratio calculation bock 1120 then calculates the compression ratio c(g.sub.m) at current set gain g.sub.m based on A.sub.i(g.sub.1), A.sub.o(g.sub.1), A.sub.i(g.sub.m), and A.sub.o(g.sub.m), as set forth in equations (x) to (y), above. An output of the compression ratio calculation block 1120 is the compression ratio c(g.sub.m) 1125. The compression ratio c(g.sub.m) 1125 may be valid only after the baseline values register 1110 and current values register 1115 have at least once received all of the above median amplitude voltages. The compression ratio c(g.sub.m) 1125 is sent to the FSM block 705.

[0094] Gain Control Block

[0095] The gain control block 715 is used to control the set gains of the AFE stages 310 under the control of the FSM block 705. An embodiment of a gain control block 715 is shown in FIG. 12.

[0096] An incrementer/decrementer block 1205 receives from the FSM block 705 a start signal 1210. When the start signal 1210 is received the set gain 325 is set to the baseline set gain value 1215 received from the FSM block 705.

[0097] An update signal 1220 is received from the FSM block 705. At each rising edge of the update signal 1220 the incrementer/decrementer block 1205 increases the current set gain 325 by a preconfigured value if an increase gain signal 1225 from the FSM block 705 is a 1, or decreases the set gain 325 by the preconfigured value otherwise.

[0098] A maximum compare bock 1230 outputs a 1 if the set gain 325 from the incrementer/decrementer block 1205 is equal to or greater than a preconfigured maximum gain for the system and outputs a 0 otherwise. A minimum compare block 1235 outputs a 1 if the set gain 325 is equal to or less than a preconfigured minimum gain specified for the system and outputs a 0 otherwise. An OR gate 1240 receives the outputs of the maximum compare block 1230 and minimum compare block 1235 and outputs 1245 a logic OR of these inputsthat is, the OR gate outputs a 1 if the gain is equal to greater than the maximum gain, or is equal to or less than the minimum gain, and outputs a 0 otherwise. This done signal is output to a controlling or cooperating system as an indication that the ACDGC block 305 has finished setting the optimum gain.

[0099] Finite State Machine (FSM) Block

[0100] The finite state machine (FSM) 705 block controls the threshold control block 735 of each amplitude block 710, and the gain control block 715, and interprets the current compression ratio c(g.sub.m) at current set gain g.sub.m received from the compression calculation block 720. The FSM block 705 selects a baseline set gain g.sub.1 wherein no compression occurs in the conditioned analog signal 320.

[0101] The FSM block's 705 operation depends upon whether the ACDGC block 306 has only one amplitude block 710, or instead has multiple amplitude blocks 710.

[0102] In either case, the FSM block 705 starts by signaling the gain control block 715 to set its output values to nominal starting values. As such, the gain control block 715 is controlled to set the set gain 325 of the AFE stages 310 to baseline set gain g.sub.1. In addition, the FSM block 705 signals the threshold control block 735 in the case of a single amplitude block 710, or threshold control blocks 735 in the case of multiple amplitude blocks 710, to nominal starting values. As such, the FSM block 705 gives each threshold control block 735 a corresponding target count and calculation period.

[0103] in the case of multiple amplitude blocks 710, for example four amplitude blocks 710 each configured to determine a different one of voltages V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N, once each amplitude block 710 determines and outputs to the compression calculation block 720 its corresponding threshold voltage 725, the FSM block 705 then signals the gain control block 715 to increase the set gain 325 to a new current set gain g.sub.m, and signals the threshold control blocks 735 of the amplitude blocks 710 to compute new threshold voltages.

[0104] In the case of a single amplitude block 710, after a first threshold voltage Vthat is, one of voltages V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.Nis reached by the threshold control block 735, the compression calculation block 720 receives and stores the threshold voltage, and the FSM block 705 then signals the threshold control block 735 to determine another one of the threshold voltages, until all of the threshold voltages are determined. The FSM block 705 then signals the gain control block 715 to increase the set gain 325 to a new current set gain a, and as above signals the threshold control block 735 in sequence to determine the voltage thresholds.

[0105] After all of the voltage thresholds V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N are determined at both the baseline set gain g.sub.1 and the current set gain g.sub.m, the compression calculation block 720 computes the compression ratio and sends it to the FSM block 705. If the compression ratio c(g.sub.m) at the current set gain g.sub.m is below the predefined limit c(g.sub.m)c.sub.max, the FSM block 705 signals to the gain control block 715 to increase the current set gain g.sub.m 325. The FSM block 705 then again signals the one or more amplitude blocks 710 to determine the median amplitudes V.sub.i.sup.P, V.sub.i.sup.N, V.sub.o.sup.P, and V.sub.o.sup.N at the new current set gain g.sub.m, for output to the compression calculation block 720, and the process repeats until the compression ratio c(g.sub.m) reaches the predefined limit c.sub.max.

[0106] Advantages

[0107] By having accurate detection of the gain compression there is no need to be conservative to choose a low gain in order to keep compression within the linear gain response region. Automatic compression detection in combination with gain control supports incoming signals with larger dynamic range without sacrificing system performance due to non-optimum gain selection.

[0108] By having knowledge of the gain compression, the amplifier design constraints can be relaxed which improves power consumption and simplifies the amplifier design.

[0109] In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that these specific details are not required. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the understanding. For example, specific details are not provided as to whether the embodiments described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof.

[0110] Embodiments of the disclosure can be represented as a computer program product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible, non-transitory medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the disclosure. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described implementations can also be stored on the machine-readable medium. The instructions stored on the machine-readable medium can be executed by a processor or other suitable processing device, and can interface with circuitry to perform the described tasks.

[0111] The above-described embodiments are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art. The scope of the claims should not be limited by the particular embodiments set forth herein, but should be construed in a manner consistent with the specification as a whole.