Parasitic capacitance cancellation in capacitive measurement

Abstract

An integrated circuit compensates for parasitic capacitance in a capacitive measuring apparatus wherein a capacitance measurement is done by repeatedly transferring charge from a capacitor to be measured to a reference capacitor.

Claims

1. An integrated circuit for measuring an inductance of a structure, wherein said integrated circuit comprises: charge transfer circuitry for transferring charge during each of a plurality of measurement cycles from said structure to a reference capacitor, and wherein the charge accumulated in the reference capacitor is reduced during every cycle in the inductance measurement by a predetermined amount of charge, and wherein the charge being transferred for measurement is scaled using at least one current mirror structure.

2. The integrated circuit of claim 1, wherein said integrated circuit further comprises at least one current mirror structure for scaling the amount of charge reduction during every cycle.

3. The integrated circuit of claim 1, wherein the reference capacitor is located on-chip in the integrated circuit.

4. The integrated circuit of claim 1 further including a number of selectable on-chip capacitors and wherein the selection of said on-chip capacitors determines the amount of charge reduction during every cycle.

5. The integrated circuit of claim 1, wherein the current mirror structure or structures includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the inductance measurement for sensitivity.

6. The integrated circuit of claim 1, wherein the current mirror structure or structures includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the inductance measurement for speed.

7. The integrated circuit of claim 1, wherein the current mirror structure or structures includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the inductance measurement for stability.

8. The integrated circuit of claim 2, wherein the current mirror structure or structures includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the inductance measurement for sensitivity.

9. The integrated circuit of claim 2, wherein the current mirror structure or structures includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the inductance measurement for speed.

10. The integrated circuit of claim 2, wherein the current mirror structure or structures includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the inductance measurement for stability.

11. The integrated circuit of claim 2, wherein the reduction of charge is independent of the voltage across said reference capacitor.

12. The integrated circuit of claim 1, wherein a reference current which flows for a defined period of time is used to reduce said charge by said predetermined amount.

13. A method to measure an inductance of a structure, wherein said method comprises the steps of transferring charge during each of a plurality of cycles of the measurement from said structure to a reference capacitor, of reducing the amount of charge accumulated in said reference capacitor by a predetermined amount and of scaling the charge being transferred by using at least one current mirror structure.

14. The method of claim 13, further including a step wherein at least one current mirror structure is used to scale the amount of charge reduction during every cycle of said measurement.

15. The method of claim 14, further including a step wherein scaling ratios for said current mirror or mirrors are selected according to an algorithm which optimizes said inductance measurement for sensitivity.

16. The method of claim 14, further including a step wherein scaling ratios for said current mirror or mirrors are selected according to an algorithm which optimizes said inductance measurement for speed.

17. The method of claim 14, further including a step wherein scaling ratios for said current mirror or mirrors are selected according to an algorithm which optimizes said inductance measurement for stability.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is further described by way of examples with reference to the accompanying drawings in which:

(2) FIG. 1 shows a charge transfer circuit with a parasitic capacitance cancellation circuit;

(3) FIG. 2 shows charge (UP) and transfer (PASS) signals;

(4) FIG. 3 depicts a charge transfer circuit and capacitance cancellation circuit during a charge phase;

(5) FIG. 4 depicts the charge transfer and parasitic capacitance cancellation circuit during a transfer phase;

(6) FIG. 5 is a graphical representation of the definition of a mirror structure;

(7) FIG. 6 shows a two stage current mirror structure to transfer charge from C.sub.M to C.sub.R;

(8) FIG. 7 shows a charge transfer circuit which uses a mirror method of parasitic capacitance cancellation;

(9) FIGS. 8A and 8B respectively show two forms of a cascade mirror structure with a current based capacitance cancellation circuit;

(10) FIG. 9 shows a diagram of an integrated circuit using current mirror ratio technology and capacitive cancellation;

(11) FIGS. 10A and 10B are respective flow charts of possible algorithms to implement an automatic adjustment of parameters (CR value or current mirror ratios of amount of capacitive cancellation) for performance based on two specific metrics;

(12) FIG. 11 shows a diagram for a circuit to detect the presence of RTS noise;

(13) FIG. 12 shows an implementation for a capacitive cancellation circuit with the cancellation happening before the current mirror structure; and

(14) FIG. 13 shows a charge scaling capacitor on an input side to reduce the size of ratio required in a current mirror structure when large input capacitors are measured.

DESCRIPTION OF PREFERRED EMBODIMENTS

(15) FIG. 1 shows a charge transfer circuit as well as a parasitic capacitance cancellation circuit.

(16) Before a measurement period a reference capacitor (C.sub.R) is initialized to a known voltage Va (e.g. 0V) by closing a switch S1.

(17) The Charge Transfer Cycle consists of at least 4 phases, viz the Charge Phase (UP), the Transfer Phase (PASS) and two Deadtime Phases (FIG. 2) which ensure that the Charge Phase and the Transfer Phase do not overlap. During the Charge Phase switches S3, S5 and S7 are closed and switches S2, S4 and S6 are open. A measured capacitor (C.sub.M) as well as the parasitic capacitance (C.sub.P) are charged to a reference voltage (Vdd).

(18) During the Transfer Phase the switches S.sub.2, S.sub.4 and S.sub.6 are closed and the switches S.sub.3, S.sub.5 and S.sub.7 are open. Capacitors C.sub.M and C.sub.P are connected to the reference capacitor (C.sub.R) and charge is transferred from C.sub.M and C.sub.P to C.sub.R. The voltage on C.sub.R at the end of the Transfer Phase is V.sub.CR.

(19) Thus, during each Charge Transfer Cycle, the parasitic capacitance (C.sub.P) adds C.sub.p (VddV.sub.CR) charge to C.sub.R. This is the amount of charge that the parasitic capacitance cancellation circuit must remove during each Charge Transfer Cycle.

(20) During the Transfer Phase (FIG. 4), a compensation capacitor C.sub.C is pre-charged to (VddV.sub.CR) and thus C.sub.C has a charge of C.sub.c (VddV.sub.CR). This charge is supplied by the buffer and the supply voltage (Vdd). No charge is added to or removed from C.sub.R.

(21) During the Charge Phase (FIG. 3) the charge on C.sub.C is decreased to 0. The charge needed to change the charge on C.sub.C from C.sub.c (VddV.sub.CR) to 0, is removed from C.sub.R. The VCc+ terminal of the C.sub.C capacitor is connected to a buffer output and the VCc terminal is connected to C.sub.R. This connection configuration causes charge to be removed from C.sub.R as the C.sub.C capacitor discharges from (VddV.sub.CR) volt to 0 volt.

(22) Thus if C.sub.p=C.sub.c, the additional charge that the parasitic capacitance (C.sub.P) adds to C.sub.R during each Charge Transfer Cycle, is removed by the compensation capacitor (C.sub.C) in the next Charge Transfer Cycle and the net gain of charge on C.sub.R is only because of C.sub.M. The effect of the parasitic capacitance C.sub.P is thus cancelled.

(23) FIG. 5 shows graphically the mirror structure required. The circuit is connected so that a reference current (I.sub.R) flows between nodes 1 and 3. The current mirror ratio structure (k defines the ratio between I.sub.S and I.sub.R) then results in a derived current (I.sub.S=kI.sub.R) flowing between nodes 2 and 4. k is a factor determined by the designer. If k=1 then the currents are the same; if k<1 then I.sub.S is smaller than I.sub.R, and if k>1, I.sub.S is larger than I.sub.R.

(24) In FIG. 6 the mirror element is shown in a general circuit for charge transfer measurement. C.sub.M (the capacitor the value of which must be measured) is charged through S.sub.1 (Charge Phase) and then discharged to ground through S.sub.2 (Transfer Phase). The resulting current (I.sub.R) flows through the current mirror element between nodes 1 and 3. This results, in accordance with the method of operation of the mirror element, in a current kI.sub.R flowing between nodes 2 and 4. This same current is connected to a second mirror ratio structure and this results in a current n(kI.sub.R) flowing between nodes 6 and 8. In this example the initial reference current I.sub.R is multiplied first by a factor k and then by a factor n. In a specific situation k and n are each smaller than 1. This current forces charge into C.sub.R, charging it with a charge that is related through the factor nk with the charge flowing from C.sub.M to ground. This technique results in a linear charging of C.sub.R i.e. the voltage level on C.sub.R rises in equal steps for each Charge Transfer Cycle and does not fall away as results from charging C.sub.M directly into C.sub.R. After each Charge Transfer Cycle the voltage level on C.sub.R can be checked to see if a trip level has been reached.

(25) The values of n and k can be chosen to meet certain objectives, for example to limit the value of C.sub.R due to size or cost considerations e.g. if k=0.1 and n=0.01 then the charge transfer is reduced by a factor of 1000.

(26) The current mirror can be a single current mirror or use can be made of two or more current mirrors. This does not affect the implementation of the invention. The two stage implementation is merely an example that works well in practice.

(27) FIG. 7 shows the parasitic capacitance cancellation structure. The value of parasitic capacitance to be cancelled can be selectively varied through the various switches available. If the three capacitors shown are used more charge will be removed from C.sub.R every cycle.

(28) Through switches S6, S7 and S8 the capacitors are charged. The capacitors are discharged through the switches S.sub.3, S.sub.4 and S.sub.5 to ground, creating a reference current. The mirrored and scaled currents then flow through the secondary nodes of the current mirror structure resulting in charge being removed from C.sub.R.

(29) During very low voltage levels on C.sub.R, the structure does not operate well and the charge removed will not reflect the desired parasitic capacitance to be removed. However, in this application it is believed that the negative effect is negligible and is far outweighed by the positives.

(30) The switching selection of the capacitors can be done under software control to automatically calibrate products for optimum operation. For example, a product can be designed and the PCC (parasitic capacitance cancellation) can be used to tune automatically for, say, 4000 transfers, when no touch is present. In this way manufacturing variations can be compensated for.

(31) This means a sensor can be tuned to have a certain capacitance and hence a standard level of performance can be achieved over production. It is thus possible to use various current mirror ratios, different size reference capacitors, various capacitance cancellation values and an algorithm to adjust these to obtain specific transfer counts for a fixed trip level with various objectives such as sensitivity (proximity distance), stability, noise immunity, reaction time and number of charge transfer cycles, to reach a specific voltage level (trip level) and sample frequency. These features can be achieved on a single integrated circuit coupled with a sense plate without the need for external capacitors.

(32) The adjustment of a trip level can also be used in an equivalent way to adjusting the C.sub.R value. Moving the trip level higher is equivalent to enlarging the C.sub.R and vice versa.

(33) FIGS. 8A and 8B show how the charge to be removed during capacitance cancellation can be determined by choosing between various reference current sources (FIG. 8B) rather than capacitors (FIG. 8A). A capacitor charged to a specific voltage contains a defined charge. This charge, divided or multiplied via current mirror ratios, is used to define the charge that is removed in the capacitance cancellation technique. The same effect (FIG. 8B) can be achieved using current as a reference for the charge, instead of capacitance. A defined current flowing for a specific period of time also defines a charge. The charge can be taken out of C.sub.R using a current during the complete cycle or during a portion of each cycle. All that is required is that the period (i.e. main oscillator) and amplitude of current remain stable. As mentioned before this may be attractive in terms of implementation on silicon. The charge may also be determined by another technique applicable to the specific situation without affecting the other teachings and advantages of this invention.

(34) Currents are in general more stable and noise immune than voltages. On silicon (CMOS) it is also possible to generate a range of current references, using mirror structures and other techniques, that are well matched and less affected by layout parasitic effect than, for example, capacitors. The use of currents to remove charge from the C.sub.R can also have advantages for the capacitive cancellation implementation in the sense that switching every Charge Transfer Cycle is not needed for the cancellation circuit. The cancellation current can flow continuously and as long as the charge transfer frequency is stable a fixed ratio between charge added from the C.sub.M to C.sub.R and the charge removed from C.sub.R will be maintained. If C.sub.M changes, the ratio will also change to reflect the changed capacitance measured.

(35) FIG. 9 shows a circuit diagram based on an integrated circuit from Azoteq (Pty) Ltd based on a charge transfer measurement method using current mirror ratios and capacitive cancellation techniques. It is apparent that only a few external components are required and that all C.sub.R's have been implemented on-chip. The implementation of current ratio structures makes the on-chip implementation of components practical and at the same time makes possible the selection and implementation on-chip of at least one such component, multiple components or combinations of such components.

(36) The integrated circuit (U2) (IQS127 from Azoteq (Pty) Ltd) comprises all the building blocks for the capacitive measurement circuit including the current mirror for scaling the charge transferred from the sense plate (which is connected to pad SNS_PLT) to U2 and the capacitive cancellation circuit that contains several capacitors to select from to predetermine the capacitance that is removed. An external resistor R.sub.1 is used to increase protection against electrostatic discharge (ESD) from the sense plate to U2. Capacitors C.sub.1 and C.sub.2 are for voltage regulation and help to assure a good, stable and noise free supply voltage to the IC U2. The device (U2) provides two outputs namely an indication of proximity detection on POUT, and a touch (i.e. much stronger capacitance variation detected) on TOUT.

(37) FIGS. 10A and 10B are two flow charts of respective algorithms for automatic adjustment of parameters to achieve certain performance objectives. The algorithm in FIG. 10A uses the largest acceptable size of C.sub.R as a metric to aim for and requires less capacitive cancellation to achieve a certain charge transfer count per cycle. The algorithm in FIG. 10B aims to have the largest acceptable capacitive cancellation amount and this results in a smaller C.sub.R value. The FIG. 10B algorithm also results in more sensitive settings for capacitive measurements. The current mirror ratios can also be used to interplay with the C.sub.R values or the capacitive cancellation.

(38) Explanation of ATI Terms

(39) TABLE-US-00001 ATI Antenna Tuning Implementation. C.sub.R Reference Capacitor (Four size selections) CC Bits Capacitance Cancellation size selection (0 to 256) Current Sample The number of charge transfers for the current sense channel ATI Target The preselected number of charge transfers that the ATI algorithm aims for CRI_DIV The C.sub.R current mirror divider ratio (0 = 32/1 = 128) ATI_BUSY Flag that indicates the ATI is in progress for the current sense channel CRI_DIV Select flag Flag to indicate the C.sub.R current mirror divider ratio must be selected CR Select flag Flag to indicate the C.sub.R size must be selected ATI_INIT flag Flag to indicate the initial difference (with all the PCC bits set to zero) between the current sample and the ATI target must be stored ATI_AT_MIN flag Flag to indicate the current sample cannot be adjusted lower ATI_AT_MAX flag Flag to indicate the current sample cannot be adjusted higher Long Term Average A filtered value of the current sample Reseed Flag Flag to indicate the long term average must be loaded with the current sample value
Explanation of the ATI Algorithm

(40) The aim of the ATI algorithm is to adjust the relevant parameters (C.sub.R size, C.sub.R current mirror ratio and the PCC bits) to get the current sample as close as possible to the ATI target count value. This will ensure that the circuit adjusts itself to obtain repeatable performance despite manufacturing and other tolerances.

(41) The ATI algorithm can be implemented in a number of ways. Two possible algorithms are presented. The first algorithm in FIG. 10A (Stability Enhancement) will result in a big C.sub.R being selected with a smaller capacitive cancellation (CC) value. This produces a more stable system that is less sensitive and also less noise sensitive. The second algorithm in FIG. 10B (Sensitivity Enhancement) will result in the selection of a big CC value. This produces a more sensitive system that can be used to maximize proximity detection distance.

(42) Algorithm 1 (Stability Enhancement)FIG. 10A

(43) During initialization for ATI [102], the ATI_BUSY flag is set to indicate to the system that ATI is in progress. The CC bits are set to zero, the current mirror divider ratio is set to a higher value and the C.sub.R size is set to a maximum value. The CRI_DIV Select flag is also set to force the system to do a determination if the higher value is the optimal selection.

(44) The system then completes a charge transfer cycle [104]. If it is determined that the CRI_DIV Select flag is set [106] a test is done to check whether the current sample is bigger than the ATI target [138]. If it is bigger the current mirror divider ratio is changed to the lower value [136], the CRI_DIV Select flag is cleared and the CR Select flag is set [134] to force the selection of the appropriate C.sub.R size.

(45) After the next charge transfer cycle is completed the CR Select flag is set [108]. The current sample is checked against the ATI target [142]. If the current sample is smaller than the ATI target the CR Select flag is cleared and the ATI_INIT flag is set [140] to start the process of determining the appropriate CC value to get the current sample the closest to the ATI target.

(46) If the current sample is bigger than the ATI target the C.sub.R size is reduced [144] to the next smaller value until the current sample is smaller than the ATI target. If the minimum value of C.sub.R size is reached [146] the ATI_AT_MIN flag is set [148] to indicate the current sample cannot be adjusted any lower than its current value.

(47) After the next charge transfer cycle is completed the ATI_INIT flag is set [110]. The current CC value (zero) is stored together with the difference between the current sample and the target [134]. The ATI_INIT flag is also cleared.

(48) The algorithm will then keep increasing the CC value [120] and storing the smallest difference value and the CC value that yielded the smallest difference value [118] until either the current sample is at double the target value [112] or the maximum value for the CC is reached [122]. On either of these conditions the CC value that yielded the smallest difference in relation to the target is loaded and a reseed is forced [130].

(49) Algorithm 2 (Sensitivity Enhancement)FIG. 10B

(50) During initialization for ATI [202], the ATI_BUSY flag is set to indicate to the system that ATI is in progress. The CC bits are set to a third of the maximum value. This will result in the algorithm selecting a smaller C.sub.R value with a higher CC value resulting in higher sensitivity. The current mirror divider ratio is set to the lower value and the C.sub.R size is set to the maximum value. The CRI_DIV Select flag is also set to force the system to do a determination if the lower value is the optimal selection.

(51) The system then completes a charge transfer cycle [204]. If it is determined that the CRI_DIV Select flag is set [206] a test is done to check whether the current sample is smaller than the ATI target [238]. If it is smaller, the current mirror divider ratio is changed to the higher value [236], the CRI_DIV Select flag is cleared and the CR Select flag is set [234] to force the selection of the appropriate C.sub.R size.

(52) After the next charge transfer cycle is completed the CR Select flag will be set [208]. The current sample is checked against the ATI target [242]. If the current sample is smaller than the ATI target the CR Select flag is cleared and the ATI_INIT flag is set [240] to start the process of determining the appropriate CC value to get the current sample the closest to the ATI target. The CC value is also set to zero.

(53) If the current sample is bigger than the ATI target the C.sub.R size is reduced [244] to the next smaller value until the current sample is smaller than the ATI target. If the minimum value of C.sub.R size is reached the ATI_AT_MIN flag is set [248] to indicate the current sample cannot be adjusted any lower than its current value.

(54) After the next charge transfer cycle is completed the ATI_INIT flag is set [210]. The current CC value (zero) is stored together with the difference between the current sample and the target [234]. The ATI_INIT flag is also cleared.

(55) The algorithm will then keep increasing the CC value [220] and storing the smallest difference value and the CC value that yielded the smallest difference value [218] until either the current sample is at double the target value [212] or the maximum value for the CC is reached [222]. On either of these conditions the CC value that yielded the smallest difference in relation to the target is loaded and a reseed is forced [230]

(56) FIG. 11 illustrates an example of a circuit-noise detection structure which is specifically aimed at noise generated on-chip. An example of the type of noise is Random Telegraph Signal noise (RTS noise) which results in substantial steps in the measurements and which is it not typically Gaussian by nature. The normal implementation incorporates the sense plate, C.sub.RX (a reference capacitor for external measurement) and C.sub.CX (a reference capacitor for capacitance cancellation of the external sense plate), connected through switches S.sub.1, S.sub.3 and S.sub.5 respectively to a measurement circuit (IC) 320. S.sub.1 is the PASS switch in a charge transfer implementation. The UP switch is not shown. C.sub.MI (internal measurement capacitor) is used to emulate the operation of a sense plate. This is done wholly within the integrated circuit to avoid environmental influences. C.sub.CI defines the amount of charge to be removed for the internal measurement. It is important to incorporate as many elements of the circuit as possible for the internal measurement, within the IC.

(57) It is possible but not essential for the internal and external measurements to work concurrently. For example, when one is in the UP phase, the other can do the PASS phase and vice versa. An additional trip circuit is required for the internal measurements. Detection of a step or change in measurement on the internal C.sub.RI indicates a change in the transfer function of the capacitance measurement circuit 320. This is then used for the filtering of the measurement data.

(58) In one embodiment the detection of RTS noise in accordance with the preceding description triggers an analysis of the normal measurement data and an automatic learning algorithm is then implemented to model the noise manifestation from these measurements. It is then possible to remove the effects of this noise automatically from the measurement signal when the noise occurs or when it disappears.

(59) In another embodiment the size (amplitude) of the internal noise is used to derive an effect (through scaling etc) of the noise on the normal measurement and the effect of the noise can be removed.

(60) Various levels of complexity can be involved and this will depend on the requirements in the application and also on the processing resources available to the designers. In a simple form the indication or triggering of a proximity event detection is inhibited for a period when noise is detected.

(61) In analysis it has been found that noise is introduced into the current mirror structures and that when the capacitance cancellation is then performed this noise is amplified. FIG. 12 shows an implementation for capacitive cancellation to reduce or remove the effect of noise amplification when the charge removal is done after the current mirror.

(62) A switch S.sub.1 is a PASS switch that transfers the charge from the Sense Plate (C.sub.M) to the current mirror (M1) that mirrors the charge which is transferred as per the ratio (1:X) into the C.sub.R where the charge is accumulated to be measured in some way. For example, a fixed trip level may be set and the number of transfers may be counted, or a fixed number of transfers may be done and then the voltage level may be measured with an ND converter.

(63) Essentially the charge from the sense plate is used to change the capacitors C.sub.1 to C.sub.X, (those connected) before the rest of the charge flows into the current mirror. When S.sub.1 is later opened, a switch S.sub.2 is closed to dump the charge that was accumulated in the capacitance cancellation capacitors. These capacitors must then be charged each time a charge transfer occurs.

(64) In the measurement of small capacitance values the parasitic capacitance inherent in the capacitance cancellation structure may have a negative effect. In this case the structure may be pre-charged (but no cancellation capacitor is switched in) before the charge transfer cycle, to eliminate unwanted parasitic capacitance.

(65) The capacitors C.sub.1 to C.sub.X are not effectively used because the input to the current mirror only allows the current mirror to be charged to a threshold value at its input (0.7V), whereas the sense plate is charged to a much higher voltage. Hence if these capacitors are pre-charged to a negative voltage it will help to improve size efficiency.

(66) Experience has shown that noise is introduced through the current mirror structures. It has not been determined if higher ratios exacerbate this issue, but in another embodiment (shown in FIG. 13) a simple capacitive charge divider structure is implemented to achieve a scaling effect of the charge transferred from the sense plate (C.sub.M) to the measurement circuit. This is important to keep on-chip components, such as capacitors and currents, within practical limits. In FIG. 13 the switch S.sub.2 is closed to charge the sense plate which is effectively a capacitor C.sub.M. A switch S.sub.2 is then opened and S.sub.1 is closed. This will pass the charge from the sense plate to the charge transfer measurement circuit. If S.sub.3 is closed and S.sub.4 is open the charge will be fully transferred and the capacitive cancellation circuit 322 will perform its function on this charge in accordance with its design.

(67) When S.sub.1 is closed, S.sub.3 is open and S.sub.4 is closed the charge from C.sub.M is divided between C.sub.M and C.sub.DIV. In the next operation S.sub.1 is opened and S.sub.3 closed. The circuit then operates as before but the charge will have been divided according to the ratio of C.sub.M and C.sub.DIV. When S.sub.1 is opened the process to charge C.sub.M through S.sub.2 can start again. It is also preferable that C.sub.DIV is chosen so that when the charge division is done, the voltage on C.sub.DIV is still higher than the input to the current mirror structure (typically a diode voltage drop). This can also be ensured by not discharging C.sub.DIV between each charge transfer cycle. This will change the ratio of charge division but can easily be calculated and accounted for.

(68) The use of the C.sub.DIV approach reduces the sensitivity at very high values of C.sub.M but provides a large input range.