DYNAMIC IMPEDANCE IMAGING SYSTEM

Abstract

A dynamic impedance imaging system includes a dynamic impedance imaging sensor, an impedance detection and flow rate measurement module and an electrical impedance tomography (EIT) instrument. The impedance detection and flow rate measurement module is configured to detect an abnormal particle flowing through the dynamic impedance imaging sensor to obtain a flow rate of the abnormal particle, and generate a synchronous trigger signal. The EIT instrument is configured to inject a sinusoidal excitation current into the dynamic impedance imaging sensor under the trigger of the synchronous trigger signal, perform multi-channel interleaved sampled for the abnormal particle according to the flow rate to acquire multi-channel sampled data, and calibrate the multi-channel sampled data to implement impedance tomography imaging for the abnormal particle.

Claims

1. A dynamic impedance imaging system, comprising a dynamic impedance imaging sensor, an impedance detection and flow rate measurement module and an electrical impedance tomographic (EIT) instrument, wherein the dynamic impedance imaging sensor is connected to the impedance detection and flow rate measurement module; the dynamic impedance imaging sensor is configured to determine whether there is an abnormal particle flowing through a tube; the impedance detection and flow rate measurement module is configured to detect the abnormal particle flowing through the dynamic impedance imaging sensor to obtain a flow rate of the abnormal particle, and generate a synchronous trigger signal; the EIT instrument is respectively connected to the impedance detection and flow rate measurement module and the dynamic impedance imaging sensor; the EIT instrument is configured to inject a sinusoidal excitation current into the dynamic impedance imaging sensor under triggering of the synchronous trigger signal, to perform multi-channel interleaved sampled for the abnormal particle according to the flow rate to acquire multi-channel sampled data, and to calibrate the multi-channel sampled data to implement impedance tomography imaging for the abnormal particle.

2. The dynamic impedance imaging system according to claim 1, wherein the dynamic impedance imaging sensor comprises a first annular electrical signal receiver, a second annular electrical signal receiver and an annular channel imaging sensor arranged in sequence according to direction of a fluid; each of the first annular electrical signal receiver, the second annular electrical signal receiver and the annular channel imaging sensor is provided with a plurality of electrodes; the first annular electrical signal receiver and the second annular electrical signal receiver are respectively connected to the impedance detection and flow rate measurement module through corresponding electrodes; and the annular channel imaging sensor is connected to the EIT instrument through the corresponding electrodes.

3. The dynamic impedance imaging system according to claim 2, wherein the first annular electrical signal receiver is provided with two electrodes embedded in the tube wall; the second annular electrical signal receiver is provided with two electrodes embedded in the tube wall; and the annular channel imaging sensor is provided with sixteen electrodes.

4. The dynamic impedance imaging system according to claim 2, wherein the impedance detection and flow rate measurement module comprises a first field-programmable gate array (FPGA) calculation and control module, an orthogonal excitation generation module, a first mixer, a second mixer, a first comparator and a second comparator; the orthogonal excitation generation module is respectively connected to the first FPGA calculation and control module, one electrode of the first annular electrical signal receiver, one electrode of the second annular electrical signal receiver, the first mixer and the second mixer; another electrode of the first annular electrical signal receiver is connected to the first mixer; another electrode of the second annular electrical signal receiver is connected to the second mixer; and the orthogonal excitation generation module is configured to generate a first orthogonal excitation signal and a second orthogonal excitation signal; the first annular electrical signal receiver is configured to receive the second orthogonal excitation signal, and output a voltage signal to the first mixer; and the second annular electrical signal receiver is configured to receive the second orthogonal excitation signal, and output a voltage signal to the second mixer; the first mixer and the second mixer are respectively connected to the first FPGA calculation and control module; the first mixer is configured to mix the first orthogonal excitation signal with the voltage signal output by the first annular electrical signal receiver to obtain a first mixing signal, and mix the second orthogonal excitation signal with the voltage signal output by the first annular electrical signal receiver to obtain a second mixing signal; the second mixer is configured to mix the first orthogonal excitation signal with the voltage signal output by the second annular electrical signal receiver to obtain a third mixing signal, and mix the second orthogonal excitation signal with the voltage signal output by the second annular electrical signal receiver to obtain a fourth mixing signal; the first FPGA calculation and control module is configured to calculate a first impedance amplitude information between the first annular electrical signal receiver and the second annular electrical signal receiver according to the first mixing signal and the second mixing signal, and calculate a second impedance amplitude information between the first annular electrical signal receiver and the second annular electrical signal receiver according to the third mixing signal and the fourth mixing signal; the first comparator is configured to generate a first pulse signal according to the first impedance amplitude information; the second comparator is configured to generate a second pulse signal according to the second impedance amplitude information; the first FPGA calculation and control module is further configured to calculate the flow rate of the abnormal particle according to the first pulse signal and the second pulse signal; and the second pulse signal is used as the synchronous trigger signal to trigger the EIT instrument.

5. The dynamic impedance imaging system according to claim 4, wherein the impedance detection and flow rate measurement module further comprises a first amplifier, a second amplifier, a third amplifier, a first current amplifier and a second current amplifier; the orthogonal excitation generation module is connected to an input terminal of the first amplifier; an output terminal of the first amplifier is respectively connected to one electrode of the first annular electrical signal receiver and one electrode of the second annular electrical signal receiver; another electrode of the first annular electrical signal receiver is connected to the first mixer through the first current amplifier and the second amplifier in sequence; another electrode of the second annular electrical signal receiver is connected to the second mixer through the second current amplifier and the third amplifier in sequence.

6. The dynamic impedance imaging system according to claim 5, wherein the impedance detection and flow rate measurement module further comprises a first low-pass filter and a second low-pass filter; the first low-pass filter is connected between the first mixer and the first FPGA calculation and control module; and the second low-pass filter is connected between the second mixer and the first FPGA calculation and control module.

7. The dynamic impedance imaging system according to claim 6, wherein the impedance detection and flow rate measurement module further comprises a first analog to digital converter (ADC), a second ADC, a third ADC, a fourth ADC, a first digital to analog converter (DAC) and a second DAC; a first output terminal of the first low-pass filter is connected to the first FPGA calculation and control module through the first ADC, and a second output terminal of the first low-pass filter is connected to the first FPGA calculation and control module through the second ADC; a first output terminal of the second low-pass filter is connected to the first FPGA calculation and control module through the third ADC, and a second output terminal of the second low-pass filter is connected to the first FPGA calculation and control module through the fourth ADC; the first FPGA calculation and control module is connected to the first comparator through the first DAC; and the first FPGA calculation and control module is connected to the second comparator through the second DAC.

8. The dynamic impedance imaging system according to claim 2, wherein the EIT instrument comprises an analog switch array, a multi-channel interleaved sampled module, a second FPGA calculation and control module and an advanced reduced instruction set computer (RISC) machine (ARM) processor; the second FPGA calculation and control module is respectively connected to the multi-channel interleaved sampled module, the analog switch array and the ARM processor; the analog switch array is connected to the plurality of electrodes of the annular channel imaging sensor; the analog switch array is connected to the multi-channel interleaved sampled module; the analog switch array is configured to inject a sinusoidal excitation current into the annular channel imaging sensor; the multi-channel interleaved sampled module is configured to, according to a principle of adjacent excitation and adjacent measurement, perform interleaved sampling on signals output by each electrode of the annular channel imaging sensor to acquire multi-channel sampled data; the second FPGA calculation and control module is configured to calibrate the multi-channel sampled data to acquire calibrated sampled data, and calculate voltage data from the calibrated sampled data; and the ARM processor is configured to implement impedance tomography imaging of the abnormal particle according to the voltage data.

9. The dynamic impedance imaging system according to claim 8, wherein the second FPGA calculation and control module comprises a narrow-band mode calibration module, a broad-band mode calibration module and an amplitude demodulation module; the narrow-band mode calibration module is configured to calibrate the multi-channel sampled data to acquire calibrated sampled data when f.sub.in<⅛f.sub.s, where f.sub.in is an input frequency of a measured single-dot-frequency signal, and f.sub.s is a sampled frequency of the multi-channel interleaved sampled module; the broad-band mode calibration module is configured to calibrate the multi-channel sampled data to acquire calibrated sampled data when ⅛f.sub.s≤<¼f.sub.s; and the amplitude demodulation module is configured to calculate voltage data from the calibrated sampled data.

10. The dynamic impedance imaging system according to claim 9, wherein the narrow-band mode calibration module comprises a finite impulse response (FIR) low-pass filter; the FIR low-pass filter is configured to perform low-pass filtering on the multi-channel sampled data; the broad-band mode calibration module comprises an orthogonal data generation unit, a fast Fourier transform (FFT) unit and a gain error and phase error calibration unit; the orthogonal data generation unit is configured to generate a plurality of sets of orthogonal sequences; the FFT unit is configured to perform FFT for the multi-channel sampled data; and the gain error and phase error calibration unit is configured to eliminate a time phase error and a gain error of the sampled data after the FFT according to the orthogonal sequences.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to illustrate the technical solutions in the embodiments of the present disclosure or in the prior art more clearly, the accompanying drawings required in the embodiments are introduced below briefly. Apparently, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and other drawings may be obtained from these accompanying drawings by those of ordinary skill in the art without creative labor.

[0035] FIG. 1 is a structural schematic diagram of a dynamic impedance imaging system provided by an embodiment of the present disclosure.

[0036] FIG. 2 is a structural block diagram of the dynamic impedance imaging system provided by an embodiment of the present disclosure.

[0037] FIG. 3 is a structural block diagram of a dynamic impedance imaging sensor provided by an embodiment of the present disclosure.

[0038] FIG. 4 is a structural block diagram of an impedance detection and flow rate measurement module provided by an embodiment of the present disclosure.

[0039] FIG. 5 is a structural block diagram of an electrical impedance tomographic (EIT) instrument provided by an embodiment of the present disclosure.

[0040] FIG. 6 is a structural block diagram of a second FPGA calculation and control module provided by an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The technical solutions of the embodiments of the present disclosure are clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are merely a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative labor should fall within the protection scope of the present disclosure.

[0042] To make the above object, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementations.

[0043] The dynamic impedance imaging system of the embodiments of the present disclosure provides, which is applied to dynamic imaging of cells, implement the capturing of an abnormal particle in a fluid by integrating (utilizing) the core technology of a microfluidic single-cell resistance detection system based on an EIT instrument. This embodiment combines the interleaved sampled technology with the EIT technology, such that the dynamic impedance imaging system can meet the requirements for bandwidth and SNR in the fields of biomedicine and multiphase flow.

[0044] FIG. 1 is a structural schematic diagram of the dynamic impedance imaging system provided by an embodiment of the present disclosure, and FIG. 2 is a structural block diagram of the dynamic impedance imaging system provided by an embodiment of the present disclosure. Referring to FIGS. 1 to 2, the dynamic impedance imaging system according to the present embodiment includes a dynamic impedance imaging sensor, an impedance detection and flow rate measurement module and the EIT instrument. The dynamic impedance imaging sensor is connected to the impedance detection and flow rate measurement module. The dynamic impedance imaging sensor is configured to determine whether there is an abnormal particle flowing through a tube. The impedance detection and flow rate measurement module is configured to detect the abnormal particle flowing through the dynamic impedance imaging sensor to obtain a flow rate of the abnormal particle, and generate a synchronous trigger signal to start the EIT instrument. The EIT instrument is respectively connected to the impedance detection and flow rate measurement module and the dynamic impedance imaging sensor. The EIT instrument is configured, in response to the triggering of the synchronous trigger signal, to inject a sinusoidal excitation current into the dynamic impedance imaging sensor, to perform multi-channel interleaved sampled for the abnormal particle according to the flow rate to acquire multi-channel sampled data, and to calibrate the multi-channel sampled data to implement impedance tomography imaging for the abnormal particle.

[0045] FIG. 3 is a structural block diagram of the dynamic impedance imaging sensor provided by an embodiment of the present disclosure. Referring to FIG. 3, the dynamic impedance imaging sensor includes a first annular electrical signal receiver 35, a second annular electrical signal receiver and an annular channel imaging sensor 42 arranged in sequence according to flow direction of a fluid. The first annular electrical signal receiver 35, the second annular electrical signal receiver 39 and the annular channel imaging sensor 42 each are provided with multiple electrodes. The first annular electrical signal receiver 35 and the second annular electrical signal receiver are respectively connected to the impedance detection and flow rate measurement module through the corresponding electrodes. The annular channel imaging sensor 42 is connected to the EIT instrument through the corresponding electrodes.

[0046] As an optional implementation, the dynamic impedance imaging sensor includes a tube wall 36. The first annular electrical signal receiver 35 is provided with two electrodes embedded in the tube wall 36, which are an electrode 37 and an electrode 38 respectively. The second annular electrical signal receiver 39 is provided with two electrodes embedded in the tube wall 36, which are an electrode 40 and an electrode 41 respectively. The annular channel imaging sensor 42 is provided with sixteen electrodes, and the electrodes of the part of the annular channel imaging sensor 42 that contacts the tube wall 36 are embedded in the tube wall 36. The tube wall 36 is made of a transparent perspex material. The distance between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39 is L.sub.1, and the distance between the second annular electrical signal receiver 39 and the annular channel imaging sensor 42 is L.sub.2 . The flow direction of the fluid and the abnormal particle is shown by an arrow in FIG. 3. When the abnormal particle flows through the first annular electrical signal receiver 35, the impedance detection and flow rate measurement module generates a first pulse signal P.sub.1. Similarly, when the abnormal particle flows through the second annular electrical signal receiver 39, the impedance detection and flow rate measurement module generates a second pulse signal P.sub.2. Provided that the distance L.sub.1 between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39 is known, the flow rate of the abnormal particle can be obtained by acquiring a time difference t.sub.1 between the first pulse signal P.sub.1 and the second pulse signal P.sub.2, namely, v=L.sub.1/t.sub.1. The second pulse signal P.sub.2 is used as a start signal of the EIT instrument. When the EIT instrument detects the second pulse signal P.sub.2, the EIT instrument starts to perform excitation and measurement imaging.

[0047] FIG. 4 is a structural block diagram of the impedance detection and flow rate measurement module provided by an embodiment of the present disclosure. Referring to FIG. 4, the impedance detection and flow rate measurement module includes a first FPGA calculation and control module 22, an orthogonal excitation generation module 1, a first mixer 2, a second mixer 13, a first comparator 11 and a second comparator 12. The first mixer 2 and the second mixer 13 are high precision mixers.

[0048] The orthogonal excitation generation module 1 is respectively connected to the first FPGA calculation and control module 22, one electrode of the first annular electrical signal receiver 35, one electrode of the second annular electrical signal receiver 39, the first mixer 2 and the second mixer 13. Another electrode of the first annular electrical signal receiver 35 is connected to the first mixer 2. Another electrode of the second annular electrical signal receiver 39 is connected to the second mixer 13. The orthogonal excitation generation module 1 is configured to generate a first orthogonal excitation signal and a second orthogonal excitation signal.

[0049] The first annular electrical signal receiver 35 is configured to receive the second orthogonal excitation signal, and output a voltage signal to the first mixer 2. The second annular electrical signal receiver 39 is configured to receive the second orthogonal excitation signal, and output a voltage signal to the second mixer 13.

[0050] The first mixer 2 and the second mixer 13 are respectively connected to the first FPGA calculation and control module 22. The first mixer 2 is configured to mix the first orthogonal excitation signal with the voltage signal output by the first annular electrical signal receiver 35 to obtain a first mixing signal, and mix the second orthogonal excitation signal with the voltage signal output by the first annular electrical signal receiver 35 to obtain a second mixing signal. The second mixer 13 is configured to mix the first orthogonal excitation signal with the voltage signal output by the second annular electrical signal receiver 39 to obtain a third mixing signal, and mix the second orthogonal excitation signal with the voltage signal output by the second annular electrical signal receiver 39 to obtain a fourth mixing signal.

[0051] The first FPGA calculation and control module 22 is configured to calculate a first impedance amplitude information between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39 according to the first mixing signal and the second mixing signal, and calculate a second impedance amplitude information between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39 according to the third mixing signal and the fourth mixing signal.

[0052] The first comparator 11 is configured to generate a first pulse signal according to the first impedance amplitude information. The second comparator 12 is configured to generate a second pulse signal according to the second impedance amplitude information. The first FPGA calculation and control module 22 is further configured to calculate the flow rate of the abnormal particle according to the first pulse signal and the second pulse signal. The second pulse signal is used as the synchronous trigger signal to trigger the EIT instrument.

[0053] As an optional implementation mode, the impedance detection and flow rate measurement module further includes a first amplifier 6, a second amplifier 50, a third amplifier 18, a first current amplifier 7 and a second current amplifier 17. The orthogonal excitation generation module 1 is connected to an input terminal of the first amplifier 6. An output terminal of the first amplifier 6 is respectively connected to one electrode of the first annular electrical signal receiver 35 and one electrode of the second annular electrical signal receiver 39. Another electrode on the first annular electrical signal receiver 35 is connected to the first mixer 2 through the first current amplifier 7 and the second amplifier 50 in sequence. Another electrode of the second annular electrical signal receiver 39 is connected to the second mixer 13 through the second current amplifier 17 and the third amplifier 18 in sequence.

[0054] As an optional implementation, the impedance detection and flow rate measurement module further includes a first low-pass filter 3 and a second low-pass filter 14. The first low-pass filter 3 is connected between the first mixer 2 and the first FPGA calculation and control module 22. The second low-pass filter 14 is connected between the second mixer 13 and the first FPGA calculation and control module 22.

[0055] As an optional implementation, the impedance detection and flow rate measurement module further includes a first analog to digital converter (ADC) 4, a second ADC 5, a third ADC 15, a fourth ADC 16, a first digital to analog converter (DAC) 8 and a second DAC 9. A first output terminal of the first low-pass filter 3 is connected to the first FPGA calculation and control module 22 through the first ADC 4, and a second output terminal of the first low-pass filter 3 is connected to the first FPGA calculation and control module 22 through the second ADC 5. A first output terminal of the second low-pass filter 14 is connected to the first FPGA calculation and control module 22 through the third ADC 15, and a second output terminal of the second low-pass filter 14 is connected to the first FPGA calculation and control module 22 through the fourth ADC 16. The first FPGA calculation and control module 22 is connected to the first comparator 11 through the first DAC 8. The first FPGA calculation and control module 22 is connected to the second comparator 12 through the second DAC 9.

[0056] As an optional implementation, the impedance detection and flow rate measurement module further includes a reference voltage 10, and the reference voltage 10 is connected to the first comparator 11 and the second comparator 12, respectively.

[0057] A specific implementation principle of the impedance detection and flow rate measurement module is as follows.

[0058] The orthogonal excitation generation module generates the first orthogonal excitation signal I1=sin(ω.sub.0t+φ) and the second orthogonal excitation signal Q=cos(ω.sub.0t+φ), where ω.sub.0 is an angular frequency of the excitation signal, is a phase, and t is time. The second orthogonal excitation signal Q is input to the first amplifier 6, and is amplified by the first amplifier 6 to obtain a signal V.sub.o=A cos(ω.sub.0t+φ), where A is the amplitude of the signal. V.sub.o is applied to one electrode of the first annular electrical signal receiver 35 and one electrode of the second annular electrical signal receiver 39 as an excitation signal. Another electrode of the first annular electrical signal receiver 35 is connected to the first current amplifier 7, and another electrode of the second annular electrical signal receiver 39 is connected to the second current amplifier 17. Assuming that an impedance between the two electrodes of the first annular electrical signal receiver 35 and an impedance between the two electrodes of the second annular electrical signal receiver 39 are Z.sub.x, then a current input to the first current amplifier 7 and the second current amplifier 17 is:

[00001]$I=\frac{V_o}{R_1+Z_x},$

[0059] where R.sub.1 is a resistance of a pull-down resistor.

[0060] An output voltage of the first current amplifier 7 and the second current amplifier 17 is:

[00002]$V=\frac{\mathrm{Vo}}{1+Z_x/R_1};$

where 1+Z.sub.x/R.sub.1=A.sub.Z.sup.1<ϕ.sub.Z.sup.1, A.sub.Z.sup.1 is an amplitude of 1+Z.sub.x/R.sub.1, and ϕ.sub.Z.sup.1 is a phase angle of 1+Z.sub.x/R.sub.1. An output voltage generated by an output signal of the first current amplifier 7 through the second amplifier 50 and an output voltage generated by an output signal of the second current amplifier 17 through the third amplifier 18 are:

[00003]$\hat{V}=\frac{A_{1}A}{A_Z^1}\cos \left({\omega }_{0}t+\varphi -{\varphi }_Z^1\right);$

where A.sub.1 is a gain of the second amplifier 50 and the third amplifier 18. {circumflex over (V)} is mixed with I1 and Q in the first mixer 2 and the second mixer 13. The first low-pass filter 3 and the second low-pass filter 14 perform low-pass filtering on a mixing result to output

[00004]$\frac{A_{1}A}{A_Z^1}\sin \left({\varphi }_Z^1\right)\mathrm{and}\frac{A_{1}A}{A_Z^1}\cos \left({\varphi }_Z^1\right)$

respectively. The first ADC 4, the second ADC 5, the third ADC 15 and the fourth ADC 16 then sample output analog signals of the first low-pass filter 3 and the second low-pass filter 14, and send sampling results to the first FPGA calculation and control module 22 for calculation, so as to obtain the impedance amplitude information between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39:

[00005]$Z=\frac{A_{1}A}{A_Z^1}.$

[0061] Meanwhile, the first FPGA calculation and control module 22 outputs the above impedance amplitude information in form of analog voltage through the first DAC 8 and the second DAC 9. If the impedance Z.sub.x between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39 does not change, the output of the first DAC 8 and the second DAC 9 is a direct current (DC) level. If there is an abnormal particle flowing through the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39, the impedance Z.sub.x between the electrodes increases or decreases, and the above impedance amplitude information Z decreases or increases accordingly. When the abnormal particle flows through the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39, the first DAC 8 and the second DAC 9 generate negative or positive pulses. The reference voltage 10, the first comparator 11 and the second comparator 12 shape the pulse signals generated by the first DAC 8 and the second DAC 9 into low-voltage complementary metal oxide semiconductor (LVCMOS) pulse signals P.sub.1 and P.sub.2. The first pulse signal P.sub.1 is used as a timing start signal, and the second pulse signal P.sub.2 is used as a timing end signal. By calculating the time interval t.sub.1 between P.sub.1 and P.sub.2, the flow rate can be calculated when L.sub.1 in FIG. 3 is known, that is, v=L.sub.1/t.sub.1. L.sub.1 is the distance between the first annular electrical signal receiver 35 and the second annular electrical signal receiver 39. P.sub.2 is also used as the synchronous trigger signal of the EIT instrument. When the second pulse signal P.sub.2 arrives, the EIT instrument starts to operate.

[0062] FIG. 5 is a structural block diagram of the EIT instrument provided by an embodiment of the present disclosure. Referring to FIG. 5, the EIT instrument includes an analog switch array 19, a multi-channel interleaved sampled module, a second FPGA calculation and control module 34 and an ARM processor 44. In this embodiment, the multi-channel interleaved sampled module is a four-channel interleaved sampled module, and the multi-channel interleaved sampled module includes a fifth ADC 27, a sixth ADC 28, a seventh ADC 29 and an eighth ADC 30. The fifth ADC 27, the sixth ADC 28, the seventh ADC 29 and the eighth ADC 30 are all 24-bit high-precision ADCs.

[0063] The second FPGA calculation and control module 34 is respectively connected to the multi-channel interleaved sampled module, the analog switch array 19 and the ARM processor 44. The analog switch array 19 is connected to the multiple electrodes of the annular channel imaging sensor 42. The analog switch array 19 is connected to the multi-channel interleaved sampled module. The analog switch array 19 is configured to inject a sinusoidal excitation current into the annular channel imaging sensor 42. The multi-channel interleaved sampled module is configured to, according to a principle of adjacent excitation and adjacent measurement, perform interleaved sampling on the signals output by each electrode of the annular channel imaging sensor 42 to acquire multi-channel sampled data. The second FPGA calculation and control module 34 is configured to calibrate the multi-channel sampled data to acquire calibrated sampled data, and calculate voltage data from the calibrated sampled data. The ARM processor 44 is configured to implement impedance tomography imaging of the abnormal particle according to the voltage data.

[0064] As an optional implementation, the EIT instrument further includes a third DAC 21, a constant current source 43, an instrumentation amplifier 20, a band-pass filter 26, a liquid crystal display (LCD) 23, a universal serial bus (USB) driver module 24 and a personal computer (PC) 25. A specific connection relationship of these components is shown in FIG. 5.

[0065] As an optional implementation, the second FPGA calculation and control module 34 includes a narrow-band mode calibration module 31, a broad-band mode calibration module 32 and an amplitude demodulation module 33. The narrow-band mode calibration module 31 is configured to calibrate the multi-channel sampled data to acquire calibrated sampled data when f.sub.in<⅛f.sub.s, where f.sub.in is an input frequency of a measured single-dot-frequency signal, and f.sub.s is a sampled frequency of the multi-channel interleaved sampled module. The broad-band mode calibration module 32 is configured to calibrate the multi-channel sampled data to acquire calibrated sampled data when ⅛f.sub.s≤f.sub.in<¼f.sub.s. The amplitude demodulation module 33 is configured to calculate voltage data from the calibrated sampled data.

[0066] A specific implementation principle of the EIT instrument is as follows.

[0067] When the trigger signal P.sub.2 arrives, the EIT instrument starts operating. The second FPGA calculation and control module 34 generates a sinusoidal excitation current through the third DAC 21 and the constant current source 43, and injects the sinusoidal excitation current into the annular channel imaging sensor through the analog switch array 19. According to a principle of adjacent excitation and adjacent measurement, when the sinusoidal excitation current is injected into electrodes m and m+1 (m<15) of the annular channel imaging sensor 42, the remaining electrodes perform synchronous measurement. The time consumed for each injection and synchronous measurement is T.sub.1, and the time required to complete a frame of image is T=13T.sub.1, the voltage data acquired by the synchronous measurement is {tilde over (V)}, and the voltage data {tilde over (V)} is calculated by the amplitude demodulation module 33. The L.sub.2 in FIG. 3 approximately satisfies the following relationship:

L.sub.2≈T×v.

[0068] In actual operation, L.sub.2 is fixed in length after the processing of the annular channel imaging sensor 42 is completed, and the flow rate v is calculated by the flow rate calculation equation. Then the time for the system to generate each frame of image is calculated by the formula of the relationship approximately satisfied by the length of the above L.sub.2, so as to obtain the time T.sub.1 for each injection of excitation current and synchronous measurement.

[0069] where

[00006]$T_1=\frac{L_2}{13v}.$

[0070] A diameter of the annular channel imaging sensor 42 is D , and a three-dimensional (3D) sensitivity matrix is calculated for a cylindrical chamber with a length of L.sub.2 and a diameter of D:

J(x, y, z)=−∫∇xyz(I.sup.m1)∇xyz(I.sup.n)dV, 1≤x≤64, 1≤y≤64, 1≤z≤16;

[0071] where J(x, y, z) is the 3D sensitivity matrix of the system, x is a number of points in an X-axis direction, Y is a number of points in a Y-axis direction, Z is a number of points in a Z-axis direction, dV is a volume integral symbol, ∇xyz(I.sup.m1) is a gradient of a space potential for an ml-th excitation, and ∇xyz(I.sup.n) is a gradient of a space potential for an n -th excitation. Then the above 3D sensitivity matrix is reduced to two-dimensional (2D) to obtain a 2D sensitivity matrix:

[00007]$\tilde{J}\left(x,y\right)=\frac{\underset{z=1}{\overset{16}{.Math.}}J\left(x,y,z\right)}{16}.$

[0072] The above 2D sensitivity matrix and the measured voltage data {tilde over (V)} are used to implement the tomography imaging for an object in an area of the annular channel imaging sensor 42:

[00008]$\hat{\sigma }=\underset{\sigma }{\arg \min }\frac{1}{2}.Math.\tilde{V}-\tilde{J}\left(x,y\right)\sigma .Math.;$

[0073] where σ is a calculated intermediate variable, and σ becomes {circumflex over (σ)} after a calculation iteration is completed. The second FPGA calculation and control module 34 sends the sampling data {tilde over (V)} to the ARM processor 44. The ARM processor 44 completes the calculation of the tomography imaging, and displays the imaging result on the LCD. Alternatively, the acquired data may be sent to the PC 25 through the USB driver module 24 to complete calculation and graphic display.

[0074] In this embodiment, 4-channel interleaved sampled method is used to expand the sampled rate of the system while maintaining a high SNR. In actual use, a mismatch error caused by interleaved sampling needs to be calibrated. The narrow-band mode calibration module 31 and the broad-band mode calibration module 32 in the second FPGA calculation and control module are configured to calibrate the mismatch error of the-interleaved sampled data.

[0075] FIG. 6 is a structural block diagram of the second FPGA calculation and control module 34 provided by an embodiment of the present disclosure. Referring to FIG. 6, the narrow-band mode calibration module 31 includes a finite impulse response (FIR) low-pass filter 49. The FIR low-pass filter 49 is configured to perform low-pass filtering on the multi-channel sampled data.

[0076] The broad-band mode calibration module 32 includes an orthogonal data generation unit 47, a fast Fourier transform (FFT) unit 46 and a gain error and phase error calibration unit 48. The orthogonal data generation unit 47 is configured to generate multiple sets of orthogonal sequences. The FFT unit 46 is configured to perform FFT for the multi-channel sampled data. The gain error and phase error calibration unit 48 is configured to eliminate a time phase error and a gain error of the sampled data after the FFT according to the orthogonal sequences.

[0077] A specific implementation principle of the second FPGA calculation and control module 34 is as follows.

[0078] A calibration algorithm part of the second FPGA calculation and control module 34 includes a data stitching unit 45, the FFT unit 46, the gain error and phase error calibration unit 48, the orthogonal data generation unit 47, the FIR low-pass filter 49 and the amplitude demodulation module 33.

[0079] For a four-channel interleaved sampled system, when the input frequency of the measured single-dot-frequency signal is f.sub.in and the system sampled rate is f.sub.s, a noise spectrum caused by the time phase error and the gain error satisfies the following relationship:

[00009]${\omega }_n=\frac{k}{4}{\omega }_s\pm {\omega }_{\mathrm{in}},k=1,2;$

[0080] where ω.sub.in=2πf.sub.in, ω.sub.s=2πf.sub.s, and ω.sub.n is an angular frequency of the noise spectrum.

[0081] If the four-channel interleaved sampled data is x[n] and the number of points is N, the sampled data x[n] is subjected to FFT to obtain x[k]. If a peak spectral point generated by the input signal is at a position of k, noise points generated by the mismatch error are at the following positions:

[00010]$\{\begin{array}{c}{k}_2=N/4\pm k\\ k_3=N/2-k\end{array};$

[0082] where k.sub.2 and k.sub.3 are the positions of the noise points generated by the mismatch error. For a narrow-band operating mode, the frequency of the input signal is required to meet f.sub.in<⅛f.sub.s. After acquiring the four-channel interleaved sampled data, a low-pass filter h.sub.1[n] is configured to perform low-pass filtering to eliminate the noise spectrum caused by the time phase error and the gain error. h.sub.1[n] satisfies the following constraints:

[00011]$\{\begin{array}{c}{s}_f\le \frac{1}{8}{f}_s\\ s_a\ge 40\mathrm{dB}\end{array};$

[0083] where s.sub.f is a stopband cutoff frequency of h.sub.1[n], and s.sub.a is a stopband attenuation. The data after calibration in the narrow-band operating mode is {tilde over (x)}[n]=x[n]*h.sub.1[n], where * represents a convolution operation.

[0084] For a broad-band mode, the calibration algorithm calibrates as follows:

[0085] 1. given the four-channel interleaved sampled data x[n], performing FFT on the sampled data x[n] to obtain x[k], and calculating the position k.sub.1 of the peak spectral point in the input signal, where the number of points is N.

[0086] 2. Calculating positions of the noise points generated by the mismatch error

[00012]$\{\begin{array}{c}{k}_2=N/4\pm k_1\\ k_3=N/2-k_1\end{array}.$

[0087] 3. Calculating noise frequencies according to the above positions of the noise points

[00013]$\{\begin{array}{c}{f}_{k_1}=\frac{f_s}{N}\left(\frac{N}{4}+k_1\right)\\ f_{k_2}=\frac{f_s}{N}\left(\frac{N}{4}-k_1\right)\\ f_{k_3}=\frac{f_s}{N}\left(\frac{N}{2}-k_1\right)\end{array},$

[0088] where f.sub.k.sub.1, f.sub.k2, and f.sub.k3 are values of noise frequencies estimated according to the positions k.sub.2 and k.sub.3 of the noise points, respectively.

[0089] 4. Generating three sets of standard orthogonal sequences based on the above noise frequencies

[00014]$\{\begin{array}{c}{Q}_1\left[n\right]=\cos \left(2\pi f_{k_1}\frac{1}{f_s}n\right)\\ I_1\left[n\right]=\sin \left(2\pi f_{k_1}\frac{1}{f_s}n\right)\\ Q_2\left[n\right]=\cos \left(2\pi f_{k_2}\frac{1}{f_s}n\right)\\ I_2\left[n\right]=\sin \left(2\pi f_{k_2}\frac{1}{f_s}n\right)\\ Q_3\left[n\right]=\cos \left(2\pi f_{k_3}\frac{1}{f_s}n\right)\\ I_3\left[n\right]=\sin \left(2\pi f_{k_3}\frac{1}{f_s}n\right)\end{array}.$

[0090] where Q.sub.1[n] and I.sub.1[n] are a set of standard orthogonal sequences generated according to the noise frequency f.sub.k.sub.1 in Step 3; Q.sub.2[n] and I.sub.2[n] are a set of standard orthogonal sequences generated according to the noise frequency f.sub.k.sub.2 in Step 3; Q.sub.3[n] and I.sub.3[n] are a set of standard orthogonal sequences generated according to the noise frequency f.sub.k.sub.3 in Step 3. In this embodiment, the orthogonal sequences Q.sub.3, I.sub.3, Q.sub.2, I.sub.2, Q.sub.1, I.sub.1 are generated by a coordinate rotation digital computer (CORDIC) algorithm, but the method for generation of the orthogonal sequences is not limited thereto. The combination of the CORDIC algorithm and the algorithm in this embodiment avoids the use of a memory during the generation of the orthogonal sequences, thereby saving storage space and saving time in the process of reading the internal storage. The following describes the combination of the CORDIC algorithm and the algorithm of this embodiment to generate the orthogonal sequences Q.sub.3, I.sub.3, Q.sub.2, I.sub.2, Q.sub.1, I.sub.1.

[0091] 5. Generating phase stepping

[00015]$\{\begin{array}{c}{\theta }_{f_{k_1}}=\frac{2\pi \left(N+4k_1\right)}{4N}\\ {\theta }_{f_{k_2}}=\frac{2\pi \left(N-4k_1\right)}{4N}\\ {\theta }_{f_{k_3}}=\frac{2\pi \left(N-2k_1\right)}{2N}\end{array}.$

[0092] where is a phase stepping for generating the orthogonal sequences Q.sub.1[n] and I.sub.1[n]; θ.sub.f.sub.k2 is a phase stepping for generating the orthogonal sequences Q.sub.2[n] and I.sub.2[n]; and is a phase stepping for generating the orthogonal sequences Q.sub.3[n] and I.sub.3[n].

[0093] 6. Generating CORDIC initial values

[00016]$\{\begin{array}{c}{x}_0^{k_i}=k=0.607263\\ y_0^{k_i}=0\\ {𝓏}_0^{k_i}=0\end{array},i\in \left[1,3\right]$

[0094] where the use of CORDIC algorithm to generate the orthogonal sequences Q.sub.1[n], I.sub.1[n], Q.sub.2[n], I.sub.2[n], Q.sub.3[n] and I.sub.3[n] requires initial values, which are x.sub.0.sup.k.sup.1, y.sub.0.sup.k.sup.1, z.sub.0.sup.k.sup.1, x.sub.0.sup.k.sup.2, y.sub.0.sup.k.sup.2, z.sub.0.sup.k.sup.2 and x.sub.0.sup.k.sup.3, y.sub.0.sup.k.sup.3, z.sub.0.sup.k.sup.3 respectively. The superscript k.sub.i is used here to distinguish the three different sets of initial values, and i ranges from 1 to 3.

[0095] 7. Performing iterative calculations

[00017]$\{\begin{array}{c}{S}_m^{k_i}=\{\begin{array}{c}-1,Z_m^{k_i}<0\\ +1,Z_m^{k_i}\ge 0\end{array}\\ x_{m+1}^{k_i}=x_m^{k_i}-S_m^{k_i}{2}^{-m}{y}_m^{k_i}\\ y_{m+1}^{k_i}=y_m^{k_i}+S_m^{k_i}{2}^{-m}{x}_m^{k_i}\\ {𝓏}_{m+1}^{k_i}={𝓏}_m^{k_i}-S_m^{k_i}\arctan \left(2^{-m}\right)\end{array}i\in \left[1,3\right],m\in \left[1,15\right]$

[0096] where iterative calculations are performed through the CORDIC algorithm, and a desired precision is achieved after 15 iterations. x.sub.m.sup.k.sup.i and y.sub.m.sup.k.sup.i are final iteration values, and s.sub.m.sup.k.sup.i and z.sub.m.sup.k.sup.i are intermediate variables of the iteration. The three sets of orthogonal sequences require three sets of iterations. The subscript i is used to distinguish the different orthogonal sequences, and i ranges from 1 to 3.

[0097] 8. Calculating the orthogonal sequences

[00018]$\{\begin{array}{c}{Q}_i\left[1\right]=x_{16}^{k_i}\\ I_i\left[1\right]=y_{16}^{k_i}\end{array},i\in \left[1,3\right].$

[0098] where and represent the three sets of orthogonal sequences, which are distinguished by the subscript i, for i∈[1,3]. and are calculation results obtained in the previous step.

[0099] 9. Updating the CORDIC initial values

[00019]$\{\begin{array}{c}{x}_0^{k_i}=k=0.607263\\ y_0^{k_i}=0\\ {𝓏}_0^{k_i}=n{\theta }_{f_{k_i}},n\in \left[2,N\right]\end{array},i\in \left[1,3\right].$

[0100] 10. Repeating Steps 4, 5 and 6

[00020]$\{\begin{array}{c}{Q}_i\left[n\right]=x_{16}^{k_i}\\ I_i\left[n\right]=y_{16}^{k_i}\end{array},n\in \left[2,N\right],i\in \left[1,3\right].$

[0101] 11. Calculating cross-correlation

[00021]$\{\begin{array}{c}{R}_{x{Q}_k}=\frac{1}{N_0}\underset{n=1}{\overset{N_0}{.Math.}}x\left[n\right]Q_k\left[n\right]\\ R_{x{I}_k}=\frac{1}{N_0}\underset{n=1}{\overset{N_0}{.Math.}}x\left[n\right]I_k\left[n\right]\end{array},k\in \left[1,2,3\right],N_0\ll N$

[0102] where N.sub.0 is a number of cross-correlation calculation points, and and are cross-correlation calculation results between the sampled data x[n] and Q.sub.k[n], I.sub.k[n].

[0103] 12. Obtaining phase and amplitude information of the noise spectrum

[00022]${\theta }_k=\{\begin{array}{c}\arctan .Math.\frac{R_{x{Q}_k}}{R_{x{I}_k}}.Math.,R_{x{Q}_k}>0,R_{x{I}_k}>0\\ -\arctan .Math.\frac{R_{x{Q}_k}}{R_{x{I}_k}}.Math.,R_{x{Q}_k}<0,R_{x{I}_k}>0\\ \arctan .Math.\frac{R_{x{Q}_k}}{R_{x{I}_k}}.Math.+\pi ,R_{x{Q}_k}<0,R_{x{I}_k}<0\\ \pi -\arctan .Math.\frac{R_{x{Q}_k}}{R_{x{I}_k}}.Math.,R_{x{Q}_k}>0,R_{x{I}_k}<0\end{array},k\in \left[1,2,3\right],$$A_k=2\sqrt{R_{x{Q}_k}^2+R_{x{I}_k}^2},k=\left[1,2,3\right]$

[0104] where θ.sub.k is obtained phase information, and A.sub.k is obtained amplitude information, for k∈[1,3].

[0105] 13. Reconstructing four-channel interleaved sampled mismatch error data e[n] according to the calculated amplitude and phase information.

[00023]$e\left[n\right]=A_1\cos \left(2\pi f_{k_1}\frac{n}{f_s}+{\theta }_1\right)+A_2\cos \left(2\pi f_{k_2}\frac{n}{f_s}+{\theta }_2\right)+A_3\cos \left(2\pi f_{k_3}\frac{n}{f_s}+{\theta }_3\right),$

[0106] where A.sub.1, A.sub.2 and A.sub.3 are the amplitude information A.sub.k in Step 11, for k∈[1, 2,3]; and θ.sub.1, and θ.sub.3 are the phase information in Step 11.

[0107] 14. Completing the calibration of the four-channel interleaved sampled data by subtracting the mismatch error e[n] from the acquired data x[n] and then acquiring calibrated data

{tilde over (x)}[n]=x[n]−e[n].

[0108] In order to obtain a more accurate amplitude demodulation value, the frequency of the input signal in the broad-band mode is f.sub.in<¼f.sub.s.

[0109] The amplitude demodulation module demodulates the amplitude information of the sampling signal by calculating an average value.

[0110] The advantages of the dynamic impedance imaging system in this embodiment are as follows. The dynamic impedance imaging system can capture the abnormal particle flowing in the dynamic impedance imaging sensor, measure the flow rate of the abnormal particle, and perform electrical impedance tomography imaging on the abnormal particle after obtaining the flow rate of the abnormal particle.

[0111] In particular, the dynamic impedance imaging sensor first determines whether there is an abnormal particle flowing through the tube, and sends out two hardware trigger signals P.sub.1 and P.sub.2 successively when there is an abnormal particle flowing through the sensor. The P.sub.1 and P.sub.2 are used as gate signals for the hardware system to obtain the flow rate v of the abnormal particle (usually a cell cluster). The gate signal P.sub.2 and the flow rate v are used as start and scan time control signals to start and control the EIT system.

[0112] The impedance detection and flow rate measurement module may detect an impedance change between the two measurement electrodes when the fluid passes through the dynamic impedance imaging sensor. It converts this change into a standard LVCMOS level output to measure the flow rate of the abnormal particle in the fluid and provide a start signal for the EIT instrument.

[0113] The dynamic impedance imaging system is based on a 16-channel EIT instrument, and has the impedance detection and flow rate measurement module in the leading position. These two systems cooperate to complete the capture of the abnormal particle in the fluid.

[0114] This embodiment proposes a calibration algorithm of a interleaved sampled mismatch error suitable for the dynamic impedance imaging system. The calibration algorithm can be embodied in two operating modes, broad-band and narrow-band, and the two different operating modes can be selected according to actual operating conditions so as to achieve a balance between performance and resources.

[0115] This embodiment combines the interleaved sampled technology and the EIT technology to satisfy the requirements for the SNR and sampled rate (bandwidth) of the EIT system in the biomedical field.

[0116] Each embodiment of the present specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts between the embodiments may refer to each other.

[0117] In this specification, several embodiments are used for illustration of the principles and implementations of the present disclosure. The description of the above embodiments is used to help understand the method of the present disclosure and the core idea thereof. In addition, those of ordinary skill in the art can make various modifications in terms of specific implementations and scope of application in accordance with the teachings of the present disclosure. In conclusion, the content of the present specification shall not be construed as a limitation to the present disclosure.