Pinned photodiode with a low dark current

Abstract

A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

Claims

1. A method comprising: manufacturing a pinned photodiode, the manufacturing including: forming a conversion region of a first conductivity type on a substrate of a second conductivity type, the conversion region being configured to convert photons into electric charges; forming a shallow semiconductor region of the second conductivity type on the conversion region; coating said shallow semiconductor region with a heavily-doped insulator layer that is doped with dopants of the second conductivity type, the shallow semiconductor region being positioned between the conversion region and the heavily-doped insulation layer; and providing a dopant diffusion from the heavily-doped insulator layer into the shallow semiconductor region, wherein: the shallow semiconductor region is formed on the conversion region prior to coating said shallow semiconductor region with the heavily-doped insulator layer; and providing the dopant diffusion includes forming a diffusion layer of the second conductivity type in an upper portion of the shallow semiconductor region, the diffusion layer having a doping level that is higher than a doping level of the shallow semiconductor region.

2. The method of claim 1, wherein the conversion region is of type N and the layer of a heavily-doped insulator is a boron-doped silicon oxide layer.

3. The method of claim 1, wherein providing the dopant diffusion includes diffusing dopants from the heavily-doped insulator layer into the shallow semiconductor region to a penetration depth smaller than 50 nm.

4. The method of claim 1, wherein forming the shallow semiconductor region includes coating the conversion region with the shallow semiconductor region with a maximum doping level in a range from 10.sup.17 to 10.sup.18 at./cm.sup.3 before coating the shallow semiconductor region with the heavily-doped insulator layer.

5. The method of claim 1, wherein providing the dopant diffusion includes annealing the heavily-doped insulator layer and forming a heavily-doped diffusion layer of the second conductivity type having a doping level that is greater than a doping level of the shallow semiconductor region.

6. The method of claim 2, wherein the boron-doped silicon oxide layer is doped with a boron concentration from 510.sup.21 to 210.sup.22 at./cm.sup.3.

7. The method of claim 3, wherein the penetration depth is smaller than 10 nm.

8. A pinned photodiode, comprising: a conversion region of a first conductivity type formed on a substrate of a second conductivity type, the conversion region being configured to convert photons into electric charges; a diffusion layer of the second conductivity type formed on the conversion region; a shallow semiconductor region of the second conductivity type positioned between the diffusion layer and the conversion region; and a heavily-doped insulator layer that coats the diffusion layer, the heavily-doped insulator layer being of the second conductivity type.

9. The pinned photodiode of claim 8, wherein the heavily-doped insulator layer is boron-doped silicon oxide at a boron concentration from 510.sup.21 to 210.sup.22 at./cm.sup.3.

10. The pinned photodiode of claim 8, wherein the diffusion layer has a depth of less than 50 nm.

11. The pinned photodiode of claim 8, wherein the shallow semiconductor region has a maximum doping on the order 10.sup.18 at./cm.sup.3 and the diffusion layer has a maximum doping on the order 10.sup.20 at./cm.sup.3.

12. The pinned photodiode of claim 8, wherein said diffusion layer has a doping level that is higher than a doping level of the shallow semiconductor region.

13. A device, comprising: a transfer transistor; and a pinned photodiode, the pinned photodiode including: a conversion region of a first conductivity type formed on a substrate of a second conductivity type, the conversion region being configured to convert photons into electric charges; a diffusion layer of the second conductivity type formed on the conversion region; a shallow semiconductor region of the second conductivity type positioned between the diffusion layer and the conversion region; and a heavily-doped insulator layer that coats the diffusion layer, the heavily-doped insulator layer being of the second conductivity type.

14. The device of claim 13, wherein the heavily-doped insulator layer is boron-doped silicon oxide at a boron concentration from 510.sup.21 to 210.sup.22 at./cm.sup.3.

15. The device of claim 13, wherein the diffusion layer has a depth of less than 10 nm.

16. The device of claim 13, wherein the transfer transistor includes an insulated gate, a drain, and a source, the source being at least a portion of the conversion region.

17. The device of claim 13, wherein said diffusion layer has a doping level that is higher than a doping level of the shallow semiconductor region.

18. The device of claim 15, wherein the shallow semiconductor region has a maximum doping on the order 10.sup.18 at./cm.sup.3 and the diffusion layer has a maximum doping on the order 10.sup.20 at./cm.sup.3.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 is a simplified cross-section view corresponding to FIG. 2 of U.S. Pat. No. 6,677,656;

(2) FIG. 2 shows concentration variations according to depth for a structure of the type in FIG. 1;

(3) FIG. 3 is a cross-section view showing a second embodiment of a pinned photodiode having a low dark current; and

(4) FIG. 4 shows concentration variations according to depth for a structure of the type in FIG. 3.

(5) As usual in the representation of integrated circuits, the various cross-section views are not to scale. Further, in the following description, unless otherwise indicated, terms approximately, in the order of, etc., mean to within 10%, and terms referring to directions, such as upper, lower, lateral, horizontal, vertical, etc., apply to devices arranged as illustrated in the corresponding cross-section views, it being understood that, in practice, the devices may have different directions.

DETAILED DESCRIPTION

(6) FIG. 3 is a cross-section view showing an embodiment of pinned photodiode having a low dark current. This photodiode comprises, on a heavily-doped P-type substrate 11, a layer 12 which is also P-type doped, preferably formed by epitaxy, inside of which is formed an N-type doped well 13 having a shallow P-type region 14, that is, a region of a depth smaller than 100 nm, preferably smaller than 75 nm, formed therein by implantation. As previously, a transfer MOS transistor 15 is formed and includes region 13, which forms its source, a heavily-doped N-type region 16, which forms its drain, and a gate 18. The pixel particularly comprising photodiode 12, 13, 14, and the transistor is delimited by a deep trench 20 preferably extending all the way to substrate 11. This deep trench is bordered with a heavily-doped P-type region 21, preferably formed by diffusion from a heavily-doped material contained in the insulator filling trench 20.

(7) The structure is coated with a layer 22 of a heavily-doped insulator. This insulator will for example be, in the case of the previously-indicated conductivity types, a layer of borosilicate glass, or in other words of heavily boron-doped silicon oxide. Thus, after the anneals resulting from subsequent manufacturing steps, the boron contained in layer 22 has a very shallow diffusion at a very high concentration in the underlying semiconductor. A heavily-doped P-type layer 24 thus forms at the surface of region 14. It should be noted that the diffusion does not affect the N.sup.+ regions, which have a much stronger doping.

(8) Preferably, the doping levels and the anneal times of the various layers are selected to obtain, perpendicularly to layers 24, 14, 13, and 12, a concentration profile of the type shown in FIG. 4.

(9) It can thus be observed that if layer 14 is moderately doped (for example, at a maximum doping on the order of 10.sup.18 at./cm.sup.3), due to the presence of layer 24, a shallow layer having a maximum doping at the level of the upper oxide on the order of 10.sup.20 at./cm.sup.3. As a result, the dark current generation becomes negligible at the interface between a very heavily-doped region and an upper insulator. Indeed, the generation of electron-hole pairs at the interface between an insulating layer and a semiconductor layer decreases when the semiconductor doping (for example, silicon) increases. As an example, a measurement at 60 C. shows that the dark current is 100 pA/cm.sup.2 for a device of the type in FIG. 1 and is approximately half thereof for a device of the type in FIG. 3.

(10) In a manufacturing mode, after having formed lateral insulations 20 and 21 and then MOS device 15 comprising insulated gate 18 and N-type source area 13, a silicon oxide layer 22 having a thickness approximately in the range from 5 to 20 nm (for example, 10 nm) doped with boron at a concentration in the range from 510.sup.21 to 210.sup.22 at./cm.sup.3, for example, 110.sup.22 at./cm.sup.3, is deposited.

(11) The embodiment described herein is likely to have many variations. For example, all the conductivity types of the photodiode may be inverted. In this case, the heavily boron-doped insulator layer will be replaced with an insulator layer heavily doped with arsenic or phosphorus (for example, PSG).

(12) The specific form of the shown pinned photodiode is an example only. Other forms of photodiodes may be used as well as other transfer transistor layouts. Further, in each pixel comprising a photodiode and a transfer transistor, other elements will be preferably integrated, for example, a reset transistor.

(13) In FIG. 3, the limit of P-type layer 14 has been indicated with dotted lines. This illustrates the fact that this layer is optional. It is possible to only provide the very thin layer of high doping level resulting from the diffusion of the dopant contained in the insulator covering the structure. On the other hand, doping insulator 22 has been shown as covering the entire structure. In specific embodiments, a previous etching of this insulator may be provided so that it only covers useful regions of the photodiode.

(14) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present disclosure. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.

(15) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.