Algorithm for passive power factor compensation method with differential capacitor change and reduced line transient noise

Abstract

A computer-implementable control algorithm that measures: 1) the reactive power; 2) the power factor; 3) the voltage; and 4) the line frequency. The algorithm calculates the differential compensation capacitance required that is either positive (capacitance to be added), or negative (capacitance to be removed). The new compensation capacitance is calculated from the sum or difference of the differential compensation capacitance and the current compensation capacitance. The algorithm compares the capacitor switching bit pattern for the current compensation capacitance and the capacitor switching bit pattern for the new compensation capacitance, and selects a capacitor switching bit map accordingly. The capacitor switch combination for the new compensation capacitance is switched in incrementally according to the capacitor switching bit map. To reach the selected capacitor switch combination, only one switch is switched at a time to minimize the line transient noise. This part of the algorithm continues to run until the PF is corrected, with the capacitor switches being switched on/off each delayed by a millisecond interval to minimize line transient noise.

Claims

1. A method for conducting passive power factor compensation based on differential capacitor change, comprising: a. acquiring real time electrical power circuit measurements comprising: power factor, line voltage, line frequency, reactive power, and sign of reactive power; b. determining a compensation capacitance required; c. determining the states of each of capacitor switches for engaging or disengaging their corresponding capacitors for achieving a total capacitance closest to the compensation capacitance required; d. forming a new capacitor combination according the states of each of the capacitor switches determined for the compensation capacitance required; e. first disengaging currently engaged capacitors in current capacitor combination one by one in ascending order starting with the capacitor with lowest capacitance and ending with the capacitor with highest capacitance, and after all capacitors are disengaged, engaging capacitors in the new capacitor combination one by one in ascending order starting with the capacitor with lowest capacitance and ending with the capacitor with highest capacitance to minimize line transient noise; and repeating above steps a-e every pre-determined time interval.

2. The method of claim 1, wherein the determination of the compensation capacitance required comprises: calculating $\mathrm{C\_pfc}=\frac{\mathrm{P\_reactive}}{2.Math..Math.\mathrm{fl}{\mathrm{Vac}}^2},$ where C_pfc is a differential compensation capacitance, P_reactive is the reactive power measured, Vac is the line voltage measured, and fl is the line frequency measured; and if an absolute value of the differential compensation capacitance is larger than a predetermined limit value, then adding, if the power factor measured is positive, or subtracting, if the power factor measured is negative, C_pfc to or from existing capacitance value, resulting in the compensation capacitance required.

3. The method of claim 2, wherein the predetermined limit value being equal or larger than of minimum capacitance step.

4. The method of claim 1, wherein positions and the states of the capacitor switches are represented in binary form; wherein the capacitor switches being positioned in descending order according to their corresponding the capacitor capacitance values with the capacitor switch corresponding to the capacitor with highest capacitance being positioned at most significant bit (MSB) and the capacitor switch corresponding to the capacitor with lowest capacitance being positioned at least significant bit (LSB).

5. The method of claim 1, wherein each of engaging and disengaging of each capacitor being separated by a delay time interval.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention are described in more detail hereinafter with reference to the drawings, in which

(2) FIG. 1 shows a circuit diagram illustrating an exemplary electrical power circuitry incorporated with a computer-implementable control algorithm for passive power factor compensation based on differential capacitor change in accordance to an embodiment of the presently claimed invention;

(3) FIG. 2A shows a circuit diagram illustrating another exemplary electrical power circuitry incorporated with a computer-implementable control algorithm for passive power factor compensation based on differential capacitor change in accordance to another embodiment of the presently claimed invention;

(4) FIG. 2B depicts a flow chart illustrating the capacitor switching operation for the electrical power circuitry shown in FIG. 2A;

(5) FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D depict the flow charts illustrating the process steps of a computer-implementable control algorithm for passive power factor compensation based on differential capacitor change in accordance to yet another embodiment of the presently claimed invention;

(6) FIG. 3E depicts a table illustrating the bit pattern transition corresponding to an exemplary engagement of compensation capacitors;

(7) FIG. 4 depicts a table illustrating an exemplary embodiment of the data structure for the compensation capacitance values and parameters stored in external non-volatile storage;

(8) FIG. 5A shows a table listing the compensation capacitance values and parameters, and results of an exemplary implementation of the presently claimed invention; and FIG. 5B shows a chart of capacitor select logic state vs. reactive power.

DETAILED DESCRIPTION

(9) In the following description, methods and systems incorporating a computer-implementable control algorithm for passive power factor compensation based on differential capacitor change and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

(10) FIG. 1 shows a circuit diagram illustrating an exemplary electrical power circuitry incorporated with a computer-implementable control algorithm for passive power factor compensation based on differential capacitor change in accordance to an embodiment of the presently claimed invention. This electrical power circuitry is for a three-phase system; however, the similar configuration can be applied to other two-phase systems. In this electrical power circuitry, the three capacitors C.sub.1 (106), C.sub.2 (105), and C.sub.3 (104) can be switched in or out individually by their corresponding switches SW.sub.bit0 (103), SW.sub.bit1 (102), and SW.sub.bit2 (101) according to the determined compensation capacitance required for power quality compensation. In addition, the measurement module (107) collects the power line quality data, including voltage, current, power factor, real power, and reactive power.

(11) The positions and states of the switches can be represented in binary form in the control algorithm. One exemplary embodiment is as follows:

(12) TABLE-US-00001 TABLE 1 Bit Values and Capacitance Switch.sub.bit 2 (MSB) 1 0 (LSB) Capacitance 50 uF 25 uF 12 uF

Table 1

(13) To minimize the line transient noise, to reach the selected capacitor switch combination, only one switch is switched at a time. Referring to Table 2 below. For example, if the compensation capacitance required is to be increased to 62 uF from the current 25 uF, the changes in the states of the three switches are to go through State 3, State 4, then finally State 5 in sequential order.

(14) TABLE-US-00002 TABLE 2 Switch.sub.bit State bit2 bit1 bit0 Total Capacitance (uF) 0 0 0 0 0 1 0 0 1 12 2 0 1 0 25 3 0 1 1 37 4 1 0 0 50 5 1 0 1 62 6 1 1 0 75 7 1 1 1 87

Table 2

(15) The number of capacitors and their values are chosen as an example for the purpose of illustrating the principle of the presently claimed invention. Any number of capacitors and capacitance values can be adopted for the implementation of the presently claimed invention.

(16) FIG. 2A shows a circuit diagram illustrating another exemplary electrical power circuitry incorporated with the computer-implementable control algorithm. In this electrical power circuitry, the capacitor switches are implemented with inrush relay. FIG. 2B depicts a flow chart illustrating the capacitor switching operation for this implementation. For example, to switch in the capacitor C.sub.3, switch SW.sub.bit2a (202) is first switched on, wait for a delay period (e.g. 30 millisecond), then switch on SW.sub.bit2 (201); to switch out the capacitor C.sub.3, switch SW.sub.bit2 (201) is first switched off, wait for a delay period (e.g. 30 millisecond), then switch of SW.sub.bit2a (202).

(17) To determine the compensation capacitance required, a computation based on the following mathematical calculations is made:

(18) Given:

(19) Vac AC power line voltage

(20) fl Line frequency

(21) PF Power factor

(22) P_real Real Power

(23) P_apparent Apparent Power

(24) P_reactive Reactive Power

(25) Phase angle

(26) I_reactive Reactive current

(27) Z_cap Capacitive impedance

(28) C_pfc PFC capacitance

(29) Relationships
P_real=P_apparent.Math.PF=P_apparent.Math.cos()
cos().sup.2+sin().sup.2=1PF.sup.2+sin().sup.2=1
P_reactive=P_apparent.Math.sin()=P_apparent.Math.{square root over (1PF.sup.2)}

(30) $\mathrm{P\_reactive}=\mathrm{Vac}.Math.\mathrm{I\_reactive}=\mathrm{Vac}.Math.\frac{\mathrm{Vac}}{\mathrm{Z\_cap}}=\mathrm{Vac}.Math.\frac{\mathrm{Vac}}{\frac{1}{2.Math..Math.\mathrm{fl}.Math.\mathrm{C\_pfc}}}={\mathrm{Vac}}^2.Math.2.Math..Math.\mathrm{fl}.Math.\mathrm{C\_pfc}$
Convenient mean of determining compensation capacitance

(31) $\mathrm{C\_pfc}=\frac{\mathrm{P\_reactive}}{2.Math..Math.\mathrm{fl}{\mathrm{Vac}}^2}$

(32) In accordance to various embodiments of the presently claimed invention, the computer-implementable control algorithm relies on a measurement module for measuring: line voltage: Vac, line frequency: fl, reactive power: P_reactive, and sign of reactive power: +ve for lagging and ve for leading (expressed as + or power factor).

(33) FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D depict flow chart illustrating the process steps of the computer-implementable control algorithm to automatically adjust the compensation capacitance. The flow chart in FIG. 3A illustrates the overall process, which comprises the following steps:

(34) a. initializing existing capacitance value C_pfc to zero;

(35) b. acquiring the real time measurements, the measurements comprising: power factor; line voltage; line frequency, which can be measured data or default constant; reactive power; sign of reactive power, which can be determined from part of power factor measurement;

(36) c. calculating the compensation capacitance required, as shown in details in FIG. 3B, based on the equation:

(37) $\mathrm{C\_pfc}=\frac{\mathrm{P\_reactive}}{2.Math..Math.\mathrm{fl}{\mathrm{Vac}}^2},$
the calculation comprising: if the absolute value of C_pfc is larger than a predetermined limit value, preferably equal or larger than of minimum capacitance step (this is to provide a hysterisis and prevent hunting), then add (if power factor is positive) or subtract (if power factor is negative) C_pfc to (add) or from (subtract) existing capacitance value;

(38) d. decode the capacitor combination (or positions and states of switches in binary form) for the compensation capacitance required as detailed in the flow chart shown in FIG. 3C;

(39) e. engage the newly decoded capacitor combination starting from the currently engaged capacitor combination as detailed in the flow chart shown in FIG. 3D; and

(40) f. repeating steps a to e every pre-determined time interval, typically fifteen minutes.

(41) In accordance to one embodiment, the engagement of the suitable compensation capacitors based on new existing capacitance value comprises a series of steps as depicted in the flow chart shown in FIG. 3D. An example of such engagement with its corresponding bit pattern transition from 101 to 110 is illustrated in the table shown in FIG. 3E.

(42) In accordance to various embodiments of the presently claimed invention, the computer-implementable control algorithm to automatically adjust the compensation capacitance is primarily implemented using a microcontroller (MCU). In this implementation, in the step of engaging of suitable compensation capacitance comprises, compensation capacitance values are loaded into the MCU from external sources to provide flexibility in adapting the algorithm to different power levels. For example, external non-volatile storage, such as EEprom, Flash, etc. is used to store the compensation capacitance values and parameters and read into MCU thru I/O interface. The compensation capacitance values and parameters are loaded into the non-volatile storage via an interface with a pre-defined protocol such as the UART, I2C, and USB. Additional firmware routine can be employed to verify the external non-volatile storage validity and halt the execution in case of corrupt data found. An exemplary embodiment of the data structure for the compensation capacitance values and parameters stored in external non-volatile storage is illustrated in the table shown in FIG. 4.

(43) In accordance to various embodiment of the presently claimed invention, a logging of time stamped data of power line quality information is provided. The data comprises: MCU log power line information to non-volatile memory; time; voltage; line frequency, real power; reactive power; capacitor engaged or switch state; power factor if reactive power does not contain sign; ambient temperature; and checksum. The data structure should be able to indicate the number of phase(s) of the electrical system.

(44) The embodiments disclosed herein may be implemented using general purpose or specialized computing devices, mobile communication devices, computer processors, or electronic circuitries including but not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), and other programmable logic devices configured or programmed according to the teachings of the present disclosure. Computer instructions or software codes running in the general purpose or specialized computing devices, mobile communication devices, computer processors, or programmable logic devices can readily be prepared by practitioners skilled in the software or electronic art based on the teachings of the present disclosure.

(45) In some embodiments, the present invention includes computer storage media having computer instructions or software codes stored therein which can be used to program computers or microprocessors to perform any of the processes of the present invention. The storage media can include, but are not limited to, floppy disks, optical discs, Blu-ray Disc, DVD, CD-ROMs, and magneto-optical disks, ROMs, RAMs, flash memory devices, or any type of media or devices suitable for storing instructions, codes, and/or data.

(46) The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.

(47) The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalence.