Improving linearity in semiconductor devices

Abstract

A field effect transistor that has a source, a drain, a gate and a semiconductor region. The semiconductor region has a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate. The channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.

Claims

1. A field effect transistor, comprising: a source; a drain; a gate; and a semiconductor region between the source and the drain, the semiconductor region having a source access region between the gate and the source, a drain access region between the gate and the drain, and a channel region under the gate that includes a two-dimensional electron gas extending across an entire length of the gate, wherein the channel region under the gate has a maximum current-carrying capability that is lower than a maximum current-carrying capability of the source access region.

2. The field effect transistor of claim 1, wherein the channel region under the gate has a smaller width than that of the source access region.

3. The field effect transistor of claim 1, wherein the channel region under the gate has a smaller current carrying cross-sectional area than that of the source access region.

4. The field effect transistor of claim 1, wherein the field effect transistor comprises a plurality of channel regions under the gate.

5. The field effect transistor of claim 4, wherein the plurality of channel regions under the gate includes nanowires of semiconductor material.

6. The field effect transistor of claim 5, wherein the nanowires do not extend beyond an area covered by the gate.

7. The field effect transistor of claim 1, further comprising at least one region of limited conductivity under the gate, between the source access region and the drain access region, the at least one region of limited conductivity having a lower conductivity that that of the channel region under the gate.

8. The field effect transistor of claim 7, wherein the at least one region of limited conductivity comprises at least one insulating region.

9. The field effect transistor of claim 1, wherein the semiconductor region comprises a nitride semiconductor material.

10. The field effect transistor of claim 9, wherein the nitride semiconductor material comprises a gallium nitride semiconductor material.

11. The field effect transistor of claim 1, wherein the source access region comprises a plurality of channels at different depths and the channel region under the gate has a smaller quantity of channels than a quantity of the plurality of channels.

12. The field effect transistor of claim 1, wherein the channel region under the gate has an amount of current-carrying semiconductor material that is lower than an amount of current-carrying semiconductor material of the source access region.

13. The field effect transistor of claim 1, wherein a source-drain current of the field effect transistor is not limited by the current-carrying capability of the source access region or the drain access region.

14. The field effect transistor of claim 1, wherein the channel region under the gate has a lower conductivity than that of the source access region.

15. The field effect transistor of claim 1, further comprising a doped region over the source access region and the drain access region and not over the channel region under the gate.

16. The field effect transistor of claim 1, wherein a semiconductor material under the gate is different from a material of the source access region or drain access region.

17. A field effect transistor, comprising: a first electrode; a second electrode; a gate having a gate length; a first channel region covered by the gate and extending across the gate length; and a second channel region not covered by the gate, positioned between the first electrode and the gate, wherein the first channel region has a first cross-section perpendicular to a line between the first electrode and the second electrode, wherein the second channel region has a second cross-section perpendicular to the line between the first electrode and the second electrode, wherein an area of the first cross-section of the first channel region is smaller than an area of the second cross-section of the second channel region, and wherein the second channel region is wider than the first channel region in a width direction perpendicular to the line between the first electrode and the second electrode.

18. The field effect transistor of claim 17, wherein the first channel region comprises a nitride semiconductor material.

19. The field effect transistor of claim 18, wherein the nitride semiconductor material comprises a gallium nitride semiconductor material.

20. The field effect transistor of claim 17, wherein the first channel region comprises at least one nanowire.

21. The field effect transistor of claim 20, wherein the first channel region comprises a plurality of nanowires.

22. The field effect transistor of claim 20, wherein the at least one nanowire comprises a first nanowire having a fin-like shape.

23. The field effect transistor of claim 17, further comprising at least one insulating region under the gate.

24. The field effect transistor of claim 23, wherein the at least one insulating region comprises a region of damaged semiconductor material.

25. The field effect transistor of claim 17, wherein the first channel region includes a two-dimensional electron gas extending across the gate length.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like reference character. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily drawn to scale, with emphasis instead being placed on illustrating various aspects of the techniques described herein.

(2) FIGS. 1A, 1B, and 1C show a semiconductor device having a channel with a uniform width.

(3) FIG. 2 shows the relationship between current and gate-source voltage for an ideal transistor and a transistor with non-linear behavior.

(4) FIG. 3 shows the relationship between transconductance and gate-source voltage for an ideal transistor and a transistor with non-linear behavior.

(5) FIG. 4 shows the relationship between electron velocity and electric field in a field effect transistor.

(6) FIGS. 5A, 5B, 5C, 5D, 5E and 5F show a semiconductor device having a channel with a smaller width for a region under the gate than the rest of the channel.

(7) FIGS. 6A, 6B, 6C, and 6D show a semiconductor device having two channel regions under the gate with a total width smaller than the rest of the channel.

(8) FIGS. 7A, 7B, and 7C show a semiconductor device with multiple channel regions under the gate that have a total width smaller than the rest of the channel.

(9) FIGS. 8A, 8B, and 8C show a semiconductor device with multiple channel regions under the gate separated by regions of limited conductivity.

(10) FIG. 8D shows an embodiment of a field effect transistor with multiple channels c1, c2 at different depths in the source access region.

(11) FIG. 9A-H show example steps of a fabrication process for forming multiple channel regions underneath the gate.

(12) FIG. 10 is an SEM image after gate metallization in a prototype of a semiconductor device with nanowires under the gate.

(13) FIGS. 11A and 11B are plots of the current and transconductance characteristics vs. V.sub.gs and V.sub.ds, respectively, for a conventional planar semiconductor device and a prototype of a nanowire channel device.

(14) FIG. 12 is a plot of the cutoff frequency versus V.sub.gs for examples of a conventional planar channel device and a nanowire channel device.

DETAILED DESCRIPTION

(15) For the last two decades, the performance of GaN-based transistors has been improved significantly through improved material quality and new process technologies. However, the performance of state-of-art GaN-based transistors remains below theoretical expectations based on GaN material properties. One problem, particularly for large-signal RF operation, is the non-linear behavior of short-channel GaN transistors. In conventional GaN devices, the extrinsic transconductance (g.sub.m) drops quickly with increasing drain current after the extrinsic transconductance reaches a maximum point. This problem becomes more serious as the gate length scales down. The g.sub.m roll-off at high drain current not only deteriorates the linearity in large-signal operation, but also limits the maximum operating frequency. In previous research, it has been shown that a non-constant access resistance (two-dimensional electron gas (2-DEG) resistance) is the main cause of this behavior because it increases rapidly with an increase in current. Use of a highly-doped source/drain contact and a self-aligned gate structure can reduce this problem, but it results in a serious degradation of the breakdown voltage.

(16) In a field effect transistor, the current that flows through the transistor is modulated by the voltage applied to the gate. Increasing the range of gate voltages for which a semiconductor device operates linearly can allow operating at higher voltages with reduced distortion, and may enable large-signal operation.

(17) FIG. 1A shows a cross-section of a conventional field effect transistor 1 having a source 2, a gate 3, a drain 4 and a semiconductor region 5. Depending on the voltage applied to the gate 3 (e.g., a gate-source voltage V.sub.gs), a channel is formed in the semiconductor region 5 and current flows through a channel between the source 2 and the drain 4. The current that flows between the source 2 and the drain 4 is termed the source-drain current I.sub.sd.

(18) A plan view of the field effect transistor 1 along the line A-A is shown in FIG. 1B. A cross-sectional view of the field effect transistor 1 along the line B-B is shown in FIG. 1C. FIG. 1B shows portions of the semiconductor region 5 that correspond to the region under the source 5a, source access region 5b, region under the gate 5c, drain access region 5d, and region under the drain 5e, which have the same widths, W.sub.5. In field effect transistor 1, the channel has the same width, W.sub.5, throughout the length of the transistor between the source 2 and the drain 4. As shown in FIG. 1B, each of regions 5a-5e has the same width W.sub.5.

(19) In an ideal field effect transistor, the relationship between the gate-source voltage V.sub.gs and source-drain current I.sub.sd is linear above a certain voltage, as shown by curve 7 in FIG. 2. However, as discussed above, conventional short-channel nitride semiconductor transistors exhibit non-linear behavior above a certain gate-source voltage (V.sub.gs). The behavior of a conventional short-channel nitride semiconductor transistor is shown by curve 8 in FIG. 2. Curve 8 shows that the conventional short-channel nitride semiconductor transistor operates linearly at low V.sub.gs, but at a high enough V.sub.gs the transistor operates non-linearly, and may reach an upper limit where the source-drain current I.sub.sd no longer increases with increasing gate-source voltage V.sub.gs. When a conventional short-channel nitride semiconductor transistor is operated in a range of gate-source voltages that results in non-linear operation of the transistor, the output signal may be distorted, which may be undesirable in many applications. To avoid distortion, the conventional short-channel nitride semiconductor transistor may be operated in the linear range of operation. However, doing so limits the range of gate-source voltages over which the transistor operates.

(20) Such non-linear behavior above a certain gate-source voltage V.sub.gs is also apparent when examining the transconductance of the transistor. The transconductance, g.sub.m, is the slope of the current as a function of voltage. When the transconductance is constant the transistor behaves linearly. The transconductance of an ideal transistor, shown by curve 9 in FIG. 3, is constant beyond a certain source-gate voltage V.sub.gs. The transconductance of a conventional short-channel nitride semiconductor transistor, shown by curve 10, is constant over a range of voltage values, but for gate-source voltages V.sub.gs higher than a cutoff voltage V.sub.cutoff, the transconductance decreases with increasing gate-source voltages V.sub.gs. Such nonlinear behavior for conventional short-channel nitride semiconductor transistors is caused by current limitations in various regions of the channel.

(21) Current depends on the number of electrons, n, and the velocity of the electrons, v.sub.c, based on the equation I=qnv.sub.c, where q is the charge of an electron. Varying the gate-source voltage V.sub.gs changes the number of electrons, n, within the region under the gate 5c. When the gate-source voltage V.sub.gs increases, the number of electrons within region 5c also increases.

(22) An example of the relationship between electron velocity and electric field strength is shown in FIG. 4. The electron velocity increases with increasing electric field strength until a saturation velocity (v.sub.sat) is reached. Different semiconductor materials have different saturation velocities. In GaN, for example, electrons reach a saturation velocity of 1.510.sup.7 cm/s at an electric field of 100 kV.Math.cm. Above a certain gate-source voltage, the electric field under the gate is high enough that the electrons under the gate should travel at the saturation velocity and the current within region 5c should be I=qnv.sub.sat. However, it has been appreciated that the current in region 5c cannot reach I=qnv.sub.sat because it is limited by the number of electrons provided by the source access region 5b.

(23) The current in the source access region 5b and the drain access region 5d is also governed by the equation I=qnv. The electric field in the source access region 5b is lower than that of region 5c, as the source access region 5b is not covered by the gate. Due to the lower electric field, the electrons in the source access region 5b may not reach the saturation velocity v.sub.sat. As a result, the maximum current that can flow through regions 5b is lower than the maximum current that can flow through region 5c.

(24) Since regions 5b, 5c, and 5d are in series, the current through these regions is equal (this concept is termed current continuity). The source-drain current of the transistor is thus limited by the maximum current that can flow through the source access region 5b. At low gate-source voltages, the number of electrons under the gate may be at a value where the source access region 5b and the drain access region 5d do not limit the current the current in the channel. However, for gate-source voltages above the cutoff voltage V.sub.cutoff, the source-drain current becomes limited by the limited current-carrying capacity of the source access region 5b, which produces the non-linear behavior shown in FIGS. 2 and 3.

(25) According to the innovative techniques described herein, an improvement in the linearity of field effect transistors can be achieved by limiting the amount of current that can flow under the gate to prevent the source-drain current I.sub.sd of the transistor from being limited by the current-carrying capability of the source access region or the drain access region. Any of a variety of techniques may be used to limit the current that can flow in the region under the gate. In some embodiments, the amount of current-carrying semiconductor material (e.g., of the channel) under the gate may be reduced so that the source-drain current I.sub.sd is limited by the amount of current-carrying semiconductor material under the gate, rather than being limited by the current-carrying capability of the source access region or the drain access region.

(26) FIGS. 5A-5F show a field effect transistor 11 having a limited amount of current-carrying semiconductor material under the gate, according to some embodiments. FIG. 5A shows a cross-sectional view of the field effect transistor 11. Field effect transistor 11 has a source 12, a gate 13, a drain 14 and a semiconductor region 15. FIG. 5B shows a plan view of the field effect transistor 11 along the line C-C of FIG. 5A. As shown in FIG. 5B, the semiconductor region 15 includes the region under the source 15a, source access region 15b, region under the gate 15c, drain access region 15d, and region under the drain 15e.

(27) As shown in FIG. 5B, the region 15c under the gate has a smaller width, W.sub.15c, than the width, W.sub.15b of the source access region 15b and the drain access region 15d. The channel thus has a smaller width in region 15c under the gate than in source access region 15b and drain access region 15d, and thus the cross-sectional area of the channel in region 15c under the gate is less than in source access region 15b and drain access region 15d. In some embodiments, the cross-sectional area of the channel in region 15c is small enough such that the source-drain current I.sub.sd in the field effect transistor 11 is limited by the cross-sectional area of the channel in region 15c and not limited by the current-carrying capability of the source access region 15b or the drain access region 15d. In some embodiments, field effect transistor 11 behaves linearly over a broader range of voltages (e.g., at higher gate-source voltages) than field effect transistor 1.

(28) A cross-sectional view of the field effect transistor 11 along line D-D, according to some embodiments, is shown in FIG. 5C. As shown in FIG. 5C, a portion of the gate 13 may be formed over the region 15c and portions of the gate 13 may be formed on the sides of region 15c. Such a gate configuration may be termed a wrap-around gate configuration. As shown in FIG. 5C, the channel 6 has a smaller width W.sub.15c than the width of the source access region 15b and the drain access region 15d. FIG. 5E shows a perspective cutaway view of an embodiment according to FIG. 5C in which field effect transistor 11 is a HEMT that includes an InAlN/AlN barrier layer formed on a GaN semiconductor layer, thereby forming a two-dimensional electron gas as the channel (dashed line).

(29) A cross-sectional view of the field effect transistor 11 along line D-D having a different gate structure, according to some embodiments, is shown in FIG. 5D. As shown in FIG. 5D, the gate 13 may be formed over the region 15c. Such a gate configuration may be termed a planar gate configuration. In some embodiments, one or more regions of limited conductivity 16 may be formed on the sides of region 15c. Regions of limited conductivity 16 may include a material having a lower conductivity than the semiconductor material of region 15c and/or the semiconductor material of source access region 15b and/or drain access region 15d. In some embodiments, regions of limited conductivity 16 may be formed of electrically insulating material.

(30) Regions of limited conductivity 16 may be formed in any suitable way. In some embodiments, a portion of the semiconductor material in region 15c may be removed (e.g., etched), and regions 16 may be formed in the region where the semiconductor material was removed. As another example, insulating material may be formed without removing semiconductor material. For example, regions 16 may be formed by damaging semiconductor material of region 15 using ion implantation, or any other suitable process, to degrade the conductivity of the semiconductor material in region 16. Such a technique may lower the fringing capacitance from the sidewall of the channel region.

(31) Although region 15c may be aligned with the edge of the gate 13, in some embodiments region 15c is not aligned with the edge of the gate 13. In particular, region 15c, having a smaller width than regions 15b and 15d, need not extend the entire length of the gate, as a region 15c of smaller length is sufficient to limit the current-carrying capability of the region under the gate. FIG. 5F shows an embodiment in which current-carrying region 15c of reduced width only extends for a portion of the length of the gate 13 (shown in dashed lines). Region 15c may not extend beyond the edge of the gate 13 into regions 15b or 15d to prevent limiting the current that can flow in regions 15b and 15d, which may introduce non-linearity.

(32) The techniques described herein may improve the linearity of short-channel transistors, according to some embodiments. Such transistors may have a gate length Lg of less than 550 nm, less than 400 nm, less than 300 nm, less than 250 nm, less than 175 nm, or less than 100 nm, in some embodiments. FIG. 5A illustrates the gate length L.sub.g, which is the length of the gate along a dimension extending between the source and the drain. In some embodiments, the gate-drain distance and the gate-source distance may be greater than zero, such that the transistor includes a drain access region and/or a source access region. In some embodiments, the source access region and/or the drain access region may have a length L.sub.15b, L.sub.15d, respectively, of at least 50 nm.

(33) FIGS. 5A-5D and 5F show an embodiment in which a single current-carrying semiconductor region 15c is formed under the gate 13, thereby forming a single channel. In some embodiments, a plurality of current-carrying semiconductor regions may be formed under the gate 13, which may produce a plurality of channels, and which may improve linearity. The plurality of channels under the gate may be parallel to one another, and formed at the same depth from the surface of the substrate. FIGS. 6A-6D show an embodiment of a field effect transistor 21 in which two current-carrying semiconductor regions 15c1 and 15c2 are formed under the gate 13. FIG. 6A shows a cross sectional view and FIG. 6B shows a plan view of the field effect transistor 21 along the line E-E. In the illustrated embodiment, each of the current-carrying semiconductor regions 15c1 and 15c2 under the gate 13 has a width W.sub.wire. However, the techniques described herein are not limited to such regions having the same width, as semiconductor regions 15c1 and 15c2 may have different widths. In the illustrated embodiment, the total effective width W.sub.eff of the channel under the gate 13 is W.sub.eff=2 W.sub.wire. W.sub.eff is less than the width of the source access region 15b and the drain access region 15d.

(34) A cross-sectional view of field effect transistor 21 along line F-F, according to an embodiment with a wrap around gate, is shown in FIG. 6C. A cross-sectional view of field effect transistor 21 along line F-F, according to an embodiment with a planar gate configuration and regions of limited conductivity 16 is shown in FIG. 6D.

(35) FIGS. 7A-7D show an embodiment of a field effect transistor 31 in which more than two current-carrying regions 15c are formed under the gate 13. FIG. 7A shows a cross sectional view and FIG. 7B shows a plan view of the field effect transistor 31 along the line G-G.

(36) Increasing the number of current-carrying regions under the gate may improve linearity for some semiconductor devices. In the illustrated embodiment, there are a plurality of current-carrying regions 15c under the gate each having a width W.sub.wire. However, as discussed above, each of the current-carrying regions need not have the same width. In the example shown in FIG. 7B, there are ten current-carrying regions 15c, however any suitable number of current-carrying regions 15c may be formed. Region 15c has an effective width, W.sub.eff=N.sub.wireW.sub.wire, where N is the number of current-carrying regions under the gate.

(37) In some embodiments, the current-carrying regions 15c under the gate may be nanowires. The nanowires may not extend beyond an area covered by the gate 13, as extending the nanowires into the source access region 15b or drain access region 15d may limit the current capability of these regions and contribute to non-linearity. In some embodiments, The width W.sub.wire of a nanowire may be less than 500 nm, such as less than 250 nm, less than 125 nm, or less than 75 nm, and may be greater than 10 nm. However, the techniques described herein are not limited in this respect, as other suitable widths may be used. In some embodiments, the spacing s between nanowires may be between 20 nm and 1000 nm. However, the techniques described herein are not limited in this respect, as the techniques described herein are not limited to the spacing between nanowires. The embodiment shown in FIG. 7B shows the gate has a wrap-around configuration with gate material between respective nanowires. FIG. 7C shows a cross-sectional view of field effect transistor 31 along the line H-H of FIG. 7A.

(38) The nanowires may have any suitable cross-section, such as a square cross-section, a rectangular cross section, a rounded cross-section, or any other suitable cross-section. In some embodiments, the nanowires may have a fin-like shape. The techniques described herein are not limited as to the shape of nanowires that may be included in a field effect transistor.

(39) FIGS. 8A-8C show a field effect transistor 41 having regions of limited conductivity 16 between current-carrying regions under the gate, according to some embodiments. FIG. 8A shows a cross-sectional view and FIG. 8B shows a plan view along the line I-I of the field effect transistor 41. Field effect transistor 41 may have a planar gate configuration, as shown in the cross-sectional view along line J-J in FIG. 8C.

(40) Any suitable materials and fabrication techniques may be used to form a field effect transistor.

(41) Any suitable materials maybe used for the source and drain regions, 12, 14 such as metal(s) and/or doped semiconductor. The source and drain regions 12, 14 may have ohmic contacts. In some embodiments, the source region 12 and/or drain region 14 may be formed on the semiconductor region 15. In some embodiments, the source region 12 and drain region 14 may be recessed in the semiconductor region 15 by removing a portion of the semiconductor region 15 at the source and drain regions and filling the cavity with the materials used for the source and drain regions.

(42) A gate 13 to control the transistor may be formed on the semiconductor region 15 or an optional insulating layer. The gate 13 may be formed of any suitable conductor or semiconductor, such as a metal or polysilicon. Optionally, a gate-recess technique may be used to increase the transconductance of the transistor or to form a normally-off transistor. However, the techniques described herein are not limited as to the source, gate and/or drain regions or particular techniques for fabricating them.

(43) The semiconductor region 15 may be formed of a suitable semiconductor material(s). The semiconductor region 15 may include a compound semiconductor material, such as III-V semiconductor material (e.g., a III-N material). In some embodiments, a nitride semiconductor based transistor may be formed in which semiconductor region 15 includes a nitride semiconductor material. In some embodiments, a nitride semiconductor material may be used such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN, for example, in which w, x, y and z each have any suitable value between zero and one (inclusive), and w+x+y+z=1. Examples of nitride semiconductor materials include GaN, AlN, AlGaN, InAlN, InAlGaN, and InGaN, by way of example and not limitation. In some embodiments, the semiconductor region 15 may include a gallium nitride (GaN) semiconductor material. However, the techniques herein are not limited to nitride semiconductor materials being included in semiconductor region 15, as other III-V or II-VI semiconductor materials or IV materials may be used. In some embodiments, semiconductor region 15 may be formed of a group IV semiconductor material such as silicon or germanium, for example.

(44) The semiconductor region 15 may be monocrystalline, and may have any suitable orientation. Compound semiconductor materials, if included in semiconductor region 15, may have any suitable composition at the face of the semiconductor material. If a III-N material is included, it may have an N-face composition, a group III face composition or a non-polar orientation. For example, GaN may be grown either N-face and Ga-face or in non-polar orientations.

(45) The semiconductor region 15 may be comprised of one or more materials, depending on the type of semiconductor device to be formed. The semiconductor region 15 may include one layer of a single material or more than one layer of different materials. In some embodiments, the semiconductor region 15 may include a heterostructure having a plurality of layers of different semiconductor materials. In some embodiments, the plurality of layers may be materials with of different bandgaps and/or polarizations, such as nitride semiconductor materials having different compositions, e.g., B.sub.w1Al.sub.x1In.sub.y1Ga.sub.z1N and B.sub.w2Al.sub.x2In.sub.y2Ga.sub.z2N materials. However, the techniques described herein are not limited as to the formation of heterostructures.

(46) The semiconductor region 15 may be doped or undoped. If the semiconductor region 15 includes a region that is doped, it may be polarization doped or may include dopants such as n-type dopants or p-type dopants. If the semiconductor region 15 is doped, it may have any suitable doping concentration and distribution. If semiconductor region 15 is doped, any suitable doping technique may be used, such as implantation or diffusion, for example.

(47) The reference herein to B.sub.wAl.sub.xIn.sub.yGa.sub.zN or a B.sub.wAl.sub.xIn.sub.yGa.sub.zN material refers to a semiconductor material having nitride and one or more of boron, aluminum, indium and gallium. Examples of B.sub.wAl.sub.xIn.sub.yGa.sub.zN materials include GaN, AlN, AlGaN, AlInGaN, InGaN, and BAlInGaN, by way of illustration. A B.sub.wAl.sub.xIn.sub.yGa.sub.zN material may include other materials besides nitride, boron, aluminum, indium and/or gallium. For example, a B.sub.wAl.sub.xIn.sub.yGa.sub.zN material may be doped with a suitable dopant (e.g., silicon, germanium, etc.). The term gallium nitride (GaN) semiconductor material refers to a semiconductor material that includes gallium and nitrogen and does not exclude other elements of a III-N semiconductor from being present, such as boron, aluminum, and/or indium, for example, and does not exclude the presence of dopants.

(48) Above has been describes techniques for limiting the amount of current that can flow under the gate by limiting the amount of current-carrying material under the gate. However, other techniques may be used to limit the current that can flow in the region under the gate, as an alternative to or in addition to limiting the amount of current-carrying material under the gate. For example, a semiconductor material under the gate may different from a material in an access region. For example, the semiconductor material under the gate may have a lower conductivity than the semiconductor material in the access region. As another example, a highly doped layer (e.g., a highly-doped semiconductor region) may be formed over a semiconductor material in the access region to supply carriers to the access region, thereby raising its current-carrying capability, and such a highly doped layer may not be formed over the semiconductor material under the gate. In an embodiment, a highly doped cap layer (e.g., n+ or p+ doped) may be formed only in the access region(s). As another example, multiple channels at different depths may be formed only in the access region to improve conductivity of the access region with respect to the region under the gate, which may have fewer channel(s). An embodiment of a field effect transistor with multiple channels c1, c2 at different depths in the source access region is illustrated in FIG. 8D. Layers of different semiconductor materials of different bandgaps, for example, may be used to form the channels at different depths.

(49) FIGS. 9A-9H show a method of forming a field effect transistor with a plurality of current-carrying regions under the gate, according to some embodiments.

(50) As shown in FIG. 9A, semiconductor region 15 may be formed over a semiconductor region 17. Source region 12 and drain region 14 may be formed on/in semiconductor region 15. FIG. 9B shows a plan view of the structure of FIG. 9A and indicates the source region a, source access region b, gate region c, drain access region d and drain region e.

(51) As shown in FIG. 9C, a mask layer 18 (e.g., a hard mask) may be formed over the semiconductor region 15 in a wire pattern in regions b, c, and d as shown in FIG. 9C. The mask layer 18 may be Si.sub.3N.sub.4, SiO.sub.2 or any other suitable mask material. The mask layer 18 may be deposited and then a wire pattern may be formed in the semiconductor region 15 through lithography and subsequent etching (e.g., dry etching). In some embodiments, the mask layer 18 may be deposited with plasma-enhanced chemical vapor deposition (PECVD). However, any suitable deposition process may be used. The etching to form the wire pattern in mask layer 18 may use CF.sub.4-based plasma or any other suitable etchant. The gate region c may then be defined using lithography. FIG. 9D shows that regions a, b, d, and e are covered with a resist material 19. Resist material 19 covers regions a, b, d, and e regions to protect them while the gate region c is selectively etched. The etching of the gate region c may be performed using BCl.sub.2/Cl.sub.2-based plasma dry etching or any other suitable etching process. In this example, the mask layer 18 is resistant to the etching and the exposed semiconductor region 15 is etched to the underlying semiconductor layer 17 in region c, as shown in FIG. 9E. Additionally or alternatively, ion implantation may be used to degrade the conductivity of the exposed portions of region 15 under the gate, thereby forming regions of limited conductivity 16, as discussed above. The wire patterns of the mask layer 18 protect the semiconductor region 15 thereunder. After etching and/or ion implantation, the mask layer 18 is removed to expose the protected channel regions, as shown in FIG. 9F. In some embodiments, the mask layer 18 may be removed with a CF.sub.4-based plasma. The gate 13 is deposited over region c and the resist material 19 is removed as shown in FIG. 9G. The nanowire pattern formed by the hard mask material 18 is then removed in regions b and d to leave semiconductor region 15 exposed as shown in FIG. 9H. The mask layer 18 may be removed using wet etching. An additional step may be performed to form a passivation layer (not shown) over regions b, c, and d, leaving the source region 12 and drain region 14 exposed. The passivation layer may be Al.sub.2O.sub.3, in some embodiments. The passivation layer may be deposited by atomic layer deposition (ALD) or any other suitable process.

(52) The foregoing is one example of a fabrication process that may be used to form a field effect transistor, and it should be appreciated that the techniques described herein are not limited in this respect, as any suitable fabrication process may be used.

Example

(53) An example of a prototype device of the high linearity GaN transistor with a nanowire channel has been fabricated. A wafer grown on a SiC substrate by metal-organic chemical vapor deposition may be used. The heterostructure includes 10.3 nm of InAlN, 0.5 nm of AlN, and 1.8 m of GaN. In the sample with 30 nm Al.sub.2O.sub.3 passivation, a 2-D charge density of 1.7610.sup.13, an electron mobility of 1233 cm.sup.2/V.Math.s, and a sheet resistance of 288/ are obtained through Hall measurements.

(54) The fabrication process begins with the selective source/drain regrowth with n.sup.+ InGaN/GaN layers. After device isolation, 50 nm of Si.sub.3N.sub.4 is deposited with plasma-enhanced chemical vapor deposition (PECVD) and nanowire patterns are formed through e-beam lithography and subsequent dry etching with CF.sub.4/O.sub.2 plasma. Then, the second e-beam lithography is conducted to define the gate electrode. By using e-beam resist as a mask, the top InAlN and AlN barrier layers, as well as the first few nanometers of the GaN channel, are etched by a 25-30 nm deep BCl.sub.2/Cl.sub.2 plasma dry etching. During this etch process, the Si.sub.3N.sub.4 nanowire patterns protect the channel in the region that will form the nanowire channel. After the channel etching, the Si.sub.3N.sub.4 nanowire hard-mask is also removed with CF.sub.4/O.sub.2 plasma to expose the protected channel area. Then, gate metal including 10 nm Pt and 30 nm Au is deposited and lifted off by using the remaining e-beam resist. The SEM image in FIG. 10 shows the top view of the device after gate metallization. After removing the Si.sub.3N.sub.4 nanowire hard-mask on the access region with BOE wet etching, oxygen plasma is applied. Finally, 30 nm Al.sub.2O.sub.3 passivation layer was deposited by atomic layer deposition (ALD). For comparison, conventional devices with planar structure are also fabricated right next to the nanowire channel devices by skipping the Si.sub.3N.sub.4 nanowire patterning step. In some embodiments the gate contact may be made only on top of the active channel area by air bridge technology, which can reduce the fringing capacitance and increase the RF performance.

(55) FIGS. 11A and 11B shows a comparison of the DC transfer and output characteristics of L.sub.g=70-80 nm nanowire channel devices with conventional planar transistors. The DC characteristics of the nanowire channel devices are normalized with respect to the effective channel width (W.sub.eff=W.sub.wireN.sub.wire, where W.sub.wire, is wire width and N.sub.wire, is total number of wires) in order to compare the intrinsic device performance. The device has 490 nanowires with about 88-nm width (W.sub.eff=43.1 m) and the spacing between nanowires (W.sub.isol) is about 110-nm. As shown in FIG. 11A, the nanowire channel devices have much flatter extrinsic transconductance (g.sub.m) than the planar device thanks to the relatively larger current drivability of their source access region. That is, even at high drain current, the source access region can provide enough current to the intrinsic device and it suppresses the non-linear access resistance effect by reducing the electric field in the region. This result suggests that the main cause of the peaky behavior of g.sub.m in the conventional planar GaN devices is the increase of the source resistance rather than optical phonon scattering even at short-channel devices with sub-100 nm gate length. The extrinsic g.sub.m of the nanowire channel device is larger than that of the planar device due to about 50% lower access and contact resistance resulting from the larger effective width of its source access region. The threshold voltage (V.sub.t) is also shifted by about 1.4 V (V.sub.ds=3V) in a positive direction due to the side gate effect.

(56) Moreover, the suppression of the non-linear access resistance effect in the nanowire channel device allows realizing the real potential of current drivability in GaN HEMTs. In the conventional device, as the gate bias increases, the increase of the source resistance limits the effective gate overdrive (V.sub.ov.eff=V.sub.gs.effI.sub.dsR.sub.s), so that channel charge cannot increase linearly with the extrinsic gate bias (V.sub.gs). Therefore, the maximum drain current of the conventional short-channel GaN devices is about 22.5 A/mm which is much smaller that the theoretical expectation based on the saturated electron velocity in these devices (45 A/mm). As shown in FIG. 11B, the maximum current density of the nanowire channel device goes above 3.5 A/mm (V.sub.gs=1V) thanks to the constant source resistance even at the high drain current conditions. It shows that the intrinsic GaN device with proper source design can support such a high current density. Another advantage of the proposed structure is the potential to support a high breakdown voltage while maintaining high linearity. Since the constant source resistance need not be obtained through a self-aligned process, the gate-to-drain region may be scaled depending on the target breakdown voltage.

(57) The RF characteristics of the nanowire channel devices are measured from 100 MHz to 40 GHz by using an Agilent N5430A network analyzer and the system is calibrated with an off-wafer LRRM calibration standard, and on-wafer open and short patterns are used to de-embed parasitic pad capacitances and inductances from the measured S-parameters. As shown in FIG. 12, the nanowire channel device has about 40% lower maximum current gain cutoff frequency (f.sub.T) than the planar device due to the larger fringing capacitance from the side gate. However, due to its flatter g.sub.m, the f.sub.T drop at high gate bias is significantly suppressed in the nanowire channel device while a serious degradation of f.sub.T is observed in the planar device. The uniform RF characteristic in the wide range of the bias can be very advantageous for large-signal RF applications by improving the linearity.

(58) Additional Aspects

(59) The techniques described herein may be applied to any type of field effect transistor such as MISFETs (Metal-Insulator Semiconductor Field Effect Transistor), and MESFETs (Metal-Semiconductor Field Effect Transistor) for example. In some embodiments, the techniques described herein may be applied to power transistors. Such techniques can provide improvements in power transistors that will enable significant improvements in power electronics systems for hybrid vehicles, high efficiency power inverters for solar cells, and power converters for LEDs, for example, as well as high-speed digital electronics.

(60) Various aspects of the present invention may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

(61) Also, the invention may be embodied as a method, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

(62) Use of ordinal terms such as first, second, third, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

(63) Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of including, comprising, or having, containing, involving, and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.