SEMICONDUCTOR DEVICE HAVING EPITAXIAL LAYER WITH PLANAR SURFACE AND PROTRUSIONS

Abstract

A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.

Claims

1. A semiconductor device, comprising: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, wherein the epitaxial layer comprises a planar surface and protrusions adjacent to two sides of the planar surface.

2. The semiconductor device of claim 1, further comprising a contact plug embedded in part of the epitaxial layer, wherein a bottom surface of the contact plug comprises an arc.

3. The semiconductor device of claim 2, further comprising a silicide under the contact plug.

4. The semiconductor device of claim 3, wherein a bottom surface of the silicide comprises an arc.

5. The semiconductor device of claim 4, wherein the epitaxial layer comprises silicon phosphide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIGS. 1-10 illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION

[0011] Referring to FIGS. 1-10, FIGS. 1-10 illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 12 is provided, and a first region 14 and a second region 16 are defined on the substrate 12, in which the first region 14 in this embodiment is preferably a NMOS region and the second region 16 is a PMOS region.

[0012] Next, gate structures 18 are formed on the first region 14 and gate structures 20 are formed on the second region 16. In this embodiment, the formation of the gate structures 18, 20 could be accomplished by sequentially forming a gate dielectric layer 22, a gate material layer, a first hard mask, and a second hard mask on the substrate 12, conducting a pattern transfer process by using a patterned resist (not shown) as mask to remove part of the second hard mask, part of the first hard mask, and part of the gate material layer through single or multiple etching processes, and stripping the patterned resist. This forms gate structures 18, 20 composed of patterned material layer 24, patterned hard mask 26, and patterned hard mask 28 on the first region 14 and second region 16 respectively. It should be noted that the quantity of the gate structures 18, 20 on first region 14 and second region 16 is not limited to the ones disclosed in this embodiment.

[0013] In this embodiment, the substrate 12 could be a semiconductor substrate such as a silicon substrate, an epitaxial substrate, a SiC substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The gate dielectric layer 22 could include SiO.sub.2, SiN, or high-k dielectric material; the gate material layer 24 could include metal, polysilicon, or silicide; the hard mask 26 is preferably composed of silicon nitride; and the hard mask 28 is preferably composed of silicon oxide. It should be noted that even though the hard mask 28 composed of silicon oxide is disposed on top of the hard mask 26 composed of silicon nitride, the material of the hard masks 28 and 26 is not limited to the ones disclosed in this embodiment. For instance, the material of hard masks 26 and 28 could be selected from the group consisting of SiO.sub.2, SiN, SiC, and SiON while the hard masks 26 and 28 are composed of different material.

[0014] In addition, a plurality of shallow trench isolations (STIs) 30 is formed in the substrate 12. Despite the present invention pertains to a planar MOS transistor, it would also be desirable to apply the process of the present invention to non-planar transistors, such as FinFET devices, and in such instance, the substrate 12 shown in FIG. 1 would become a fin-shaped structure formed atop a substrate 12.

[0015] Next, a hard mask 32, a hard mask 34, and a hard mask layer 36 are deposited on the substrate 12 to cover the gate structures 18, 20 on first region 14 and second region 16, in which the hard mask 32 is preferably composed of SiOCN, the hard mask 34 is composed of even thicker SiOCN, and the hard mask layer 36 is composed of SiN. In this embodiment, the thickness of the hard mask 34 is between twice to three times the thickness of the hard mask 32, but not limited thereto.

[0016] Next, as shown in FIG. 2, a patterned mask, such as a patterned resist (not shown) is formed on the second region 16, and an etching process is conducted by using the patterned resist as mask to remove part of the hard mask layer 36, part of the hard mask 34, and part of the hard mask 32 on first region 14 for forming spacers 38 and recesses 40 adjacent to the gate structures 18. The patterned resist is stripped thereafter. It should be noted that the part of the hard mask 32 and part of the hard mask 34 on first region 14 are removed during the etching process to form spacers 38, and a major portion of the hard mask layer 36 is removed during the formation of the recesses 40 while a small portion of the hard mask layer 36 is remained on the sidewalls of the spacers 38.

[0017] Next, as shown in FIG. 3, a cleaning process is selectively conducted to completely remove the remaining hard mask layer 36 on the sidewalls of spacers 38 and impurities in the recesses 40, and an epitaxial growth process is conducted to form epitaxial layers 42 in the recesses 40 on first region 14 for serving as source/drain regions. In this embodiment, the epitaxial layer is preferably composed of silicon phosphide (SiP).

[0018] Next, as shown in FIG. 4, another hard mask layer 44 is formed on the first region 14 and second region 16 to cover the gate structures 18 and epitaxial layers 42 on first region 14 and the hard mask layer 36 on second region 16. In this embodiment, the hard mask layer 44 is preferably composed of silicon nitride, but not limited thereto.

[0019] Next, as shown in FIG. 5, a patterned mask, such as a patterned resist (not shown) is formed on the first region 14, and an etching process is conducted by using the patterned resist as mask to remove the hard mask layer 44, part of the hard mask layer 36, part of the hard mask 34, and part of the hard mask 32 on second region 16 for forming spacers 46 and recesses 48 adjacent to the gate structures 20. It should be noted that the hard mask layer 44 on second region 16 is preferably removed completely during the etching process, the hard mask 32 and hard mask 34 are partially removed during the etching process to form. spacers 46, and a major portion of the hard mask layer 36 is removed during the formation of the recesses 48 while a small portion of the hard mask layer 36 is remained on the sidewalls of spacers 46.

[0020] Next, as shown in FIG. 6, a selective cleaning process is conducted to completely remove the remaining hard mask layer 36 on the sidewalls of the spacers 46, impurities in the recesses 48, and part of the hard mask layer 44 on the first region 14 so that the remaining hard mask layer 44 is still disposed on the top and sidewalls of each gate structure 18 as well as on the top surface of the epitaxial layers 42. Next, an epitaxial layer 50 is formed in each recess 48 to serve as source/drain region on the second region 16, in which the epitaxial layer 50 is preferably composed of silicon germanium (SiGe).

[0021] It should be noted the hard mask layer 44 remained on the sidewalls of gate structures 18 and the hard mask layer 44 remained on the epitaxial layer 42 surface after the aforementioned cleaning process typically have different thickness. In this embodiment, the thickness of the hard mask layer 44 remained directly on top of each gate structure 18 or the hard mask layer 44 remained on a sidewall of each gate structure 18 is about twice the thickness of the hard mask layer 44 remained on the epitaxial layer 42 surface. For instance, the thickness of the hard mask layer 44 remained directly on top of each gate structure 18 or the thickness of the hard mask layer 44 remained on a sidewall of the gate structure 18 is approximately 40 Angstroms while the thickness of the hard mask layer 44 remained on the epitaxial layer 42 surface if about 20 Angstroms.

[0022] Referring to FIGS. 7-10, FIGS. 7-10 illustrate a method of using cleaning process to remove the hard mask layer 44 on first region 14 and forming a contact plug 72. It should be noted that in order to emphasize the steps of removing hard mask layer 44 on first region 14 (or NMOS region) and forming contact plug 72, only part of the gate structure 18 and epitaxial layer 42 and a single contact plug 72 connecting the epitaxial layer 42 on first region 14 is revealed in FIGS. 7-10.

[0023] As shown in FIG. 7, a patterned mask (not shown) could be selectively formed on the second region 16, and a first cleaning process is conducted to remove part of the hard mask layer 44 on sidewalls of the gate structures 18 and the hard mask layer 44 on epitaxial layer 42 while forming a protective layer 52 on the epitaxial layer 42. Preferably, the protective layer 52 is composed of silicon oxide and a cleaning agent used in the first cleaning process is selected from the group consisting of diluted hydrofluoric acid (dHF), phosphoric acid (H.sub.3PO.sub.4) , and SC1, in which SC1 being a standard cleaning solution preferably containing elements selected from the group consisting of NH.sub.4OH and H.sub.2O.sub.2.

[0024] Specifically, dHF from the cleaning agent is used to remove native oxides remained on the epitaxial layer 42 surface, phosphoric acid is used to remove the hard mask layer 44 composed of SiN, and the standard cleaning solution SC1 is used to form protective layer 52 composed of silicon oxide. Viewing from a much more detailed perspective, the aforementioned first cleaning process first removes the entire hard mask layer 44 on epitaxial layer 42 surface and part of the hard mask layer 44 on sidewalls of the gate structures 18 and adjacent to two sides of the epitaxial layer 42, and then forms a protective layer 52 on the exposed epitaxial layer 42 surface.

[0025] In this embodiment, the duration of the dHF is approximately 15 seconds, the temperature of the phosphoric acid is preferably between 150 C. to 190 C. or most preferably at 161 C., the duration of the phosphoric acid is preferably less than 60 seconds or most preferably less than 30 seconds, the temperature of standard cleaning solution SC1 is between 25 C. to 60 C., or most preferably at 25 C., and the duration of SC1 is preferably less than 120 seconds or most preferably 90 seconds.

[0026] Next, as shown in FIG. 8, a second cleaning process is conducted to remove the remaining hard mask layer 44 on gate structures 18 to expose the spacers 38, in which the cleaning agent used in the second cleaning process is selected from the group consisting of phosphoric acid and SC1.

[0027] Specifically, phosphoric acid from the cleaning agent in the second cleaning process is used to remove all of the remaining hard mask layer 44 on the gate structures 18, including all the hard mask layer 44 remained on the top and sidewalls of the gate structures 18. Through the protection of the protective layer 52, no damage would be done on the surface of epitaxial layer 42 by the cleaning agent during the cleaning process, and even if part of the protective layer 52 is lost, additional protective layer 52 could be formed again by the standard cleaning solution SC1. In other words, the protective layer 52 is remained still on the surface of epitaxial layer 42 as the hard mask layer 44 is removed by the aforementioned cleaning agent, and even after the hard mask layer 44 is totally removed, part of the protective layer 52 could still remain on the epitaxial layer 42 surface, or could be removed completely, which are all within the scope of the present invention.

[0028] It should be noted that after the aforementioned two cleaning processes are completed, the surface profile of the epitaxial layer 42 is slightly altered according to a preferred embodiment of the present invention. For instance, as shown in FIG. 8, the epitaxial layer 42 after the treatment preferably includes a planar surface 54 and protrusions 56 adjacent to two sides of the planar surface 54.

[0029] Next, as shown in FIG. 9, the remaining protective layer 52 if any could be selectively removed, a contact etch stop layer (CESL) 58 composed of silicon nitride could be selectively formed on the substrate 12 to cover the gate structures 18, and an interlayer dielectric (ILD) layer 60 is formed on the CESL 58. Next, a planarizing process, such as a chemical mechanical polishing (CMP) process is conducted to remove part of the ILD layer 60, part of the CESL 58, the hard masks 28, and the hard masks 26 to expose the gate material layer 24 composed of polysilicon material so that the top surface of the gate material layer 24 is even with the top surface of the ILD layer 60.

[0030] Next, a replacement metal gate (RMG) process is conducted to transform the gate structures 18, 20 on first region 14 and second region 16 into metal gates. The RMG process could be accomplished by first performing a selective dry etching or wet etching process, such as using etchants including ammonium hydroxide (NH.sub.4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 24 from gate structures 18, 20 for forming recesses (not shown) in the ILD layer 60. Next, a high-k dielectric layer 62 and a conductive layer including at least a U-shaped work function metal layer 64 and a low resistance metal layer 66 are formed in the recesses, and a planarizing process is conducted so that the surfaces of the U-shaped high-k dielectric layer 62, U-shaped work function metal layer 64, low resistance metal layer 66, and ILD layer 60 are coplanar.

[0031] In this embodiment, the high-k dielectric layer 62 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer 62 may be selected from hafnium oxide (HfO.sub.2), hafnium silicon oxide (HfSiO.sub.4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al.sub.2O.sub.3) , lanthanum oxide (La.sub.2O.sub.3) , tantalum oxide (Ta.sub.2O.sub.5), yttrium oxide (Y.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), strontium titanate oxide (SrTiO.sub.3), zirconium silicon oxide (ZrSiO.sub.4), hafnium zirconium oxide (HfZrO.sub.4), strontium bismuth tantalate (SrBi.sub.2Ta.sub.2O.sub.9, SBT) , lead zirconate titanate (PbZr.sub.xTi.sub.1-xO.sub.3, PZT), barium strontium titanate (Ba.sub.xSr.sub.1-xTiO.sub.3, BST) or a combination thereof.

[0032] In this embodiment, the work function metal layer 64 is formed for tuning the work function of the later formed metal gates to be appropriate in an NMOS or a PMOS. For an NMOS transistor, the work function metal layer 64 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer 64 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer 64 and the low resistance metal layer 66, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer 66 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. Since the process of using RMG process to transform dummy gate into metal gate is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. Next, part of the high-k dielectric layer 62, part of the work function metal layer 64, and part of the low resistance metal layer 66 are removed to forma recess (not shown), and a hard mask 68 is formed in the recess so that the top surfaces of the hard mask 68 and ILD layer 60 are coplanar. The hard mask 68 could be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

[0033] Next, as shown in FIG. 10, a contact plug formation is conducted with silicide process to form a silicide on the epitaxial layer 42 surface and a contact plug 72 electrically connected to the source/drain region and epitaxial layer 42 adjacent to two sides of the gate structures 18. In this embodiment, the contact plug formation could be accomplished by first conducting an etching process to remove part of the ILD layer 60 between gate structures 18 to form a contact hole (not shown) exposing the epitaxial layer 42 surface. Next, a first metal layer 74 and a second metal layer 76 are deposited in sequence in the contact hole, in which the first metal layer 74 and the second metal layer 76 are formed conformally on the surface of the epitaxial layer 42 and inner sidewalls of the contact hole. In this embodiment, the first metal layer 74 is selected from the group consisting of Ti, Co, Ni, and Pt, and most preferably Ti, and the second metal layer 76 is selected from the group consisting of TiN and TaN.

[0034] After depositing the first metal layer 74 and second metal layer 76, a first thermal treatment process and a second thermal treatment process are conducted sequentially to form a silicide 78 on the epitaxial layer 42. In this embodiment, the first thermal treatment process includes a soak anneal process, in which the temperature of the first thermal treatment process is preferably between 500 C. to 600 C., and most preferably at 550 C., and the duration of the first thermal treatment process is preferably between 10 seconds to 60 seconds, and most preferably at 30 seconds. The second thermal treatment process includes a spike anneal process, in which the temperature of the second thermal treatment process is preferably between 600 C. to 950 C., and most preferably at 600 C., and the duration of the second thermal treatment process is preferably between 100 milliseconds to 5 seconds, and most preferably at 5 seconds.

[0035] After the two thermal treatment processes are conducted, a third metal layer 80 is deposited to fully fill the contact hole. In this embodiment, the third metal layer 80 is composed of tungsten, but not limited thereto. Next, a planarizing process, such as a CMP process is conducted to remove part of the third metal layer 80, part of the second metal layer 76, and part of the first metal layer 74, and depending on the demand of the process also removing part of the ILD layer 60 for forming a contact plug 72 electrically connected to the epitaxial layer 42. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.

[0036] Referring again to FIG. 10, which further illustrates a structural view of a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 10, the semiconductor device includes at least a gate structure 18 on the substrate 12, an epitaxial layer 42 in the substrate 12 adjacent to two sides of the gate structures 18, a contact plug 72 embedded in part of the epitaxial layer 42 and a silicide 78 disposed under the bottom of the contact plug 72. Specifically, the epitaxial layer 42 includes a planar surface 54 and protrusions 56 adjacent to two sides of the planar surface 54, a bottom surface of the contact plug 72 has an arc profile or curved surface, and a bottom surface of the silicide 78, such as the bottom surface contacting the epitaxial layer 42 also has an arc or curved surface.

[0037] Overall, the present invention preferably conducts two cleaning processes after an epitaxial layer is formed adjacent to two sides of a gate structure, in which the first cleaning process removes part of the hard mask layer on sidewalls of the gate structure while forming a protective layer on the epitaxial layer surface and the second cleaning process removes the remaining hard mask layer on the gate structure completely. According to a preferred embodiment of the present invention, it would be desirable to use the protective layer to prevent cleaning agent from damaging the epitaxial layer underneath during the second cleaning process thereby ensuring the operation and performance of the device. It should also be noted that even though the two cleaning processes of the present invention were applied to NMOS transistors in the aforementioned embodiments, it would also be desirable to apply the same cleaning processes to transistors on PMOS region and in such instance, the transistors on PMOS region would also demonstrate epitaxial layer structure with similar planar surface and protrusions, which is also within the scope of the present invention.

[0038] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.