Nanostructured silicon based solar cells and methods to produce nanostructured silicon based solar cells

Abstract

The present invention relates to a plasma texturing method for silicon based solar cells and the nanostructured silicon solar cells produced thereof. The silicon based solar cell comprises a silicon substrate having in at least part of its surface conical shaped nanostructures having an average height between 200 and 450 nm and a pitch between 100 and 200 nm, thereby achieving low reflectance and minimizing surface charge recombination.

Claims

1. A method of producing a silicon based solar cell comprising a silicon substrate, said silicon substrate having a surface wherein at least part of said surface comprises conical shaped nanostructures having an average height between 200 and 450 nm and a pitch between 100 and 200 nm, said method comprising: emitter doping, metal contact deposition and producing conical shaped nanostructure having a height between 200 and 450 nm and a pitch between 100 and 200 nm on said silicon based solar cell by maskless reactive ion etching (RIE), wherein said emitter doping comprises laser doping; wherein said metal contact deposition is applied after said laser doping and, wherein said metal contact deposition occurs onto areas of silicon exposed to said laser doping.

2. The method according to claim 1 wherein said producing conical shaped nanostructure occurs before said emitter doping and said metal contact deposition.

3. The method according to claim 1, wherein said laser doping comprises exposing said silicon solar cell to a light beam with a wavelength in the range of 300-1100 nm.

4. The method according to claim 1, wherein said laser doping comprises exposing said silicon solar cell to a light beam with a wavelength of 532 nm.

5. The method according to claim 1, wherein said laser doping is performed by a pulsed laser and, wherein laser pulses have pulse lengths in the range between 1 s and 1 ps (10.sup.12 s), or between 1 s (10.sup.6 s) and 100 ns (10.sup.9 s).

6. The method according to claim 1, wherein said laser doping is performed by a pulsed laser and, wherein laser pulses have pulse frequency in the range between 1 KHz and 100 MHz, or 100 KHz and 200 KHz.

7. The method according to claim 1, wherein said laser doping is performed by a continuous wave laser.

8. The method according to claim 1, further comprising: passivating said silicon based solar cell by depositing a single layer or a stack of layers of dielectric materials.

9. The method according to claim 8, wherein said passivating occurs prior to said laser doping.

10. The method according to claim 8, wherein depositing said single layer or said stack of layers of dielectric materials comprises depositing Al.sub.2O.sub.3 atomic layer deposition (ALD).

11. The method according to claim 8, wherein depositing said single layer or said stack of layers of dielectric materials further comprises depositing SiN.sub.x:H deposited by plasma enhanced chemical vapour deposition (PECVD).

12. The method according to claim 8, wherein said depositing of said single layer or said stack of layers of dielectric materials comprises depositing a layer of Al.sub.2O.sub.3 having a thickness in the range of 5-50 nm, or 5-30 nm.

13. The method according to claim 1, wherein said metal contact deposition comprises depositions of Ni, Cu and Ag or Sn in a stack and, wherein said metal contact deposition is by electroless/galvanic plating, electroplating or light-induced plating.

14. The method according to claim 8, wherein said passivating further comprises depositing a semiconducting layer.

15. The method according to claim 14, wherein said depositing of said single layer or said stack of layers of dielectric materials comprises depositing a layer of SiO.sub.2 and depositing said semiconducting layer comprises depositing amorphous silicon or polysilicon.

16. The method according to claim 14, wherein said depositing of said layer of SiO.sub.2 comprises depositing a layer of SiO.sub.2 having a thickness of 0.8-2 nm by wet chemical oxidation in nitric acid at a temperature in the range of 20130 C. or thermal oxidation in oxygen or water ambient at a temperature in the range of 8001200 C.

17. The method according to claim 14, wherein said depositing said semiconducting layer comprises depositing a layer amorphous silicon or polysilicon having a thickness of 5-100 nm a by low pressure chemical vapour deposition (LPCVD) using SiH.sub.4, B.sub.2H.sub.6, BCl.sub.3 and/or PH.sub.3 at a temperature in the range of 500-700 C. or by PECVD using SiH.sub.4, Ar, B.sub.2H.sub.6, BCl.sub.3 and/or PH.sub.3 at a temperature of 200-400 C.

18. The method according to claim 9, wherein said laser doping and said metal deposition occur after said passivating.

19. The method according to claim 1, wherein said silicon based solar cell is quasi-mono-crystalline silicon containing 60-99% mono-crystalline silicon based solar cell.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The silicon solar cell and the method according to some aspect the invention will now be described in more detail with regard to the accompanying figures. The figures show one way of implementing the present invention and is not to be construed as being limiting to other possible embodiments falling within the scope of the attached claim set.

(2) FIG. 1 shows a Scanning Electron Microscopy (SEM) image of a nanostructured surface topology according to some embodiments of the invention.

(3) FIG. 2 shows a SEM image top-view of a nanostructured surface topology according to some embodiments of the invention.

(4) FIG. 3 is a graphical representation of the weighted average and minimum reflectance of light of nanostructured surfaces fabricated by RIE according to some embodiments of the invention.

(5) FIG. 4 shows the total weighted (AM1.5) average reflectance as a function of incident angle for a standard, KOH-textured 6 and RIE-textured 7 mono-c Si substrates according to some embodiments of the invention.

(6) FIG. 5 shows the Internal Quantum Efficiency (IQE) of a black Si cell and a KOH-textured reference cells.

(7) FIG. 6 is a flow-chart of a method according to some embodiments of the invention.

(8) FIG. 7a shows a SEM image of a nanostructured surface topology produced by RIE before Atomic Layer Deposition (ALD) of Al.sub.2O.sub.3 according to some embodiments of the invention.

(9) FIG. 7b shows a SEM image of a nanostructured surface topology produced by RIE after ALD of Al.sub.2O.sub.3 having a thickness of 30 nm according to some embodiments of the invention.

(10) FIG. 8 shows surface recombination velocity (SRV) of RIE-textured Cz silicon with ALD Al.sub.2O.sub.3.

(11) FIG. 9 shows minority carrier lifetime of RIE-textured p-type Cz silicon with passivated with SiO.sub.2 and n-type poly-Si according to some embodiments of the invention.

DETAILED DESCRIPTION OF AN EMBODIMENT

(12) Several batches of commercial size and grade silicon solar cells have been fabricated with the nanostructure topology of the invention, and characterized in terms of optical and photovoltaic performance, showing excellent light absorption (<2%, such as lower than 1% reflectance) and high power conversion efficiency, i.e. in the area of 16.5% efficiency. The improved optical performance at non-ideal incident angles has been confirmed by reflectance measurements.

(13) A simple mask-less, scalable RIE nanostructuring of the solar cell surface, according to some embodiments of the invention, is shown to reduce the AM1.5-weighted average reflectance to a level below 1% in a fully optimized RIE texturing, and thus holds a significant potential for improvement of the cell performance compared to current industrial standards. The reflectance is shown to remain below that of conventional textured cells also at high angle of incidence. The production process was successfully integrated in fabrication of solar cells using only industry standard processes on a Czochralski (CZ) silicon starting material. The process is shown to be equally applicable to mono-, multi- and quasi-mono-crystalline Si. The resulting cell performance was compared to cells with conventional texturing showing improved performance.

(14) The data show that the RIE nanostructures lead to superior light absorption independent of crystalline grade and incident angle.

(15) The nanostructures were fabricated as the texturing step in the following solar cell process: 1) Saw damage removal, 2) Texturing using maskless RIE in a O.sub.2 and SF.sub.6 plasma 3) Emitter formation using a POCl.sub.3 doping process, followed by PSG-removal in 5% buffered HF, 4) Deposition of SiNx:H anti-reflective coating using PECVD with SiH.sub.4, NH.sub.3 and N.sub.2, 5) Screen-printing of front and rear, 6) Edge isolation using laser ablation.

(16) The starting substrates were 156156 mm p-type, CZ mono-c Si wafers with a thickness of 200 m and a resistivity of 1-20 cm.

(17) Reflectance measurements of the RIE-textured mono-, multi and quasi-mono Si surfaces were performed using a broadband light source (Mikropack DH-2000), an integrating sphere (Mikropack ISP-30-6-R), and a spectrometer (Ocean Optics QE65000, 280-1000 nm). The reference solar spectral irradiance for AM 1.5 was used to calculate the weighted average reflectance in the wavelength range from 280-1000 nm.

(18) I-V curves on complete cells were measured under 1 Sun illumination (1000 W/m.sup.2) using a xenon light bulb.

(19) FIG. 1 shows SEM-image at 45 tilt of the black silicon surface after RIE-texturing. The nanostructures are h3-400 nm tall and the area density is D 100 m.sup.2.

(20) FIG. 2: SEM-image top-view of a similar nanostructured Si surface. The density of peaks is 50-100 m.sup.2 and typically falls within the range of 75-200 m.sup.2.

(21) FIG. 3 shows weighted (AM1.5) average reflectance before 10 and after 8 emitter diffusion as well as the minimum reflectance 9 of mono-, multi- and quasi-mono Si surfaces, respectively.

(22) FIG. 3 shows average reflectance 10 of RIE-textured Si below 1% for all three crystalline grades of Si. This is a clear improvement compared to KOH- and acidic-textured Si used in standard industrial Si solar cells. The results furthermore show negligible increase in reflectance after emitter diffusion. The RIE-textured Si show near-zero minimum reflectance independent of crystalline grade.

(23) FIG. 4 shows the total weighted (AM1.5) average reflectance as function of incident angle for a standard, KOH-textured 6 and RIE-textured 7 mono-c Si substrates. The reflectance was measured using an integrating sphere with one axis angle variation of the incident optical fiber relative to the Si substrate. The reflectance of the RIE-cell shows to be independent of incident angle up to 40 degrees.

(24) The improved optical performance at non-ideal incident angles is not only important with respect to the varying angle through the hours of the day and days of the year. In a real-life application, the available sunlight is typically diffuse due to clouds, particles in the air etc. Thus, the diffuse light response, i.e. the response to light within a certain range of non-normal incident angles, e.g. between 30 and 60 is very relevant.

(25) FIG. 4 shows that the reflectance of KOH-textured Si increases more with incident angle up to 50 than the reflectance of RIE-textured Si. For angles above 50 the reflectance of RIE-textured Si increases more with incident angle than KOH-textured Si. The reflectance of RIE-textured Si is significantly lower than KOH-textured Si for incident angles of 0-80. This result shows the potential of improved solar cell performance using RIE-texturing at non-ideal incident angles.

(26) FIG. 5 shows the IQE of a black Si cell 5 and a KOH-textured reference cell 4. FIG. 5 shows that the IQE of the RIE-textured solar cell 5 is lower than the IQE of the KOH-textured reference cell 4especially at wavelengths below 600 nm. It is assumed that the decreased IQE of the black Si cell 5 compared to the KOH-cell 4 at wavelengths below 600 nm indicates increased surface recombination, since light with shorter wavelength is absorbed closer to the surface. In order to confirm this, a LASSIE tool was used to evaluate the loss of current density of the differently textured solar cells. The result of this analysis is seen in Table 1.

(27) TABLE-US-00001 TABLE 1 Total Carrier Emitter Bulk Rear Loss recombination recombination recombination KOH 1.385 mA/cm.sup.2 0.761 mA/cm.sup.2 0.207 mA/cm.sup.2 0.192 mA/cm.sup.2 RIE 4.163 mA/cm.sup.2 3.322 mA/cm.sup.2 0.267 mA/cm.sup.2 0.069 mA/cm.sup.2

(28) Table 1 shows the calculated total carrier loss and carrier loss due to emitter, bulk and rear surface recombination for the KOH- and RIE-textured cell.

(29) The assumption that emitter recombination is the primary explanation behind the lower IQE for the RIE-textured cells compared to the KOH-textured is confirmed by the calculated carrier losses in Table 1, since the emitter recombination is the dominant carrier loss mechanism of the RIE-textured cells.

(30) TABLE-US-00002 TABLE 2 PCE [%] J.sub.SC [mA/cm.sup.2] V.sub.OC [V] FF R.sub.av [%] KOH 17.6 36.8 0.62 77.8 2-3 RIE, type 1 15.7 35.3 0.61 72.8 2.85 RIE, type 2 16.5 35.2 0.61 77.7 2.20

(31) Table 2 shows the PV performance results including power conversion efficiency, PCE, short-circuit current, Jsc, open-circuit voltage, Voc, fill factor, FF and weighted average reflectance after emitter diffusion, Ray, of the RIE- and KOH-textured cells.

(32) Table 2 shows that the RIE-textured cells have lower PCE than the KOH-cell due to lower J.sub.SC. The current loss is explained by the increased emitter recombination shown in Table 1. This may be solved by introducing a passivation layer. Examples of cells having a reflectance lower than 1% and achieving reflectance lower than 1% can be produced according to some aspects of the invention.

(33) FIG. 6 is a flow-chart of a method according to some embodiments of the invention.

(34) The method of producing a silicon based solar cell according to the first aspect of the invention comprising: 1 emitter doping, 2 metal contact deposition and 3 maskless RIE producing conical shaped nanostructure having a height between 200 and 450 nm and a pitch between 100 and 200 nm.

(35) Example of Specification of RIE process parameters: Room temperature; 25 C.+/10 degrees Gas flow ratio between SF.sub.6 and O.sub.2=0.5-2 using only one power source.

(36) Some examples of sheet resistance resulting from emitter doping: 40-200 Ohm/sq. in case of conventional emitter (RIE before doping); <10 Ohm/sq. before RIE in case of selective emitter, resulting in 40-200 Ohm/sq. in non-contact areas after RIE; <10 Ohm/sq. in case of RIE after doping, resulting in 40-200 Ohm/sq. after RIE.

(37) FIG. 7a shows a SEM image of a nanostructured surface topology produced by RIE before Atomic Layer Deposition (ALD) of Al.sub.2O.sub.3 according to some embodiments of the invention.

(38) FIG. 7b shows a SEM image of a nanostructured surface topology produced by RIE after ALD of Al.sub.2O.sub.3 having a thickness of 30 nm according to some embodiments of the invention.

(39) FIG. 8 shows surface recombination velocity (SRV) of RIE-textured Cz silicon with ALD Al.sub.2O.sub.3.

(40) The percentages values show how large a part of the total surface with SRV equal to or lower than the value. Values of SRV down to 88 cm/s have been obtained.

(41) Thus, as shown by the very low value of SRV, the use of ALD Al.sub.2O.sub.3. on the nanostructured silicon substrate according to some embodiments of the invention provides an extremely good surface passivation.

(42) TABLE-US-00003 TABLE 3 Surface Recombination Velocity [cm/s] 30 nm ALD Al.sub.2O.sub.3 3 nm Thermal SiO.sub.2 65 nm PECVD SiN.sub.x:H 110-190 610-1010 960-1320

(43) Table 3 shows surface recombination velocity (SRV) of RIE-textured Cz silicon with ALD Al.sub.2O.sub.3, thermal SiO.sub.2 and PECVD SiNx:H and, respectively.

(44) It can be clearly seen that 30 nm ALD Al.sub.2O.sub.3 provides the best passivation onto the nanostructured silicon substrate according to some embodiments of the invention as achieving the lowest surface recombination velocity.

(45) FIG. 9 shows minority carrier lifetime of RIE-textured p-type Cz silicon with passivated with 1.4 nm SiO.sub.2 and 15-40 nm n-type poly-Si.

(46) Passivation of the nanostructured silicon substrate according to some embodiments of the invention can be achieved by a combination of tunnel-oxide and poly-Si passivation.

(47) This passivation is achieved by firstly cleaning a p- and n-type Cz Si starting wafers, for example by RCA-cleaned. This can be performed on Si substrate with or without RIE-nanostructure texturing.

(48) Secondly the oxide can be grown on the substrate, e.g. in 68% HNO.sub.3 at 90-100 C. for 10 min leading to a measured thickness between 1.3 and 1.5 nm.

(49) Thirdly phosphorus-doped amorphous Si may be deposited on top of the oxide, e.g. in LPCVD at 580 C. using SiH.sub.4 and PH.sub.3.

(50) Finally a-Si may be annealed, thus becoming poly-Si, e.g. at 800 C. for 1 hour.

(51) Although the present invention has been described in connection with the specified embodiments, it should not be construed as being in any way limited to the presented examples. The scope of the present invention is set out by the accompanying claim set. In the context of the claims, the terms comprising or comprises do not exclude other possible elements or steps. Also, the mentioning of references such as a or an etc. should not be construed as excluding a plurality. The use of reference signs in the claims with respect to elements indicated in the figures shall also not be construed as limiting the scope of the invention. Furthermore, individual features mentioned in different claims, may possibly be advantageously combined, and the mentioning of these features in different claims does not exclude that a combination of features is not possible and advantageous.