Circuitry useful for clock generation and distribution

Abstract

An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.

Claims

1. An integrated circuit comprising first and second inductor arrangements, wherein: each said arrangement comprises four inductors adjacently located in a group and arranged to define two rows and two columns, the integrated circuit is configured to cause two of those inductors diagonally opposite from one another to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase, the first and second phases of the first inductor arrangement are substantially in quadrature with the first and second phases, respectively, of the second inductor arrangement, each said inductor arrangement defines associated null lines along which its effective electromagnetic field has zero or negligible field strength, and the first and second inductor arrangements are each located substantially along one of each other's said null lines.

2. An integrated circuit as claimed in claim 1, having one or more layers, wherein each said inductor is formed in only one said layer or across a plurality of said layers.

3. An integrated circuit as claimed in claim 1, wherein: the inductors each have one or more turns, and are optionally spiral inductors; or the inductors have the same size and number of turns as one another.

4. An integrated circuit as claimed in claim 3, wherein: the direction of the turns of the inductors is configured so that they produce their respective electromagnetic fields; or the inductors are connected to other circuitry of the integrated circuit or to each other so that they produce their respective electromagnetic fields.

5. An integrated circuit as claimed in claim 1, wherein the inductors each have a centre and a diameter, and wherein a spacing between the centres of the inductors is Z times the diameter of at least one of the inductors, where 1Z50, and preferably where 1Z10.

6. An integrated circuit as claimed in claim 1, wherein: each said arrangement comprises sixteen inductors including said four inductors; the inductors of each said arrangement are arranged to define four rows and four columns; the inductors of each said arrangement are configured so that each of them produces an electromagnetic field having the first phase or the second phase of that arrangement; and for any adjacent group of four of said sixteen inductors spanning two rows and two columns of a said arrangement, diagonally opposite inductors produce electromagnetic fields having the same said phase as one another.

7. An integrated circuit as claimed in claim 1, wherein said electromagnetic fields are fluctuating or alternating fields.

8. An integrated circuit as claimed in claim 1, comprising buffer circuitry adapted to receive and buffer four clock signals being the four phases of a four-phase clock signal, wherein: the first and second inductor arrangements are connected to the buffer circuitry such that their electromagnetic fields are generated from respective said clock signals.

9. An integrated circuit as claimed in claim 8, wherein: the first and second inductor arrangements and the buffer circuitry form a first clock distribution unit, said four clock signals being a first set of four clock signals; the integrated circuit comprises a second said clock distribution unit, adapted to receive and buffer a second set of four clock signals; and the first and second clock distribution units are connected such that a set of clock signals output by the buffer circuitry of the first clock distribution unit, generated by the buffer circuitry of the first clock distribution unit receiving and buffering the first set of four clock signals, are the second set of four clock signals which are received by the buffer circuitry of the second clock distribution unit.

10. An integrated circuit as claimed in claim 9, wherein: the first and second inductor arrangements of the first clock distribution unit are each located such that one of the null lines of the first inductor arrangement of the first clock distribution unit is substantially aligned with one of the null lines of the second inductor arrangement of the first clock distribution unit; the first inductor arrangements of the first and second clock distribution units are each located such that one of the null lines of the first inductor arrangement of the first clock distribution unit is substantially aligned with one of the null lines of the first inductor arrangement of the second clock distribution unit; and the second inductor arrangements of the first and second clock distribution units are each located such that one of the null lines of the second inductor arrangement of the first clock distribution unit is substantially aligned with one of the null lines of the second inductor arrangement of the second clock distribution unit.

11. An integrated circuit as claimed in claim 1, comprising analogue-to-digital converter circuitry or digital-to-analogue converter circuitry.

12. An IC chip comprising an integrated circuit as claimed in claim 1.

Description

(1) Reference will now be made, by way of example, to the accompanying drawings, of which:

(2) FIG. 1, as described hereinabove, presents a schematic view of a system in which clock signals are generated and supplied to DAC or ADC circuitry;

(3) FIG. 2, as described hereinabove, is a schematic view of a differential switching circuit which may form part of the DAC circuitry of FIG. 1;

(4) FIG. 3, as described hereinabove, is a graph representing an example 16 GHz, 4-phase clock signal;

(5) FIG. 4, as described hereinabove, presents waveforms for clock signals CLK .sub.1 to .sub.4 in its upper graph, and partial waveforms for currents received at output nodes A and B in its lower graph, for use in better understanding the operation of the differential switching circuit of FIG. 2;

(6) FIG. 5, as described hereinabove, is a schematic view of sampling circuitry which may form part of the ADC circuitry of FIG. 1;

(7) FIG. 6, as described hereinabove, is a schematic diagram presenting example buffers, buffer stages and polyphase filter stages;

(8) FIG. 7, as described hereinabove, is a schematic diagram indicating that several buffer/polyphase-filter stages may be provided in series in a clock generation and distribution path;

(9) FIG. 8A is a schematic diagram presenting buffer circuitry of FIG. 6, and useful for understanding its operation;

(10) FIG. 8B is a schematic diagram presenting buffer circuitry embodying the present invention, and useful for understanding its operation;

(11) FIGS. 9(a) and 9(b) are schematic diagrams presenting respective sets of buffer circuitry for comparison with one another and with the circuitry of FIG. 8B;

(12) FIG. 10 is a schematic diagram presenting buffer circuitry equivalent to that of FIG. 8B, and graphs useful for understanding its operation;

(13) FIG. 11 is a schematic diagram presenting buffer circuitry embodying the present invention, and a graph useful for understanding its operation;

(14) FIG. 12 is a schematic diagram demonstrating that the buffers of the buffer stages disclosed herein may be implemented by way of differential buffers, and is provided to further consider the impact of inductors of those buffers;

(15) FIGS. 13(a) and 13(b) are schematic diagrams presenting respective different inductor configurations;

(16) FIGS. 14(a) and 14(b) are schematic diagrams indicating null lines of the inductor configurations of FIGS. 13(a) and 13(b), respectively;

(17) FIG. 15(a)-15(d) contain a schematic diagram presenting four possible implementations of the inductor configuration of FIG. 13(b);

(18) FIG. 16(a)-16(d) contain a schematic diagram presenting four possible implementations of an inductor of the inductor configuration of FIG. 13(b);

(19) FIG. 17 is a schematic diagram indicating how differential buffer stages could be provided one after the other along a clock generation path, with each differential buffer having for example two inductor configurations as in FIG. 13(b); and

(20) FIG. 18 is a schematic diagram indicating how differential buffer stages could be provided one after the other along a clock generation path, with each differential buffer having for example one inductor configuration as in FIG. 13(b).

(21) The present inventors have considered how to improve control of buffer circuitry and mitigate mismatch-related issues. In particular, it has been recognised that in buffers 102 implemented as buffer circuitry 120 of FIG. 6, the threshold voltages V.sub.TH of the two transistors govern the bias/average current I that flows through them, which governs the switching delay.

(22) Improved Matching by Current Control:

(23) FIG. 8A presents buffer circuitry 120 again, in its upper portion. The same NMOS and PMOS field-effect transistors (FETs) are shown, and indicated as being susceptible to V.sub.TH variation. That is, the threshold voltages in one such buffer may be different from those in another such buffer. Also indicated is a current I (here, schematically representing an average or bias current), which flows through the two transistors during operation.

(24) In the lower part of FIG. 8A, a parallel set 104 of buffers is indicated, where each buffer is implemented as buffer circuitry 120. Given the above V.sub.TH variation, across the 4 channels CH1 to CH4 the threshold voltages V.sub.TH may be different, and as such given constant V.sub.DD, the currents I would be different giving different delays. This is indicated also in the lower part of FIG. 8A, alongside the parallel set 104 of buffers.

(25) For example, the respective threshold voltages V.sub.TH1 to V.sub.TH4 for the channels CH1 to CH4 are indicated as being different from one another, by way of suffixes 1 to 4 corresponding to the channel numbers. Of course, there are two transistors per buffer, each transistor having its own threshold voltage, however for simplicity it is simply indicated that there is some difference in threshold voltage between the buffers. The entries for V.sub.DD, I and Delay will be understood similarly (in terms of whether or not suffixes are shown) with reference to the circuitry 120 in the upper portion of FIG. 8A. Essentially, given the threshold variation represented by threshold voltages V.sub.TH1 to V.sub.TH4, the delays associated with the four buffers are substantially different (indicated by Delay1 to Delay 4).

(26) Although it may be difficult/impossible to sufficiently match V.sub.TH across the channels (both within a process and across process, given practical manufacturing constraints), it is possible to match the currents I to a high degree (as compared to V.sub.TH matching) and thereby attempt to closely match the delays.

(27) FIG. 8B presents buffer circuitry 130 devised with this in mind. The basic CMOS inverter structure is the same as in circuitry 120 of FIG. 8A, except that the input and output are resistor-coupled with a resistance or resistor 132, and that the input is DC-decoupled from (or AC-coupled to) the preceding stage by way of a capacitor or capacitance 134, which may be referred to as an AC coupling capacitor C.sub.AC.

(28) Additionally, and importantly, a PMOS transistor 136 is provided between V.sub.DD and the PMOS transistor of the inverter, and controlled by a bias voltage Vbias to act as a current source. With the decoupling capacitor 138 as indicated, a local V.sub.DD is created for the CMOS inverter transistors, also as indicated. Given the resistor 132 and capacitor 134 connected as shown, the PMOS transistor 136 acting as a current source controls or defines the average or bias current flowing through both transistors of the CMOS inverter.

(29) The current-source PMOS transistor 136 may be relatively large (as compared to the inverter transistors) and thus it is easier to match across the channels (in terms of V.sub.TH). That is, the threshold voltages V.sub.TH of the current-source PMOS transistor 136 may be matched to a much higher degree across different buffers 130 than the PMOS and NMOS transistors of the inverter portion itself. Therefore, even with a common Vbias across the channels (as opposed to an individual Vbias per channel), it is possible to match the bias current Ibias from the current source across the channels to a high or sufficient degree. Of course, an individual Vbias per channel could be provided.

(30) In the lower part of FIG. 8B (in a similar way as to in FIG. 8A), a parallel set 104 of buffers is indicated, where each buffer is implemented as buffer circuitry 130. Even with the above V.sub.TH variation in the inverter transistors across the 4 channels CH1 to CH4, such that the indicated threshold voltages V.sub.TH are different as in FIG. 8A, Ibias may be the same across the channels (with the effect of differences in local V.sub.DD across the channels) and as such also the delay. This is indicated also in the lower part of FIG. 8A, alongside the parallel set 104 of buffers.

(31) For example, the respective threshold voltages V.sub.TH1 to V.sub.TH4 for the channels CH1 to CH4 are indicated as being different from one another, by way of suffixes 1 to 4 corresponding to the channel numbers, as in FIG. 8A. The entries for local V.sub.DD, Ibias and Delay will be understood similarly with reference to the circuitry 130 in the upper portion of FIG. 8B. Essentially, even with the threshold voltage variation represented by threshold voltages V.sub.TH1 to V.sub.TH4, the currents (Ibias) and the delays (Delay) associated with the four buffers are substantially matched, or approximately the same (indicated by the entries Ibias and Delay being the same for all channels).

(32) This technique has been found to greatly improve the matching between buffers across the channels. In effect, the performance of the buffer circuitry 130 is largely independent of threshold voltage variation in the relatively small (i.e. tiny) inverter transistors.

(33) For example, the PMOS current source (current-control device, current-control switch) provided in FIG. 8B individually defines the average or bias currents of both transistors (signal-path switches) of the CMOS inverter. The average or bias currents of both transistors of the CMOS inverter are defined substantially independently of: (a) the threshold voltages of those transistors; (b) differences between those threshold voltages, and/or (c) differences between those threshold voltages and corresponding reference threshold voltages (for example, expected ideal/target threshold voltages).

(34) FIGS. 9(a) and 9(b) present respective sets of buffer circuitry, to indicate that the inverter arrangement in circuitry 130 is not essential. That is, the inverter arrangement may be considered one example of a switching arrangement comprising at least one signal-path switch configured to switch in dependence upon an input signal, where the switching performance of the buffer circuitry is dependent on a bias current flowing through the or each signal-path switch of the switching arrangement. Similarly, the current source 136 may be considered one example of a current-control arrangement connected to the switching arrangement and configured to control the bias current flowing through the or each signal-path switch so as to control the switching performance of the buffer circuitry.

(35) The buffer circuitry of FIG. 9(a), which is provided as a comparative example, comprise transistors M1 and M2 (implemented here as NMOS transistors), each of which is connected via a resistance to the supply voltage V.sub.DD and which are together connected via a common current source to ground GND. M1 and M2 are connected to receive complementary input signals IN and IN and to output complementary output signals OUT and OUT as shown. Such circuitry may be referred to as a CML (Common-Mode Logic) buffer.

(36) The switching delay is affected by the threshold voltage V.sub.TH of the transistors M1 and M2. Any threshold voltage difference between M1 and M2 means that the delay is different for rising and falling edges of the input signal IN. For example, if there is such threshold voltage mismatch, the current I from the current source does not split equally on average between the two transistors M1 and M2.

(37) For high-speed switching, e.g. to carry high-speed clock signals, it would be desirable to reduce the size of transistors M1 and M2. However, as above, this would increase the likelihood and amount of threshold voltage mismatch between the two transistors.

(38) The buffer circuitry of FIG. 9(b) is similar to that in FIG. 9(a), except that each transistor is provided with its own current source, such that transistor M1 has current source I.sub.1 and transistor M2 has current source I.sub.2. Further, the transistors are now decoupled from one another via a capacitance, with further capacitances coupling the nodes between the transistors and the current sources to ground GND, as shown. The value of these current sources could for example be set as I.sub.1=I.sub.2=I/2.

(39) In FIG. 9(b), in contrast to FIG. 9(a), the two transistors M1 and M2 are provided with their own current sources, so that the (bias) current flowing through them may be set by matching the current sources I.sub.1 and I.sub.2. The current sources may be implemented as transistors having a large gate are relative to the sizes of M1 and M2 (which may be small for high-speed operation and thus have large threshold-voltage mismatch). As such, the current sources may be relatively well matched, rendering the FIG. 9(b) delay-matched buffer circuitry in line with the general principle of the present invention. Essentially, even with the threshold voltage variation between M1 and M2, the bias currents and the delays are substantially matched, or approximately the same. With this principle, good matching could be achieved between several sets of the FIG. 9(b) circuitry, whereas this may not be achieved in respect of the FIG. 9(a) circuitry.

(40) FIG. 10 presents buffer circuitry 140 equivalent to circuitry 130 depicted in FIG. 8B, albeit in an upside-down form with the current source 142 corresponding to current source 136 provided below the CMOS inverter transistors. Also, the decoupling capacitor 138 is shown linking between the upper reference voltage (provided from a driver or amplifier 144) and a node between the CMOS inverter transistors and the current source 142.

(41) The two graphs in FIG. 10 indicate how the performance (AC gain) of the buffer circuitry 140 is related to the AC coupling capacitor C.sub.AC 134 (bearing in mind that it has associated parasitic capacitances, e.g. including those associated with the tracking and the CMOS transistor gates).

(42) In the upper graph, buffer AC gain over frequency is indicated for different sizes of C.sub.AC, named relative to one another as big, optimal and small for simplicity. As can be seen, the frequency response has been found to peak around 5 GHz as opposed to around the example clock frequency 16 GHz, giving suboptimal noise performance (or noise peaking).

(43) The lower graph gives a fuller picture of the effect of varying C.sub.AC at the example clock frequency 16 GHz, and as such represents a snapshot of the upper graph at the 16 GHz point. As indicated, the circuitry suffers from AC coupling gain loss, which varies with C.sub.AC. That is, the ideal case (desired) where gain is independent of the value of C.sub.AC is different from the actual case, where gain peaks at optimal C.sub.AC. The loss is indicated as being represented by the shaded area between the desired (ideal) and actual cases.

(44) Since it may be necessary in practice to turn the power up to compensate for AC coupling gain loss, the knock-on effect may be high power density and potentially hot spots in a circuitry implementation.

(45) FIG. 11 presents modified buffer circuitry 150, intended to address the issues identified above in connection with FIG. 10. As compared with the buffer circuitry 140, in the buffer circuitry 150 the AC coupling capacitor 134 and input-to-output coupling resistor 132 are removed, and current sources 152 and 154 are provided for both the NMOS and PMOS transistors, respectively, with decoupling capacitors 156 and 158 as shown.

(46) As such, separate nbias and pbias controls of the current sources 152 and 154 may be applied to account for variation in V.sub.THN (threshold voltage for the inverter NMOS transistor) and V.sub.THP (threshold voltage for the inverter PMOS transistor), respectively, creating a local V.sub.DD and a local V.sub.SS as shown. The current sources 152 and 154 may be implemented by way of field-effect transistors (which are large relative to the inverter transistors, for reasons of matching) in line with current source 136 of FIG. 8B, and the nbias and pbias controls may thus be understood as gate voltages for those field-effect transistors, one (nbias) associated with the current source for the inverter NMOS transistor and the other (pbias) associated with the current source for the inverter PMOS transistor.

(47) In FIG. 11 two sets of buffer circuitry 150 are shown, one after the next, with only the left-hand buffer being fully labelled for simplicity. Thus, the output of the first buffer 150 becomes the input of the next buffer 150, in line with the buffer stage 100 of FIG. 6.

(48) An inductor L 162 and variable capacitor C.sub.TUNE 164 are provided between the buffers 150, and LC.sub.TUNE may be tuned by way of C.sub.TUNE so that the buffer gain peaks at the example clock frequency 16 GHz, taking into account the parasitic capacitances C.sub.IN and C.sub.OUT as indicated in FIG. 11. These capacitances C.sub.IN and C.sub.OUT are parasitic, i.e. associated with the discrete circuit elements of buffers 150, and are not discrete components themselves.

(49) In the lower portion of FIG. 11, buffer AC gain over frequency is indicated for the buffer circuitry 140 of FIG. 10 and for the buffer circuitry 150 of FIG. 11, to demonstrate that LC.sub.TUNE may be tuned in circuitry 150 by way of C.sub.TUNE so that the buffer gain peaks at the example clock frequency 16 GHz.

(50) In circuitry 150, because there is no longer AC coupling between the buffers, there is no AC loss. C.sub.TUNE does not affect AC loss, it simply tunes the centre frequency.

(51) Incidentally, in FIG. 11 of inductor 162 and capacitor 164 only one of them is shown as being tuneable. Of course, either or both of them could be tuneable. For example, inductors and/or capacitors could be switched in or out to adjust the value of LC.sub.TUNE. Capacitor C.sub.TUNE 164 may be implemented for example as a varicap or a switched capacitor, or a combination of both. Inductor L 162 may be implemented as a switched inductor.

(52) As mentioned before, the transistors forming the current sources 152 and 154 may be large (relative to the CMOS inverter transistors) and thus well matched. The nbias and pbias controls may accordingly be common across the 4 channels CH1 to CH4, matching the currents and thus the delays across the channels. The nbias and pbias controls may, in another embodiment, be separately provided.

(53) Since the current sources 152 and 154 create local V.sub.DD and V.sub.SS for the buffer inverter, they effectively control the amplitude of the clock signals. Thus, amplitude level control (ALC) may be implemented by sensing the amplitude of the clock signals and controlling nbias and pbias accordingly. This could be done per channel or for all 4 channels in parallel. The choice as to whether to carry out such ALC per channel or in common for all channels depends on the accuracy/matching of the circuit that measures amplitude of the clock signals (Vpp) compared to the accuracy/matching of the circuit that sets the bias currents. If the measuring circuit is the more accurate of the two it may be better to have individual gain/bias adjustments (i.e. per channel). If, however, the measuring circuit mismatch is bigger than that of the circuit that sets the bias currents it may be better to control all bias currents together (i.e. in common across the channels).

(54) It has been described above that delays may be matched between buffers by matching currents, since the circuit speed is defined by Ibias. Thus, although the high-speed small gates in the CMOS inverter may have substantial V.sub.TH mismatch (.sub.VTH may for example be approx. 50 mV for such high-speed transistors), good matching across the buffers is achieved. The current-source transistors have larger areas and thus matching is much better than for the high-speed transistorsenabling adoption of common Vbias across channels.

(55) The present invention accordingly addresses the desire to provide <100 fs matching across buffers (1 at 16 GHz=174 fs). Since each channel might have e.g. 10 buffer stages in series, with four parallel channels, there may be 40+ buffers present in the overall clock generation path, e.g. within element 40 of FIG. 1. As such, the present invention has considerable advantages.

(56) Incidentally, MOS transistor current matching does not depend on just gate area but also on the drain saturation voltage V.sub.DSAT (which roughly equals or is related to V.sub.GSV.sub.TH, where V.sub.GS is the gate-source voltage and V.sub.TH is the threshold voltage). The drain saturation voltage V.sub.DSAT is the voltage beyond which the drain current is saturated, and for each gate voltage there is a different drain saturation voltage V.sub.DSAT. As background, the part of the IV curve with V.sub.DS (the drain-source voltage)<<V.sub.DSAT is the linear region, and the part with V.sub.DS>V.sub.DSAT is the saturation region. V.sub.DS and V.sub.DSAT may be thought of as equivalent to the voltage drop across the transistor device. The current mismatch between two such transistors is proportional to the difference in V.sub.TH divided by V.sub.DSAT.

(57) V.sub.TH mismatch is inversely proportional to gate area, so large gate area allows good V.sub.TH matching and high V.sub.DSAT allows good current matching. However high V.sub.DSAT (which gives good current matching) also means that the transistor gain is low and switching speed is slow, and high gate area means high capacitance which also means slow switching.

(58) It may be useful to consider the following equations: V.sub.TH mismatch=K/sqrt(area): K=Pelgrom coefficient, for example K=5 mV.fwdarw.error 5 mV for 1 m.sup.2, 0.5 mV for 100 m.sup.2 V.sub.DSAT is proportional to sqrt(L/W)therefore increasing L by a factor of 10 (whilst keeping W constant).fwdarw.increasing V.sub.DSAT by a factor of approximately 3.2 (sqrt10)

(59) With this in mind, consider the following example:

(60) To switch quickly, the switching transistors (e.g. those of the CMOS inverter considered above) need to be small (e.g. W=3 m, L=0.03 m, gate area=0.1 m.sup.2) and have low V.sub.DSAT (e.g. 100 mV for W/L=100, L/W=0.01). With K=5 mV and 0.1 m.sup.2 area the V.sub.TH error would be 16 mV; with V.sub.DSAT of 100 mV this would give 16% current error.

(61) The current-source transistors, in contrast, can be much bigger than the switching transistors, and have higher V.sub.DSAT, because they are not in the high-speed signal path (i.e. they are not switched by the high-speed input signal, such as a clock or data signal). See, for example, the circuitry of FIGS. 8B and 10. Thus, in this example, the current-source transistors may be relatively big (e.g. W=10 m, L=1 m, gate area=10 m.sup.2) and have relatively high V.sub.DSAT (e.g. 320 mV for W/L=10, L/W=0.1). With K=5 mV and 10 m.sup.2 area the V.sub.TH error would be about 1.6 mV (10 lower than for the switching transistors); with V.sub.DSAT of 320 mV this would give about 0.5% current error (32 lower than for the switching transistors).

(62) Thus, in this example, the matching between the larger current-source transistors is far better than the matching between the smaller switching transistors. In this example, the gate area A.sub.CS of the current-source transistors is 100 times larger than the gate area A.sub.SW of the switching transistors. In practice, A.sub.CS may be 10 to 1000 times larger than A.sub.SW. Further, in this example the channel length L.sub.CS of the current-source transistors is around 33 times larger than the channel length L.sub.SW of the switching transistors. In practice, L.sub.CS may be 10 to 100 times larger than L.sub.SW. Further, in this example the channel width W.sub.CS of the current-source transistors is around 3.3 times larger than the channel width W.sub.SW of the switching transistors. In practice, W.sub.CS may be 1 to 10 times larger than W.sub.SW. Transistor area (i.e. W*L) affects V.sub.TH matching (more area is better), and L/W affects V.sub.DSAT (higher is better), so it is generally much more effective to increase L as much as possible (while keeping V.sub.DSAT within reasonable limits) because this provides advantages in both respects. For example, increasing just W generally has little or no effect on current matching because V.sub.TH mismatch and V.sub.DSAT both decrease together.

(63) Improved Matching by Inductor Design:

(64) Consideration will now be made of the implementation (e.g. layout on chip) of inductors suitable for use in the circuitry described herein.

(65) A feature of the DAC and ADC circuitry described herein, in particular of the clock generation paths and buffers (buffer circuitry) for use with the DAC and ADC circuitry, is the requirement for a large number of inductors to be implemented in a small space (i.e. on chip). To understand this better, reference may be made back to, for example, FIG. 11 which shows an example buffer 150, and FIGS. 1, 6 and 7.

(66) For example, in relation to FIGS. 6 and 7, it is clear that many buffer stages may occur along the clock generation and distribution path. Moreover, each buffer stage 100 comprises one or more buffers per channel. Each polyphase filter stage 110 may also comprise one or more sets 104 of buffers or such buffer stages 100. FIG. 7 indicates that several buffer/polyphase-filter stages may be provided in series to bring the four phases on the respective channels towards the ideal case.

(67) Regarding FIG. 11, note the presence of the inductor 162 at the output of one buffer 150 and/or at the input of the next buffer 150. Such inductors may be connected to ground (GND) or a reference voltage such as VDD. They also may be connected between opposing channels (CH1 and CH3, or CH2 and CH4) if the buffers 150 are implemented as differential buffers.

(68) Thus, looking at FIGS. 6 and 7, and taking into account FIG. 11, a large number of inductors (e.g. 32 or 48) may need to be provided in the clock distribution path. Additionally, such inductors may be provided for the separate channels CH1 to CH4 and thus be connected to different phases of 1 to 4. Magnetic coupling between the inductors gives rise to phase errors in the clock distribution circuitry which is highly undesirable. Recall from the discussion of FIGS. 6 and 7 the desire for better than 100 fs matching between channels.

(69) FIG. 12 is a schematic diagram demonstrating that the buffers of the buffer stages may be implemented by way of differential buffers, and is provided to further consider the importance of the inductors. If the buffer stages were implemented with differential buffers, with clock phases 1 (0) and 3 (180) dealt with by one such buffer and 2 (90) and 4 (270) by another, it could be understood that the interaction between the inductors in each differential buffer might be acceptable (since they are out of phase with one another). However, interaction between the two differential buffers would likely be problematic and may give rise to phase errors (i.e. matching errors) between the channels.

(70) An additional consideration is that the paths/channels in the example circuitry of FIG. 1 must be connected together (e.g. via capacitors 116 in the RC network 112 of the polyphase filter stages 110 as in FIG. 6). Thus, for example, the option of distancing inductors from one another to deal with the potential magnetic coupling and phase errors (by way of isolation by distance) is not available in a practical embodiment in which the buffers disclosed herein (and thus inductors) are employed in clock generation and distribution paths as in FIG. 1. In fact, the sheer number of inductors involved also requires them to be implemented close to one another in practice.

(71) This poses the problem of how to further reduce phase errors between channels, and based on the above study of the importance of the inductors and their potential contribution to such phase errors, how handle such a large number of inductors across several phases (i.e. 1 to 4) in close proximity.

(72) Reference will now be made to FIG. 13, which schematically represents two different inductor configurations.

(73) In FIG. 13(a), an inductor implementation 202 is provided, in which an inductor is implemented as a pair of inductors 204 and 206 having opposite phases.

(74) A reasonable amount of noise (phase error) reduction can be obtained by implementing inductors as a pair having opposite phases, rather than as single inductors.

(75) The inductors 204 and 206 are indicated as circles, with two opposing phases being indicated by + (PLUS) and (MINUS), respectively, where PLUS and MINUS refer to the sign (DC current) or phase (AC current) of the magnetic field generated by currents through the inductors. It will be appreciated that the phases may be achieved by a combination of the direction of the turns of the inductor and the direction in which current flows through the inductor. It will also be understood that PLUS and MINUS are relative to one another, i.e. in antiphase or substantially 180 out of phase with one another.

(76) Also shown in FIG. 13(a) is a second pair of inductors similar to 204 and 206, in the lower portion of the Figure. Arrows are then provided between the pairs to aid an explanation of interaction between the two pairs.

(77) For example, as indicated by the arrows in FIG. 13(a), any interaction between the lower PLUS inductor and the upper PLUS inductor (of the pair) is compensated for largely by interaction between the lower PLUS inductor and the upper MINUS inductor (of the pair). A similar point could be made looking at interaction between the lower MINUS inductor and the pair of inductors, as indicated by the relevant arrows.

(78) In FIG. 13(b), an inductor implementation 212 is provided in accordance with the present invention, in which an inductor is implemented as a group of four inductors 214, 216, 218 and 220, where two have the opposite phase from the other two, and where like phases are diagonally opposite from one another.

(79) It has been recognised that far better noise (phase error) reduction (than with implementation 202) can be obtained by locating inductors having opposite phases in adjacent groups of four, where like phases are diagonally opposite from one another. This may be referred to as a cross-quad group, and such a group is indicated by implementation 212.

(80) Again, also shown in FIG. 13 (b) is a further pair of inductors similar to 204 and 206, in the lower portion of the Figure. Arrows are then provided between the pair and the cross-quad group 212 to aid explanation of interaction therebetween.

(81) For example, as indicated by the arrows in FIG. 13(b), the lower PLUS inductor interacts with each of the four inductors of the cross-quad group. As such, the effect of the cross-quad group 212 on the lower PLUS inductor is virtually non-existent, or at least very small, with the combination of the individual interactions (arrows) leading to substantial cancellation. A similar point could be made looking at the effect of the cross-quad group 212 on the lower MINUS inductor.

(82) The four inductors of the cross-quad group may be considered to be arranged in a two-by-two arrangement on a 2D surface (a semiconductor chip), e.g. with two rows and two columns. The arrangement may be considered to be a 2D arrangement, i.e. on a surface or in practice on a semiconductor chip (although, as below, this may include implementations which take up more than one layer of the chip). The arrangement of the inductors has the appearance of a grid of dots (each dot being an inductor), the dots being regularly arranged. Such a grid may be considered to be based on square or rectangular cells. The arrangement may be considered to be a matrix or rectangular/square array of inductors, defining one or more rows and columns.

(83) Although represented as circles in FIG. 13, the inductors may be implemented in practice as coils which may be planar and may have a spiral form, implemented in the metal layers (i.e. with metal tracking) of a semiconductor chip. Such spirals may be considered to be generally planar, in the sense that they may be implemented over more than one layer of the chip. For example, the spirals may have the appearance of planar spirals when the semiconductor chips is viewed in plan view (i.e. down through the layers from its upper surface), with the different layers superimposed on one another. Of course, parts of the coils occupying different such layers may overlap when the chip is viewed in plan view (e.g. as in a helical coil). Such coils may have one or more turns.

(84) FIGS. 14(a) and 14(b) present the pair 202 and cross-quad group 212 again, to further indicate a benefit of the cross-quad group 212 as compared to the pair 202.

(85) As indicated in FIG. 14(a), the pair 202 (when considered as an electromagnetic transmitter or receiver) has a null running vertically between the two inductors. The cross-quad group 212 however has two nulls, one running vertically through the middle of the group and the other horizontally through the middle of the group. Thus, the cross-quad group 212 offers more potential locations (i.e. along the nulls) where other inductors could be located for reduced interaction therebetween.

(86) Considering FIGS. 13(b) and 14(b), the arrangement of the cross-quad group is such that it has only a small (i.e. negligible) interaction on any adjacent inductor, regardless of the phase carried by that adjacent inductor. This would be true even with reasonablei.e. closespacing between inductor quad groups. In effect the group has little or no effect on its surroundings.

(87) Thus, although the phases of the lower inductors in FIG. 13(b) are the same as phases of the cross-quad group, the group would also have only a small interaction with inductors having other phases. For example, if the cross-quad group were to carry phases 1 (0) and .sub.3 (180), it would have only a small interaction with an adjacent inductor carrying phase 2 (90) or 4 (270), or only a small interaction with an adjacent cross-quad group carrying phases 2 (90) and 4 (270).

(88) By locating inductors or inductor groups relative to one another along nulls as in FIG. 14, for example so that their nulls align, better isolation is achieved than if they were to be located without aligning the nulls.

(89) Incidentally, the above discussion focuses on electromagnetic (i.e. magnetic) coupling. Capacitive coupling (E-field) reduces with distance D having a 1/D relationship and can be greatly reduced further or almost eliminated by adding conductive metal shields in between circuits. On the other hand, magnetic coupling (H-field) reduces more slowly with distance D having a 1/[log D] relationship (see below), and shields are less effective because on-chip metals (e.g. aluminium, copper) have low permeability. Thus, for circuits spaced apart by a typical distance magnetic coupling is generally a much bigger problem than capacitive coupling, especially since it is more difficult to shield and falls off more slowly with distance.

(90) FIGS. 15(a)-15(d) present four possible configurations of the cross-quad group of FIG. 13(b), and is provided to indicate that what is important in the cross-quad group is that the inductors of the group carry two opposite phases (i.e. in antiphase) and that like phases are diagonally opposite from one another. It is this, rather than any particular connections between the inductors of the group, which provides the desired effect. That is, the connections are made between the inductors having in mind the signals which will be applied in order to arrange for like phases to be diagonally opposite from one another. It will be appreciated that the direction of coil winding in each inductor can be either clockwise or anticlockwise, and that it is possible to connect the four inductors in different ways and to different phases of the clock generation circuitry. As such, FIGS. 15(a) to 15(d) simply show that many different topologies are available, and are not to be taken as showing the only available arrangements.

(91) FIGS. 16(a)-16(d) present four possible configurations of an inductor of a cross-quad group, implemented as flat spiral. As above, the direction of coil winding in each inductor can be either clockwise or anticlockwise, and it is possible to connect an inductor in different ways and to different phases of the clock generation circuitry. As such, FIGS. 16(a) to 16(d) simply show how PLUS and MINUS phases for the inductors may be generated using a single input clock phase (e.g. 1). If the opposite clock phase (e.g. 3) were to be input instead, of course the PLUS and MINUS phases would be reversed in FIGS. 16(a)-16(d). Of course, PLUS and MINUS are phases relative to one another as mentioned above, as the field in each inductor alternates over time with the input sinusoidal clock signals.

(92) Incidentally, although a cross-quad group of inductors as in FIG. 13(b) provides a significant improvement over providing simply pairs as in FIG. 13(a), it is also considered that most of the available benefit has been obtained with the cross-quad group and that the using groups with higher numbers of inductors may be less preferable in practice.

(93) For example, the magnetic coupling may be considered as: Single: 1/log(D) Pair: 1/log(D).Math.D Cross-quad: 1/log(D).Math.D.sup.2 Next-larger group: 1/log(D).Math.D.sup.3 where D is distance.

(94) That is, it is considered not worthwhile in practice to provide larger inductor groups than the cross-quad group since the overall circuitry size would need to increase every time an inductor is divided into two (LN.sup.2, where L is inductance and N is the number of turns).

(95) Incidentally, the next number of inductors which could form a group with a similar effect beyond 4 is realistically 16. By way of explanation, the number should be even for PLUS and MINUS to give acceptable cancellation; if each individual inductor (or the overall array) is rectangular, the next sizes up could be 6 or 8, but to get a real increase in isolation (1/log(D).Math.D.sup.3 as above) a group of 16 would be the next step up. However, a group of 4 (cross-quad group) is a preferred embodiment. Of course, a cross-quad group embodying the present invention may form part of a larger group of inductors (e.g. a group of 16), so that such a larger group embodies the present invention.

(96) FIG. 17 indicates schematically how differential buffer stages DB could be provided one after the other along the clock generation path, with each differential buffer having for example two cross-quad groups of inductors. Only two successive buffer stages are shown, however many may be provided.

(97) In FIG. 17, each cross-quad group is represented by a group of four circles in a similar manner as in FIG. 13(b), and as such each differential buffer stage DB is shown having one cross-quad group below it and one above it. Given that the buffers here are differential buffers, the upper buffer stages are shown handling (opposing) phases 1 and 3, and the lower stages are shown handling (opposing) phases 2 and 4.

(98) FIG. 18 also indicates schematically how differential buffer stages DB could be provided one after the other along the clock generation path, but with each differential buffer having for example one cross-quad group of inductors. For example, the circuitry laid out as in FIG. 17 may be difficult to implement, given the need for connections between the phases in PPFs as mentioned earlier (see for example network 112 in FIG. 6). In FIG. 18, the two differential buffers in each stage are adjacently located, with the cross-quad groups arranged towards the outside of the pair of differential buffers. For example, a cross-quad group carrying phases 1 and 3 is shown at the top, then the 1/3 differential buffer, then the 2/4 differential buffer, and then a cross-quad group carrying phases 2 and 4 at the bottom. PPF connections may then be made between the central differential buffers.

(99) In both FIGS. 17 and 18, null lines are presented in dashed form in line with FIG. 14(b), to demonstrate that the cross-quad groups are arranged with their nulls aligned.

(100) It will be appreciated that if 48 inductors (as might be required in the circuitry of FIG. 1) were each divided into a cross-quad group, almost 200 inductors (192) would be needed. The area that this could take up on chip in practice may be around 1 mm.sup.2 in current IC processes, representing a significant portion of the overall circuitry for example when implementing DAC and/or ADC circuitry in line with FIGS. 2 and 5. Indeed, the inductor area may be bigger than that of the other circuits (buffers, resistors, capacitors) added together. However, the saving provided by the present invention as compared to conventional inductors may be very significant; for example, if conventional inductors need 2/3/4 spacing to reduce coupling between those inductors, circuit area with conventional inductors could be up to 4/9/16 larger.

(101) The present disclosure extends to buffer circuitry in accordance with the present invention and an inductor arrangement in accordance with the present invention in combination. For example, the inductor 162 in the circuitry 150 may be implemented as (or part of) a cross-quad group of inductors as described above.

(102) Circuitry of the present invention may from part of an analogue-to-digital converter. Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

(103) The present invention may be embodied in many other different forms, within the scope of the appended claims.