Bit-interleaver for an optical line terminal

Abstract

Proposed is a bit-interleaver for an optical line terminal of an optical access network. The bit-interleaver contains a memory reader, that provides data streams at bit level to a space-time switch. The space-time switch reads within one input cycle up to N bit sets from the data streams. The switch switches within one writing cycle up to N bits onto up to its output ports, which provide respective output vectors. A number of N OR-function elements determine within the writing cycle respective single output bits. A number of N memory elements write within the one writing cycle a respective one of the output bits into a respective one of their bit sub-elements. A control unit that controls the reading of the data streams and also the switching of the bits by the switch. The control unit controls a choice of the writing addresses.

Claims

1. A Bit-Interleaver for an Optical Line Terminal of an Optical Access Network, comprising: a memory configured to receive and provide a first number of data streams assigned to respective optical network units, a space-time configured to, read within one input cycle up to the first number of bit-sets from said data streams, and switch within one writing cycle up to a second number of bits of said data streams to up to the second number of output ports in order to provide output vectors, the second number of OR-function elements configured to determine within said one writing cycle single output bits based on one of said output vectors, by combining all bits of the one of said output vectors by a Boolean OR-function; the second number of memory elements, each of the memory elements including at least a third number of bit sub-elements having sub-element writing addresses, each of the memory elements configured to write within said one writing cycle one of the single output bits into one of the bit sub-elements; and a control unit configured to control, the reading of said data streams by said space-time switch, the providing of, the output vectors to the output ports by said space-time switch, and a selection of the sub-element writing addresses of said bit sub-elements, based on data rates, offset values, a maximum number of bits within a bit-frame, a maximum number of the output ports of the space-time switch, and a minimum number of the bit sub-elements of the memory elements.

2. The Bit-Interleaver according to claim 1, wherein said control unit is configured to control said space-time switch, such that said data streams are read at said data rates, and said control unit is configured to choose within said one writing cycle said writing addresses of said bit sub-elements to a same address value.

3. The Bit-Interleaver according to claim 1, wherein each of said bit-sets read from said respective data streams contains K bits.

4. The Bit-Interleaver according to claim 1, wherein said control unit is furthermore configured to control respective reading addresses for reading within one reading cycle respective one of the second number of bits from said second number of memory elements.

5. The Bit-Interleaver according to claim 1, wherein said control unit is configured to choose within said one reading cycle said reading addresses to a same address value.

6. An Optical Line Terminal for an Optical Access Network, comprising a Bit-Interleaver according to claim 1.

7. A method of bit-interleaving for an Optical Access Network, comprising: receiving and providing a first number of data streams assigned to respective optical network units; reading within one input cycle up to the first number of bit-sets from said data streams, using a space-time switch; switching within one writing cycle up to a second number of bits of said data streams to up to the second number of output ports in order to provide output vectors, using said space-time switch; determining within said one writing cycle single output bits based on one of said output vectors, by combining all bits of the one of said output vectors by a Boolean OR-function; writing within said one writing cycle one of the single output bits into a bit sub-element of the second number of memory elements, wherein said bit sub-element has has a respective sub-element address; controlling, the reading of said data streams by said space-time switch, the providing of, the output vectors to the output ports by said space-time switch, and a selection of the sub-element writing addresses of said bit sub-elements, based on data rates, offset values, a maximum number of bits within a bit-frame, a maximum number of the output ports of the space-time switch, and a minimum number of the bit sub-elements of the memory elements.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIGS. 1a, b and c show a bit-interleaving principle for different data streams at same data rates.

(2) FIGS. 2a, b and c show a bit-interleaving principle for different data streams at different data rates.

(3) FIGS. 3a, b and c show resulting output vectors with different memory states for different memory elements at different time instances for the bit-interleaving method realizing same data rates for the different data streams.

(4) FIGS. 4a, b and c show different resulting output vectors together with different states of different memory elements at different time instances for the bit-interleaving method realizing different data rates for the different data streams.

(5) FIGS. 5 and 6 show resulting data streams obtained by reading sets of bits from the memory elements.

(6) FIG. 7 shows a proposed bit interleaver according to a preferred embodiment.

DESCRIPTION OF EMBODIMENTS

(7) FIG. 7 shows a proposed bit-interleaver BI.

(8) The bit interleaver BI contains a FIFO-reader FR, which receives M different data streams OD1, . . . OD4. The FIFO-reader is one example of a memory reader that can be used for receiving and reading the different data streams OD1, . . . OD4. Alternative types of memory readers may be used instead.

(9) In this example, the number M of the data streams is chosen to M=4 without any limitation.

(10) The FIFO-reader FR provides the different data streams OD1, . . . , OD4, to a space-time switch STS. The different data streams OD1, . . . , OD4 are data streams assigned to respective optical network units.

(11) The space-time switch STS receives within a reading cycle up to M respective bit sets BS1, . . . BS4, which are extracted from the respective data streams OD1, . . . , OD4. Each of the bit sets BS1, . . . BS4 contains K bits. In this example, the number K of the bits within a bit set is chosen to K=8 without any limitation.

(12) The space-time switch STS may receive within one reading cycle a set of K=8 bits from each of the data streams OD1, . . . OD4. In this case, the data rate, at which the different data streams OD1, . . . , OD4 are read, is the same for all data streams. For realizing different data rates for the different data streams OD1, . . . , OD4, the space-time switch STS may read within different successive reading cycles different numbers of bit sets from the different data streams OD1, . . . , OD4. For example, within a first reading cycle, the space-time switch STS may read from each of the data streams OD1, . . . OD4 respective bit sets BS1, . . . , BS4, while in the next following reading cycle the space-time switch STS reads respective bit sets BS1, BS2 only from the data streams OD1, OD2. The result of such reading of bit sets within different reading cycles by the space-time switch is, that the data streams OD1, OD2 experience a reading at a data rate, that is twice the data rate, at which the data streams OD3, OD4 are being read.

(13) The space-time switch STS switches within one writing cycle up to N bits onto up to N output ports of the switch STS. At each of the N output ports, a respective output vector v0, . . . , v(N1) is provided. In which way the switch STS switches the bits of the data streams into the output vectors v0, . . . , v(N1) will be described in detail later on.

(14) A control unit CU is connected to the switch STS and the reader FR. Thus, the control unit CU controls the reading of the data streams from the reader FR by the space-time switch STS. Furthermore, the control unit CU controls, in which way the switch STS switches the read bits onto the output ports and thus into the respective output vectors v0, . . . , v(N1).

(15) The resulting output vectors v0, . . . , v(N1) are then provided to respective OR-function elements O0, . . . , O(N1). The output vectors v0, . . . , v(N1) are of a bit length of J=3. The bit length of the output vectors is chosen in this example to J=3 without any limitation.

(16) The OR-function element O0 determines within one writing cycle a single output bit b0 based on the output vector v0. For this, the OR-function element O0 combines all bits present within the vector v0 by a boolean OR-function. The respective further OR-function elements O1, . . . , O(N1) determine from the respective vectors v1, . . . , v(N1) respective single output bits b1, . . . , b(N1).

(17) The control unit CU controls the reading addresses used for reading up to N bits from the respective N memory elements within one reading cycle.

(18) The reason, why such a reduction of the output vectors v0, . . . , v(N1) to the output bits b0, . . . , b(N1) is necessary, is that within one writing cycle, each of the vectors v0, . . . , v(N1) contains only one bit that is switched by the switch STS. The reason for this in turn is, that using a space-time switch STS for switching the bits of the bit streams onto output vectors at the different output ports is a prominent solution, but due to internal scheduling properties of such a switch STS, it cannot be guaranteed that at each instance of a writing cycle one of the bits of the data streams can be switched into exactly the first bit position of an output vector v0, . . . , v(N1). In the case, that not all bits of a bit set BS1, . . . , BS4 are switched onto respective output ports of the switch STS within a same writing cycle, one or more bits of such a bit sequence BS1, . . . , BS4 has to be delayed internally by the space-time switch STS, which in turn causes such a delayed bit to be placed inside one of the output vectors v0, . . . , v(N1) at a bit position that is different from the first bits position of the output vector. However, using a space-time switch with output vectors v0, . . . , v(N1) for the bit-interleaver BI is a favorable solution, since such a switch STS is a prominent device for switching bits from different input ports to different output ports. The resulting shift of a switched bit to a resulting bit-position within an output vector is compensated for by the OR-function elements O0, . . . , O(N1).

(19) The determined single output bits b0, . . . , b(N1) are then provided to respective memory elements M0, . . . , M(N1). Each of the N memory elements M0, . . . , M(N1) comprises at least L bit sub-elements with respective addresses. Within one writing cycle, a memory element M0, . . . , M(N1) writes a respective single output bit b0, . . . , b(N1) into one of its sub-elements at bit level. The choice of the writing address, which determines to which bit sub-element a memory element M0, . . . , M(N1) writes the respective received output bit b0, . . . . , b(N1), is chosen by the control unit CU. This choice of the writing address in detail will be described later on.

(20) The proposed bit-interleaver BI is able to provide within one writing cycle up to N output bits at the respective memory elements M0, . . . , M(N1), from which these output bits can be read out as a whole within one reading cycle. Thus, after having written within one writing cycle up to N bits into the memory elements M0, . . . , M(N1), these N bits can then be read out within a reading cycle just after the N-th bit has been written into one of the memory elements M0, . . . , M(N1). The bit-interleaver BI does not have to perform writing of all B bits of a global frame into a large memory, before extracting the whole global frame.

(21) The bit-interleaver BI may process writing of up to N bits each within successive writing cycles into the memory elements and may then read out successive sets of N bits in following reading cycles for forming successive bits of a corresponding global frame. Thus, the proposed bit-interleaver BI achieves a reduced latency in comparison to the solution when writing all bits of a global bit-interleaving frame into a whole memory and then reading out the whole global frame after having written all bits into the single large memory.

(22) Even furthermore, since the rates, at which the switch STS reads the bit-sets BS1, . . . , BS4 of the data streams OD1, . . . , OD4, is controlled by the control unit CU, and since furthermore the switching properties of the switch STS as well as the reading and the writing addresses of the memory elements M0, . . . , M(N1) are controlled by the control unit CU, the proposed bit-interleaver is a solution of great flexibility, allowing the control unit CU to achieve different data rates for the different data streams OD1, . . . , OD4 with a low latency at high speed bit-interleaving. Even furthermore, since only N memory elements M0, . . . , M(N1) are used, the power consumption imposed by the proposed bit-interleaver BI is smaller than a solution, in which a whole global frame of B bits has to be written into a memory holding these B bits.

(23) Preferably, the control unit CU is provided with pre-determined data rates R(i), wherein the index i of a data stream in this example ranges from i=1, . . . , M=4. The control unit CU uses these pre-determined data rates R(i), for controlling the reading of the bits sets BS1, . . . , BS4 by the space switch STS from the FIFO reader FR. Furthermore, the control unit CU is provided with pre-determined offset values o(i), with index i, which define an offset of the different bits of the different data streams OD1, . . . , OD4 within a global frame. The function of these offsets will be described in detail later on.

(24) Even furthermore, the control unit CU is provided with a pre-determined value B of bits present within a global frame and also the number N of the memory elements, as well as the number L of the bit sub-elements of a memory. Thus, the control unit CU chooses the output port and the writing addresses in dependence on pre-defined data-rates, pre-defined offset values, a maximum number B of bits present within a frame, the number N of memory elements and the number L of bit sub-elements.

(25) FIG. 1a shows different bit streams OD1, . . . , OD4 together with the bits A1, . . . , A8, B1, . . . , B8, C1, . . . , C8, D1, . . . , D8 as sequences over time t.

(26) FIG. 1b shows a bit-interleaving pattern of a global frame GF, in which the different bits of the data streams from the FIG. 1a are interleaved. FIG. 1b shows the interleaving of the different bits of the data streams for the case, that the data rates R(1), R(2), R(3), R(4) are all equal to 1/8 for all the data streams. In other words, all data streams have same rates R(1), . . . , R(4). The maximum number B of bits present within the global frame GF may be for example 1,228,800 bits. Such a global frame may have a time duration of 122 microseconds.

(27) The first bit of the data stream OD1, which is the bit A1, is placed at the bit position 0 of the global frame GF. Due to the fact, that the rate R(1) chosen for the bit stream OD1 is 1/8, the next bit A2 of the data stream OD1 is placed 8 further bits apart from the first bit A1, such that the bit A2 is placed in the bit position 8. Further bits A3, A4, A5 of the data stream OD1 follow at next bit positions 16, 24, 32 within the global frame GF.

(28) For the shown BIPON bit-interleaving scheme placing bits within a global frame, the bit position bp(x(i),i) of the x-th bit of the data stream with index i can be in general determined, by using the reciprocal value r(i)=1/R(i) of the rate R(i), an offset value o(i) and an integer value x(i). The integer value x(i) corresponds to the index number of the x-th bit and is thus an integer number ranging from x(i)=0 up to the integer value x(i)=int(B/r(i)). Thus, the bit position bp(x(i),i) of the x-th bit of the data stream with index i can be determined for decimal numbers as
bp(x(i),i)=o(i)+r(i)*x(i).

(29) Thus, the control unit CU determines for the x-th bit of the i-th data stream a corresponding bit-position within the global frame as described above in detail.

(30) In this example, the offset value o(1) is chosen to o(1)=0 for the data stream OD1.

(31) In FIG. 1b, it is also shown the relationship of the bits D1, D2, . . . of the data stream OD4 within the global frame GF. Due to the fact, that the rate R(4) is also chosen as R(4)=1/8 for this bit-interleaving scheme, also the bits D1, D2, . . . of the data stream OD4 are each spaced 8 bit positions apart within the global frame GF. The offset value o(4) is chosen as the value 04=3 in this example. The offset values for the bits of the data streams OD2, OD3 are not explicitly shown in the FIG. 1b, but it can be said, that the offset value o(2) is chosen to the value o(2)=1, while the offset value o(3) is chosen to the value o(3)=2.

(32) Looking at FIG. 1b, it becomes clear, that optical network units receiving this global frame GF may perform reception of bits of one of the data streams at a data rate, which is equal to data rate of the global frame GF divided by 8.

(33) FIG. 1c shows an alternative bit pattern ABP, in which the different bits of the global frame shown in FIG. 1b are split into sets of N bits. Over time, different sets of N bits may be read out from the memory devices M0, . . . , M(N1) shown in FIG. 7, and later on be successfully transmitted for realizing a transmission of a bit sequence corresponding to the global frame GF shown in FIG. 1b.

(34) The first set, which has to be read in a first reading cycle from the memories M0, . . . , M(N1) shown in FIG. 7, is the set S1. The bits of this set S1 correspond to those bits, which are stored within the bit positions 0 to 15 of the global frame GF of FIG. 1b.

(35) Within a next reading cycle, the next set of bits S2, shown in the FIG. 1c, shall be read out from the memory elements M0, . . . , M(N1) shown in FIG. 7. These are the bits allocated to the bit positions 16 to 31 of the global frame GF shown in FIG. 1b.

(36) Within a third reading cycle, the set of bits S3, shown in FIG. 1c, shall be read out from the memory elements M0, . . . , M(N1) shown in FIG. 7. These are the further bits starting at the bit positions 32 of the global frame GF shown in FIG. 1b.

(37) It will be now explained in detail, in which way different bits of different data streams are to be switched by the switch STS and written to the memories M0, . . . , M(N1), shown in FIG. 7, and furthermore also read from these memories.

(38) It shall be assumed, that the switch STS reads within one input cycle bit sets BS1, . . . , BS4 of K=8 bits each from the fiber reader FR. Within a writing cycle, the space time switch STS switches the first and the second bit of the bit sets BS1, . . . , BS4 onto respective output ports and thus into the respective vectors v0, . . . , v15, as shown in FIG. 3a. Due to internal scheduling properties of the switch STS, the switched bits are present within first bit positions, with the index 0, within the output vectors v0, . . . , v15. As an example, the bit length of the output vectors v0, . . . , v15 is chosen to J=3 as a non-limiting example.

(39) The number of the output port and thus also the number of the corresponding output vector, to which the switch STS switches at specific bit, is controlled by the control unit CU. The control unit CU determines the number of the output port, and thus the number of the output vector and also the resulting number of the memory M0, . . . , M(N1), to which a bit is switched, as the port number pn(x(i),i)=bp(x(i),i) mod N for decimal numbers. For each bit, the bit position by may be determined by the control unit CU as previously described above.

(40) FIG. 3a shows furthermore the different states of the different memory elements M0, . . . , M15 at a time instance t=0. The different OR-function elements reduce the different output vectors v0, . . . , v15 to single output bits b0, . . . , b(N1), which are then written into respective bit-sub-elements of respective memories M0, . . . , M(N1), wherein these bit-sub-elements are of a same writing address. In this example, the writing address is equal to 0. The control unit CU determines within one writing cycle for the x-th bit of the i-th data stream the writing address wa in dependence on the bit position of the x-th bit of the i-th data stream and the number L. In detail, the writing address wa of the x-th bit of the i-th data stream can be determined for decimal numbers as
wa(x(i),i)=int(bp(x(i),i)/L).

(41) Looking at the memory elements M0, . . . , M15 at the time instance t=0, an appropriate set of N bits, shown as the bit set S1 in FIG. 1c, can be read from the memories, by reading out all the memories M0, . . . , M15 at one time instance with a same reading address. In this example, the reading address is equal to the value 0.

(42) This reading has not to be performed exactly at a time instance at which the bits have finally been written into the memory elements M0, . . . , M15, but may be performed at a later point in time. The reading of the bits from the memory elements M0, . . . , M15 with the appropriate reading address is controlled and determined by the control unit CU shown in FIG. 7.

(43) Within a next writing cycle, the switch switches bits of the different data streams onto output ports and into corresponding output vectors v0, . . . , v15 at the time instance t=1, as shown in FIG. 3b. The placement of the bits A3, . . . , D4 at a bit position 0 within the vectors v0, . . . , v15 is caused by internal scheduling properties of the switch.

(44) As previously described, the mentioned OR-function elements O0, . . . , O(N1), shown in FIG. 7, generate single output bits, which are then written at this time instance t=1 into respective bit sub-elements of the memory elements M0, . . . , M15, as shown in FIG. 3b.

(45) Within this next writing cycle, the control unit CU determines for the x-th bit of the i-th data stream the number of the output port and thus the number of the memory element, to which the resulting output bit is written, as the port number pn in dependence on the bit-position bp(x(i),i). In detail, the control unit CU determines for the x-th bit of the i-th data stream the port number pn for decimal numbers as
pn(x(i),i)=bp(x(i),i)mod N.

(46) Furthermore, using the respective bit positions by of the different bits A3, . . . , D4, the control unit CU of FIG. 7 determines the writing address wa for decimal numbers as
wa(x(i),i)=int(bp(x(i),i)/L).

(47) By looking at FIG. 3b, it becomes evident, that a next set of N=16 bits can be read out from the memory elements M0, . . . , M15, by reading out the 16 bits present within these memory elements at same reading addresses, which is in this example are the reading address of the value 1.

(48) Thus, when having to read successive sets of N bits from the different memory elements, for forming a bit sequence corresponding to a global frame of a BIPON scheme, one may simply read out such N bits from the N memory elements, using a same reading address for all of these N memory elements within a same reading cycle and then simply increasing the reading address for the next reading cycle.

(49) For the further bits A5, . . . , D6, the FIG. 3c shows for a next time instance t=2, in which way the proposed choice for switching these bits and writing these bits into the memories M0, . . . , M15 leads to a placement of the bits within the memory elements at specific bit sub-elements.

(50) A resulting bit sequence RBS, shown in FIG. 5, results from reading sets of N bits from the N memory elements with a same reading address within each respective reading cycle. By comparing the resulting bit sequence RBS of FIG. 5 with the initially desired bit sequence of the global frame GF in FIG. 1b, it become clear, that the proposed bit-interleaver BI in FIG. 7 is able to perform the desired bit-interleaving of a global frame shown in FIG. 1b.

(51) FIG. 2a shows once again the different data streams OD1, . . . , OD4.

(52) FIG. 2b shows a desired bit sequence of a global frame GF2 in the case, that the data stream OD1 shall be interleaved at a rate of 1/8 and also the data stream OD4 shall be interleaved at a rate 1/8, while the data stream OD2 shall be interleaved at a rate of 1/16 and the data stream OD3 shall be interleaved at rate of 1/32.

(53) The offset values of the different data streams are chosen as previously described with regard to FIG. 1b.

(54) FIG. 2c shows the corresponding alternative bit pattern ABP2 with sets of N=16 bits over time t. The resulting sets of bits S11, S12, S13 are such, which shall be present within the memory elements M0, . . . , M(N1) at bit sub-elements of same addresses, as shown in FIG. 7.

(55) FIG. 4a shows the resulting placement of the different bits A1, . . . , D2 within the output vectors v0, . . . , v15, as well as the memory element M0, . . . , M15.

(56) At the next time instance t=1, the bits of the set S12 shown in FIG. 2c have to be placed within the output vectors v0, . . . , v15, as shown in FIG. 4b.

(57) Due to the fact, that the bit B2 has to be switched by the space time switch STS, shown in FIG. 7, the internal scheduling properties of this switch STS cause a placement of this bit B2 within the bit position of the value 1 in the output vector v1. As previously described in detail, the OR-function elements achieve a reduction of the respective output vectors v0, . . . , v15 to respective output bits b0, . . . , b(N1), as shown in FIG. 7.

(58) The resulting single output bits are then written within one writing cycle corresponding to the time instance t=1 into bit sub-elements of the writing address wa(x(i),i)=int(bp(x(i),i)/L).

(59) For the next further time instance t=2, FIG. 4c shows the placement of the different bits within the output vectors v0, . . . , v15 as well as within bit-sub-elements of a same writing address, equal to the value 2, of the memory elements M0, . . . , M15.

(60) By looking at FIG. 4c at the right hand side, it becomes evident, that it is now possible to read out at successive reading cycles respective sets of N bits from the different memory elements M0, . . . , M15, wherein within one reading cycle a same reading address is used for choosing the bit sub-element of each memory element M0, . . . , M15.

(61) By reading out sets of N bits from the memory elements as previously described above within successive reading cycles, a resulting bit pattern RBS2 can be achieved, as shown in FIG. 6. By comparing the bit sequence RBS2 of FIG. 6 with the desired bit sequence of bits of the global frame GF2 of FIG. 4b, it becomes evident, that the proposed bit-interleaver BI shown in FIG. 7 achieves the desired method of bit-interleaving needed for a BIPON.

(62) The choice of the number of bit sub-elements to L=3 is only an exemplary choice. Preferably the number of bit-sub-elements present within a memory element is chosen to L=1024.

(63) For achieving an overall data rate of 10 gigabit per second, one may choose the number of N to 64, while reading out such sets of N bits at a rate or frequency of f=156, 25 MHz. As an alternative example, sets of N=32 bits may be written and read at a frequency of f=312, 5 MHz for achieving the same bit rate of 10 gigabit per second. Even alternatively, one may choose the number of N to N=128 with a reading frequency of f=78, 125 MHz.

(64) It is an evident advantage of the proposed bit-interleaver BI shown in FIG. 7, that the global latency of the system is low, since the reading process of interleaved bits from the memory elements M0, . . . , M(N1) can be started, before all the interleaving processes of all bits forming a global frame is finished.

(65) Preferably, the different sub-devices of the bit-interleaver BI shown in FIG. 7 are implemented within a single field programmable gate array (FPGA), in the case that the memory reader is a FIFO-reader.

(66) The functions of the various elements shown in the FIG. 7, including any functional blocks labeled as control unit, may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term control unit should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the FIGS. are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.