Self-calibrating fractional-N phase lock loop and method thereof

Abstract

A circuit receives a reference clock and output an output clock in accordance with a clock multiplication factor, the circuit comprising: a digitally controlled timing adjustment circuit, a timing detection circuit, a loop filter, a controllable oscillator, a clock divider, a modulator, and a calibration circuit, wherein the modulator is configured to modulate a clock multiplication factor into a division factor and also calculate a pre-known noise caused by the modulation, and the digitally controlled timing adjustment circuit, the timing detection circuit, the loop filter, the controllable oscillator, and the clock divider form a feedback loop such that a frequency of the output clock is equal to a frequency of the reference clock multiplied by the clock multiplication, but a pre-known noise caused by the modulation is corrected by the digitally controlled timing adjustment circuit, which is calibrated by the calibration circuit in a closed-loop manner to minimize a correlation between the pre-known noise and an output of the timing detection circuit.

Claims

1. A circuit comprising: a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal; a timing detection circuit configured to receive the third clock and the fourth clock and output a timing error signal; a filtering circuit configure to receive the timing error signal and output an oscillator control signal; a controllable oscillator configured to receive the oscillator control signal and output a fifth clock; a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor; a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor; and a calibration circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.

2. The circuit of claim 1, wherein a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a fixed timing offset.

3. The circuit of claim 1, wherein the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal.

4. The circuit of claim 3, wherein a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal.

5. The circuit of claim 4, wherein the calibration circuit comprises a charge pump configured to receive the timing error signal and output an intermediate current signal in accordance with a common-mode feedback voltage, a single-pole-double-throw switch controlled by a sign of the noise cancellation signal, an integrator configured to receive the intermediate current signal via the single-pole-double-throw switch and output the gain control signal, and a common-mode feedback network configured to receive a first voltage at a positive input terminal and a second voltage at a negative input terminal of the integrator and output the common mode feedback voltage, wherein: a first throw of the single-pole-double-throw switch couples to the positive input terminal of the integrator, and a second throw of the single-pole-double-throw switch couples to the negative input terminal of the integrator.

6. The circuit of claim 5, wherein the integrator comprises a differential operational amplifier and two feedback capacitors.

7. The circuit of claim 6, wherein the single-pole double-throw switch is configured to steer the intermediate current to the positive input terminal of the integrator when the noise cancellation signal is of a first sign, and steer the intermediate current to the negative input terminal of the integrator when the noise cancellation signal is of a second sign.

8. The circuit of claim 1, wherein the modulator comprises a first order delta-sigma modulator.

9. The circuit of claim 1, wherein the controllable oscillator is a voltage-controlled oscillator.

10. The circuit of claim 1, wherein the clock divider is a counter.

11. A method comprising: receiving a first clock and a clock multiplication factor; modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor; establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor; deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with the noise cancellation signal and a gain control signal; establishing a timing error signal by detecting a timing difference between the fourth clock and the third clock; filtering the timing error signal into an oscillator control signal; outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator; outputting the second clock by dividing down the fifth clock in accordance with the division factor; and adjusting the gain control signal in accordance with a correlation between the timing error signal and the noise cancellation signal.

12. The method of claim 11, wherein the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal.

13. The method of claim 12, wherein a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal.

14. The method of claim 11, wherein adjusting the gain control signal in accordance with a correlation between the timing error signal and the noise cancellation signal the calibration circuit comprises using a calibration circuit comprising: a charge pump configured to receive the timing error signal and output an intermediate current signal in accordance with a common-mode feedback voltage, a single-pole-double-throw switch controlled by a sign of the noise cancellation signal, an integrator configured to receive the intermediate current signal via the single-pole-double-throw switch and output the gain control signal, and a common-mode feedback network configured to receive a first voltage at a positive input terminal and a second voltage at a negative input terminal of the integrator and output the common mode feedback voltage, wherein: a first throw of the single-pole-double-throw switch couples to the positive input terminal of the integrator, and a second throw of the single-pole-double-throw switch couples to the negative input terminal of the integrator.

15. The method of claim 14, wherein the integrator comprises a differential operational amplifier and two feedback capacitors.

16. The method of claim 15, wherein the single-pole double-throw switch is configured to steer the intermediate current to the positive input terminal of the integrator when the noise cancellation signal is of a first sign, and steer the intermediate current to the negative input terminal of the integrator when the noise cancellation signal is of a second sign.

17. The method of claim 11, wherein modulating the clock multiplication factor into the division factor comprises using a first order delta-sigma modulator.

18. The method of claim 11, wherein the controllable oscillator is a voltage controlled oscillator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A shows a functional block diagram of a fractional-N phase lock loop in accordance with an embodiment of the present invention.

(2) FIG. 1B shows a schematic diagram of a phase/frequency detector.

(3) FIG. 1C shows a schematic diagram of a charge pump.

(4) FIG. 1D shows a schematic diagram of a loop filter.

(5) FIG. 1E shows a schematic diagram of a voltage-controlled oscillator.

(6) FIG. 1F shows a functional block diagram of a digitally controlled timing adjustment circuit.

(7) FIG. 1G shows a schematic diagram of a digitally controlled variable-delay circuit.

(8) FIG. 2 shows a schematic diagram of a calibration circuit.

(9) FIG. 3 shows a schematic diagram of a modulator.

(10) FIG. 4 shows a flow diagram of a method in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(11) The present invention relates to phase lock loops. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

(12) FIG. 1A shows a functional block diagram of a PLL 100 in accordance with an embodiment of the present invention. PLL 100 comprises: a digitally controlled timing adjustment circuit 160 configured to receive a first clock CK1 and a second clock CK2 and output a third clock CK3 and a fourth clock CK4 in accordance with a noise cancellation signal N.sub.C and a gain control signal G.sub.C; a phase/frequency detector (PFD) 110 configured to receive the third clock CK3 and the fourth clock CK4 and output a timing error signal S.sub.TE representing a timing difference between the third clock CK3 and the fourth clock CK4; a charge pump (CP) 120 configured to convert the timing error signal S.sub.TE into a correction current I.sub.C; a loop filter (LF) 130 configured to receive the correction current I.sub.C and output a control voltage V.sub.CTL; a voltage-controlled oscillator (VCO) 140 configured to output a fifth clock CK5 in accordance with the control voltage V.sub.CTL; a clock divider 150 configured to receive the fifth clock CK5 and output the second clock CK2 in accordance with a division factor N.sub.DIV; a modulator (MOD) 170 configured to output the division factor N.sub.DIV and the noise cancellation signal N.sub.C in accordance with a clock multiplication factor N.sub.MUL; and a calibration circuit 180 configured to output the gain control signal G.sub.C in accordance with a correlation between the timing error signal S.sub.TE and the noise cancellation signal N.sub.C. For brevity, hereafter the first (second, third, fourth, fifth) clock CK1 (CK2, CK3, CK4, CK5) is simply referred to as CK1 (CK2, CK3, CK4, CK5), the timing error signal S.sub.TE is simply referred to as S.sub.TE, the correction current I.sub.C is simply referred to as I.sub.C, the control voltage V.sub.CTL is simply referred to as V.sub.CTL, the noise cancellation signal N.sub.C is simply referred to as N.sub.C, the gain control signal G.sub.C is simply referred to as G.sub.C, clock multiplication factor N.sub.MUL is simply referred to as N.sub.MUL, and the division factor N.sub.DIV is simply referred to as N.sub.DIV.

(13) PLL 100 will be the same as the aforementioned prior art PLL if the digitally controlled timing adjustment circuit 160 and the calibration circuit 180 are removed and PFD 110 receive CK1 and CK2, instead of CK3 and CK4. Similar to the prior art PLL, PLL 100 receives CK1 and outputs CK5 using VCO 140, which is adjusted in a closed loop manner via a feedback path comprising the clock divider 150, PFD 110, CP 120, and LF 130, such that a frequency of CK5 is equal to a frequency of CK1 times N.sub.MUL, which is not a pure integer. Since N.sub.MUL is not a pure integer but N.sub.DIV (which is the clock division factor of the clock divider 150) needs to be an integer, N.sub.DIV must be modulated in a way such that a mean value of N.sub.DIV equals N.sub.MUL. Modulator 170 receives N.sub.MUL and outputs N.sub.DIV, effectively modulating N.sub.DIV such that the mean value of N.sub.DIV equals N.sub.MUL. In doing so, the average frequency of CK5 is equal to the frequency of CK1 times N.sub.MUL, but an instantaneous timing of CK2 might deviate from an ideal timing of a fractional clock divider that allows a non-integer division factor of N.sub.MUL. The deviation of the instantaneous timing of CK2 from the ideal timing due to the modulation of N.sub.DIV leads to an instantaneous noise in the timing difference between CK2 and CK1. However, the instantaneous noise of the timing difference between CK2 and CK1 due to the modulation of N.sub.DIV is pre-known. The instantaneous noise is calculated by the modulator 170 and represented by N.sub.C. The digital controlled timing adjustment circuit 160 is configured to correct the instantaneous noise in the timing difference between CK2 and CK1 due to the modulation of N.sub.DIV, such the timing difference between CK4 and CK3 is free of the instantaneous noise. However, N.sub.C is numeric and digital in nature, while the timing difference between CK2 and CK1 is temporal analog in nature. A function of digital-to-analog conversion is performed by the digitally controlled timing adjustment circuit 160 to convert N.sub.C into the amount of timing difference that needs to be cancelled. G.sub.C determines a gain control of the digital-to-analog conversion.

(14) In an embodiment, a function of the digitally controlled timing adjustment circuit 160 can be described by the following mathematical expression:
t.sub.4t.sub.3=t.sub.2t.sub.1+N.sub.C.Math.G.sub.C+t.sub.OS(1)
Here, t.sub.1 is a timing of a rising edge of CK1, t.sub.2 is a timing of a rising edge of CK2, t.sub.3 is a timing of a rising edge of CK3, t.sub.4 is a timing of a rising edge of CK4, and t.sub.OS is a fixed timing offset. Here, t.sub.2t.sub.1 is a timing difference between CK2 and CK1, while t.sub.4t.sub.3 is a timing difference between CK4 and CK3. S.sub.TE represents a relative timing between CK4 and CK3 and is mathematically equal to t.sub.4t.sub.3. N.sub.C presents the instantaneous noise in t.sub.2t.sub.1 due to the modulation of N.sub.DIV. If G.sub.C, which is the conversion gain for converting N.sub.C into the timing difference to be cancelled, is set properly, the noise in t.sub.2t.sub.1 due to the modulation of N.sub.DIV will be corrected and absent in t.sub.4t.sub.3. On the other hand, if G.sub.C is not set properly, the noise will be either over-corrected or under-corrected, resulting in a residual noise in t.sub.4t.sub.3 that will become a part of S.sub.TE. When G.sub.C is set too large (small), the noise will be over-corrected (under-corrected); as a result, t.sub.4t.sub.3 will contain a residual noise that is positively (negatively) correlated with N.sub.C, and therefore a level of S.sub.TE will tend to be too high (low) when N.sub.C is positive and too low (high) when N.sub.C is negative. Calibration circuit 180 thus adjusts G.sub.C in accordance with a correlation between N.sub.C and S.sub.TE: when S.sub.TE is positively (negatively) correlated with N.sub.C, it indicates G.sub.C is too large (small) and needs to be decreased (increased).

(15) In an embodiment depicted in FIG. 1B, PFD 110 comprises two data flip-flops (DFF) 111 and 112 and an AND gate 113. Each DFF comprises an input terminal labeled D, an output terminal labeled Q, a reset terminal labeled R, and a clock terminal denoted by a wedge symbol; such notations are widely used in the prior art. DFF 111 outputs a first logical signal UP while DFF 112 outputs a second logical signal DN. The AND gate 113 receives the two logical signals UP and DN and outputs a reset signal RST. The first (second) logical signal UP (DN) is asserted upon a rising edge of CK3 (CK4) and is de-asserted when the reset signal RST is asserted. The two logical signals UP and DN jointly embody the timing error signal S.sub.TE representing a timing difference between CK3 and CK4; such embodiment is widely used and well known in the prior art and thus not explained in detail here.

(16) In an embodiment depicted in FIG. 1C, CP 120 comprises a current source 121 configured to source a charge-up current I.sub.UP, a current sink 122 configured to sink a charge-down current I.sub.DN, a first switch 123 configured to couple the charge-up current I.sub.UP to an output node 125 when the logical signal UP is asserted, and a second switch 124 configured to couple the charge-down current I.sub.DN to the output node 125 when the logical signal DN is asserted. The output node 125 interfaces with and provides the correction current I.sub.C to LF 130 of FIG. 1A. Throughout this disclosure, VDD denotes a power supply node. FIG. 1C is well known in the prior art and self-explanatory to those of ordinary skill in the art and thus not described in detail here.

(17) In an embodiment depicted in FIG. 1D, LF 130 comprises a resistor 131, a first capacitor 132, and a second capacitor 133, configured to receive the correction current I.sub.C from CP 120 of FIG. 1A and output the control voltage V.sub.CTL to VCO 140 of FIG. 1A. FIG. 1D is well known in the prior art and self-explanatory to those of ordinary skill in the art and thus not described in detail here.

(18) In an embodiment depicted in FIG. 1E, VCO 140 comprises a voltage-to-current converter (V-to-C converter) 141 configured to convert the control voltage V.sub.CTL into a control current I.sub.CTL, a current mirror 143 configured to mirror the control current I.sub.CTL into a mirrored current I.sub.M, and a ring oscillator 146 configured to output CK5 in accordance with the mirrored current I.sub.M. The voltage-to-current converter 142 comprises a NMOS transistor 142. The current mirror 143 comprises two PMOS transistors 144 and 145. The ring oscillator comprises three inverters 147, 148, and 149 configured in a ring topology, jointly receiving the mirror current I.sub.M. When the control voltage V.sub.CTL rises, the control current I.sub.CTL rises, and so does the mirrored current I.sub.M. As a result, the three inverters 147, 148, and 149 receive more power and become faster, resulting in a higher oscillation frequency for CK5.

(19) Clock divider 150 can be embodied by a counter that increments a count upon a rising edge of CK5. The count starts with 0, increments to 1 upon a rising edge of CK5, then increments to 2 upon a next rising edge of CK5, and so on. When the count reaches N.sub.DIV1, it wraps around to 0 upon a next rising edge of CK5. In this manner, the counter cyclically counts from 0 to N.sub.DIV1. CK2 is asserted whenever the count equals 0, and de-asserted otherwise.

(20) Digitally controlled timing adjustment circuit 160 receives CK1 and CK2 and outputs CK3 and CK4, so that a timing difference between CK4 and CK3 is related to a timing difference between CK2 and CK1 in accordance with a relation described by equation (1). In an embodiment depicted in FIG. 1F, digitally controlled timing adjustment circuit 160 comprises: a fixed-delay circuit 161 configured to receive CK2 and output CK4, and a digitally controlled variable-delay circuit 162 configured to receive CK1 and output CK3 in accordance with G.sub.C and N.sub.C. The fixed-delay circuit 161 provides a fixed timing difference between CK4 and CK2; that is, t.sub.4t.sub.2 is fixed. On the other hand, the digitally controlled variable-delay circuit 162 provides a variable timing difference between CK3 and CK1 and the variable timing difference is controlled by G.sub.C and N.sub.C; that is, t.sub.3t.sub.1 is variable and controlled by G.sub.C and N.sub.C. As a result, t.sub.4t.sub.3 is different from t.sub.2t.sub.1 by a variable amount controlled by G.sub.C and N.sub.C. In particular, the variable timing difference is linearly dependent on N.sub.C, and also linearly dependent on G.sub.C. In an embodiment, the fixed-delay circuit 161 is simply a short circuit; in this case, the fixed delay is zero and CK3 is the same as CK1. In an alternative embodiment, the fixed-delay circuit is an inverter chain that includes an even number of inverters configured in a cascade topology.

(21) In an embodiment, G.sub.C is a differential signal comprising a first end G.sub.C+ and a second end G.sub.C, wherein G.sub.C G.sub.C+G.sub.C. By way of example but not limitation, N.sub.C is a four-bit word comprising four bits N.sub.C[0], N.sub.C[1], N.sub.C [2], and N.sub.C [3]. In an embodiment depicted in FIG. 1G, the digitally controlled variable-delay circuit 162 comprises: a tunable inverter 167 configured to receive CK1 and output an intermediate clock CM at a circuit node 165 in accordance with a control by with G.sub.C; an output inverter 168 configured to receive the intermediate clock CKI and output CK3; and a variable capacitor 166 configured to provide a capacitive load at the circuit node 165. The tunable inverter 167 comprises: a first PMOS transistor MP1 configured to provide a source current I.sub.SC in accordance with G.sub.C+; a first NMOS transistor MN1 configured to provide a sink current I.sub.SK in accordance with G.sub.C; a second PMOS transistor MP2 controlled by CK1 and configured to enable the source current I.sub.SC to charge the variable capacitor 166 when CK1 is low; and a second NMOS transistor MN2 controlled by CK1 and configured to enable the sink current I.sub.SK to discharge the variable capacitor 166 when CK1 is high. The variable capacitor 166 comprises four capacitors 163_0, 163_1, 163_2, and 163_3 configured to conditionally shunt the circuit node 165 to ground via four switches 164_0, 164_1, 164_2, and 164_3 in accordance with N.sub.C [0], N.sub.C [1], N.sub.C [2], and N.sub.C [3], respectively. The output inverter 168 serves as an inverting buffer, and together with the tunable inverter 167 causes CK3 to be the same as CK1 except for a delay. In an embodiment, a capacitance of the variable capacitor 166 increases linearly with a value of N.sub.C. A low-to-high (high-to-low) transition of CK1 will cause the tunable inverter 161 to discharge (charge) the variable capacitor 166 via the second NMOS (PMOS) transistor MN2 (MP2) using the sink (source) current I.sub.SK (I.sub.SC), resulting in a high-to-low (low-to-high) transition of CKI. In an embodiment, a magnitude of the source (sink) current I.sub.SC (I.sub.SK) is negatively linearly dependent on G.sub.C+ (G.sub.C), i.e. a positive increment of G.sub.C+ (G.sub.C) leads to a negative increment of the source (sink) current I.sub.SC (I.sub.SK). The time that CKI takes to finish the high-to-low (low-to-high) transition in response to the low-to-high (high-to-low) transition of CK1 is linearly dependent on a total capacitance at the circuit node, but negatively linearly dependent on the magnitude of the sink (source) current I.sub.SK (I.sub.SC). Since the capacitance of the variable capacitor is linearly dependent on the value of N.sub.C and the magnitude of the source (sink) current I.sub.SC (I.sub.SK) is negatively linearly dependent G.sub.C+ (G.sub.C), the time that the intermediate clock CM takes to finish the transition is approximately linearly dependent on N.sub.C and also linearly dependent on G.sub.C. Therefore, digitally controlled timing adjustment circuit 160 effectively embodies equation (1).

(22) The calibration circuit 180 outputs G.sub.C based on a correlation between S.sub.TE and N.sub.C. In an embodiment, G.sub.C is established in accordance with an algorithm of adaptation described by the following equation

(23) $\begin{array}{cc}{G}_C^{\left(\mathrm{new}\right)}=\{\begin{array}{cc}{G}_C^{\left(\mathrm{old}\right)}-.Math.S_{\mathrm{TE}}& \mathrm{if}{N}_C>0\\ G_C^{\left(\mathrm{old}\right)}& \mathrm{if}{N}_C=0\\ G_C^{\left(\mathrm{old}\right)}+.Math.S_{\mathrm{TE}}& \mathrm{if}{N}_C<0\end{array}& \left(2\right)\end{array}$
Here, is an adaptation constant, G.sub.C.sup.(old) is a value before adaptation, and G.sub.C.sup.(new) is a value after adaptation. A calibration circuit 200 depicted in FIG. 2 can be used to embody the calibration circuit 180 of FIG. 2 in accordance with the algorithm of adaptation described in equation (2). Calibration circuit 200 comprises: a charge pump 210 configured to receive S.sub.TE, which comprises UP and DN as explained earlier, and output an intermediate current signal I.sub.C in accordance with a common-mode feedback voltage V.sub.CMFB; an integrator 230 configured to receive the intermediate current signal I.sub.C via a single-pole-double-throw (SPDT) switching network 220 and output the gain control signal G.sub.C comprising the first end G.sub.C+ and the second end G.sub.C; and a common-mode feedback network 250 configured to output the common-mode feedback voltage V.sub.CMFB. The calibration circuit 200 further comprises a sign detection circuit 260 configured to receive N.sub.C and output a pair of logical signals POS and NEG that are used to control SPDT switching network 220. CP 210 comprises a current source 211 configured to source a charge-up current I.sub.UP, a current sink 212 configured to sink a charge-down current I.sub.DN, a first switch 213 configured to couple the charge-up current I.sub.UP to an output node 215 when the logical signal UP is asserted, and a second switch 214 configured to couple the charge-down current I.sub.DN to the output node 215 when the logical signal DN is asserted. The output node 215 interfaces with and provides the intermediate current signal I.sub.C to the SPDT switching network 220. The sign detection circuit 260 comprises a sign operator 261 and an inverter 262. When N.sub.C is positive, POS is asserted and NEG is de-asserted. When N.sub.C is negative, POS is de-asserted and NEG is asserted. When N.sub.C is zero, POS and NEG are both de-asserted. The two logical signals POS and NEG, therefore, represents a sign of N.sub.C. The SPDT switching network 220 comprises two switches 221 and 222 controlled by the two logical signals POS and NEG, respectively. The integrator 230 comprises a fully differential operational amplifier 233 and two capacitors 231 and 232 configured in a negative feedback topology. The fully differential operational amplifier 233 comprises two input terminals labeled as + and on the left side and two output terminals labeled as + and on the right side. The voltages at the two input terminals are V.sub.X+ and V.sub.X, respectively. The voltages at the two output terminals are G.sub.C and G.sub.C+, respectively. When N.sub.C is positive and consequently POS is asserted, the capacitors 232 is charged (discharged) by I.sub.C via the switch 221 if I.sub.C is positive (negative), resulting in a decrement (increment) of G.sub.C+, and thus a decrement (increment) of G.sub.C. When N.sub.C is negative and consequently NEG is asserted, the capacitors 231 is charged (discharged) by I.sub.C via the switch 222 if I.sub.C is positive (negative), resulting in a decrement (increment) of G.sub.C, and thus an increment (decrement) of G.sub.C. Also, the intermediate current signal I.sub.C is a current-mode representation of S.sub.TE. Therefore, G.sub.C is adjusted with an incremental amount proportional to S.sub.TE when N.sub.C is positive, and proportional to S.sub.TE when N.sub.C is negative. As a result, G.sub.C is adjusted with an incremental amount proportional to S.sub.TE when N.sub.C is positive, and proportional to S.sub.TE when N.sub.C is negative. The calibration circuit 200 thus embodies the function described by equation (2).

(24) The CM feedback network 250 comprises: two resistors 252 and 253 configured to form a serial connection between V.sub.X+ and V.sub.X to tap a common-mode voltage V.sub.CM (i.e., to do CM detection), and an operational amplifier 254 configure to receive a common-mode reference voltage V.sub.CMR at an non-inverting terminal (labeled by +) and the common-mode voltage V.sub.CM at an inverting terminal (labeled by ) and output a common-mode feedback voltage V.sub.CMFB to control the charge-down current I.sub.DN. In an alternative embodiment not shown in figure, the common-mode feedback voltage V.sub.CMFB to control the charge-down current I.sub.UP. In either case, the CM feedback network 250 adjusts a part of the charge pump 210 in a closed loop manner, so that a mean value of V.sub.X+ and V.sub.X will be approximately equal to V.sub.CMR. Common-mode feedback is well known to those of ordinary skill in the art and thus not described in detail here.

(25) In an embodiment, MOD 170 of FIG. 1A is embodied by a modulator 300 depicted in FIG. 3. Modulator 300 comprises a rounding operator (denoted by round()) 302, two unit delays (denoted by z.sup.1) 304 and 306, and three summing operators 301, 303, and 305. Unit delay 304 receives a rounding error e.sub.1 and outputs a delayed rounding error e.sub.1d. Summing operator 301 sums N.sub.MUL and e.sub.1d into a modified multiplication factor N.sub.MUL. Rounding operator 302 rounds N.sub.MUL into N.sub.DIV. Summing operator 303 subtracts N.sub.DIV from N.sub.MUL to generate e.sub.1. Summing operator 305 sums N.sub.C with N.sub.DIV and deducts N.sub.MUL to output an intermediate signal N.sub.CNEXT. Unit delay 306 receives N.sub.CNEXT and outputs N.sub.C. Rounding operator 302, summing operator 301 and 303, and unit delay 304 form a 1st order delta-sigma modulator, so that a mean value of N.sub.DIV equals N.sub.MUL. Summing operator 305 and unit delay 306 form an error accumulator, so that N.sub.C is equal to an accumulative sum of a difference between N.sub.DIV and N.sub.MUL. The difference between N.sub.DIV and N.sub.MUL is an instantaneous error of the 1st order delta-sigma modulator, and thus an error of the clock dividing operation of the clock divider 150. N.sub.C, is the accumulative sum of a difference between N.sub.DIV and N.sub.MUL, represents an accumulative error of the clock dividing operation of the clock divider 150 and thus a timing error of CK2. Digitally controlled timing adjustment circuit 160 corrects the timing error by adjusting the timing difference between CK2 and CK1 with an amount determined by N.sub.C.

(26) Now refer to FIG. 1F. In an alternative embodiment not shown in the figure, the fixed-delay circuit 161 and the digitally controlled variable-delay circuit 162 are swapped, and the digitally controlled variable-delay circuit 162 is controlled by G.sub.C and N.sub.C instead, where N.sub.C is an inversion of N.sub.C. In this alternative embodiment, the timing difference between CK3 and CK1 is fixed and the timing difference between CK4 and CK2 is variable and controlled by G.sub.C and N.sub.C, but the function remains the same and equation (1) is fulfilled.

(27) Still refer to FIG. 1F. The digitally controlled variable-delay circuit 162 belongs to a category of circuits known as digital-to-time converters, wherein a timing of an output clock is controlled by a digital signal. The digitally controlled variable-delay circuit 162 can be embodied by other digital-to-time converters, as long as the time difference between CK3 and CK1 is linearly dependent on both N.sub.C and G.sub.C.

(28) Now refer to FIG. 1A. PFD 110 is merely an exemplary timing detection circuit but not a limitation. An alternative timing detection circuit can be used instead, as long as the timing difference between CK4 and CK3 can be detected and properly represented by an associated timing error signal (such as S.sub.TE). Also, VCO 140 is merely an exemplary controllable oscillator circuit but not a limitation. An alternative controllable oscillator circuit can be used instead, as long as an output clock (such as CK5) can be generated and a frequency of the output clock can be controlled by a control signal (such as V.sub.CTL). Likewise, CP 120 and the subsequent LF 130 are an exemplary embodiment, but not a limitation, configured to filter a timing error signal (such as S.sub.TE) generated by a preceding timing detection circuit (such as PFD 110) into a control signal (such as V.sub.CTL). An alternative embodiment can be used instead, as long as the timing error signal can be filtered into a controllable signal for controlling a subsequent controllable oscillator circuit (such as VCO 140).

(29) In accordance with an embodiment of the present invention, a flow chart 400 of a method comprises: receiving a first clock and a clock multiplication factor (step 401); modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor (step 402); establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor (step 403); deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with a noise cancellation signal and a gain control signal (step 404); establishing a timing error signal by detecting a timing difference between the fourth clock and the third clock (step 405); filtering the timing error signal into an oscillator control signal (step 406); outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator (step 407); outputting the second clock by dividing down the fifth clock in accordance with the division factor (step 408); and adjusting the gain control signal in accordance with a correlation between the timing error signal and the noise cancellation signal (step 409).

(30) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.