Re-configurable Single Transformer Quadrature Voltage Controlled Oscillator

Abstract

A quadrature voltage controlled oscillator (QVCO). The QVCO includes a first node for providing a first quadrature signal, a second node for providing a second quadrature signal, a third node for providing a third quadrature signal, and a fourth node for providing a fourth quadrature signal. The QVCO further includes a first coil connected between the first node and the second node and a second coil connected between the third node and the fourth node. The first coil and second coil are positively magnetically coupled.

Claims

1. (canceled)

2. A quadrate voltage controlled oscillator, comprising: a first node for providing a first quadrature signal; a second node for providing a second quadrature signal; a third node for providing a third quadrature signal; a fourth node for providing a fourth quadrature signal; a first coil connected between the first node and the second node; a second coil connected between the third node and the fourth node, wherein the first coil and second coil are positively magnetically coupled; a first selectable conductive circuit coupled between the first node and the third node; and circuitry for disabling the first selectable conductive circuit and in response providing a differential signal between the first node and the second node; wherein the circuitry for disabling the first selectable conductive circuit disables the first selectable conductive circuit by disconnecting the first selectable conductive circuit from ground.

3. A quadrate voltage controlled oscillator, comprising: a first node for providing a first quadrature signal; a second node for providing a second quadrature signal; a third node for providing a third quadrature signal; a fourth node for providing a fourth quadrature signal; a first coil connected between the first node and the second node; a second coil connected between the third node and the fourth node, wherein the first coil and second coil are positively magnetically coupled; a first selectable conductive circuit coupled between the first node and the third node; a second selectable conductive circuit coupled between the second node and the fourth node; and selection circuitry for disabling the first and second selectable conductive circuits and in response providing a first differential signal between the first node and the second node and a second differential signal between the third node and the fourth node, wherein the first differential signal and the second differential signal are in phase with respect to one another; wherein the circuitry for disabling the first and second selectable conductive circuits disables the first and second selectable conductive circuits by disconnecting the first and second selectable conductive circuits from ground.

4. The oscillator of claim 3 and wherein the selection circuitry is further for enabling the first and second selectable conductive circuits and in response providing the first quadrature signal at the first node, the second quadrature signal at the second node, the third quadrature signal at the third node, and the fourth quadrature signal at the fourth node.

5. The oscillator of claim 4 wherein each of the first, second, third, and fourth selectable conductive circuits comprises a respective additional transistor having a gate coupled to the selection circuitry.

6-11. (canceled)

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0027] FIG. 1 illustrates an electrical schematic of a prior art source coupled QVCO.

[0028] FIG. 2 illustrates an electrical schematic of a prior art drain-gate coupled QVCO.

[0029] FIG. 3 illustrates an electrical schematic of a prior art drain-source coupled QVCO.

[0030] FIG. 4 illustrates an electrical schematic of a preferred embodiment QVCO.

[0031] FIG. 5 illustrates a timing diagram of the in-phase and quadrature signals of the QVCO of FIG. 4.

[0032] FIG. 6A illustrates an exploded perspective view of two inductors included in a preferred embodiment QVCO.

[0033] FIG. 6B illustrates a cross-sectional view of two inductors included in a preferred embodiment QVCO.

DETAILED DESCRIPTION OF EMBODIMENTS

[0034] FIGS. 1 through 3 were described above in the Background of the Invention section of this document, and the reader is assumed familiar with the principles of that discussion.

[0035] FIG. 4 illustrates a schematic of a preferred embodiment quadrature voltage controlled oscillator (QVCO) shown generally at 200. QVCO 200 includes bias control circuitry 202 that may be constructed according to known principles for biasing a QVCO and more particularly for biasing transistors with QVCO 200, as further explored below. QVCO 200 also includes four nodes 204, 206, 208, and 210, each for providing a respective in-phase or quadrature signal, namely, I+, Q+, Q, and I, as further appreciated below.

[0036] QVCO 200 includes two inductors 212 and 214 that may be a single coil C.sub.1 with an intermediary or center tap, and it also includes two additional inductors 216 and 218 that may be a single coil C.sub.2, also with an intermediary or center tap. Coil C.sub.1 is connected between nodes 204 and 206, and coil C.sub.2 is connected between nodes 208 and 210. The center tap of each of coils C.sub.1 and C.sub.2 is connected to a fixed voltage potential, shown as V.sub.DD. Coils C.sub.1 and C.sub.2 are also inductively or magnetically coupled together as shown in FIG. 4 using inductor dot convention. Unlike the various prior art QVCO descriptions set forth earlier, however, notably in FIG. 4 the dot convention demonstrates a positive (or additive) electromagnetically coupling factor (i.e., current in opposing directions) as between coils C.sub.1 and C.sub.2. In any event, apart from this change in polarity, again the electromagnetic coupling is achieved preferably by locating the inductors within a proximity to one another, with the distance of this proximity or other magnetically coupling technique being ascertainable by one skilled in the art.

[0037] QVCO 200 also includes various symmetric circuits, referred to herein as cross-coupled conduction circuits, coupled between pairings of the four signal nodes of QVCO 200. Specifically, a first cross-coupled conduction circuit XC.sub.1 includes an nMOS transistor 220 having its drain connected to node 204 and its gate connected to node 206, an nMOS transistor 222 having its drain connected to node 206 and its gate connected to node 204, with the sources of both nMOS transistor 220 and nMOS transistor 222 connected to a drain on an nMOS transistor 224, which has its source connected to ground and receives a bias signal, BIAS2, at its gate, from bias control circuitry 202. A second cross-coupled conduction circuit XC.sub.2 includes an nMOS transistor 226 having its drain connected to node 208 and its gate connected to node 210, an nMOS transistor 228 having its drain connected to node 210 and its gate connected to node 208, with the sources of both nMOS transistor 226 and nMOS transistor 228 connected to a drain of an nMOS transistor 230, which has its source connected to ground and receives the bias signal, BIAS2, at its gate, from bias control circuitry 202. A third cross-coupled conduction circuit XC.sub.3 includes an nMOS transistor 232 having its drain connected to node 204 and its gate connected to node 208, an nMOS transistor 234 having its drain connected to node 208 and its gate connected to node 204, with the source of both nMOS transistor 232 and nMOS transistor 234 connected to a drain of an nMOS transistor 236, which has its source connected to ground and receives a bias signal, BIAS1, at its gate, from bias control circuitry 202. A fourth cross-coupled conduction circuit XC.sub.4 includes an nMOS transistor 238 having its drain connected to node 206 and its gate connected to node 210, an nMOS transistor 240 having its drain connected to node 210 and its gate connected to node 206, with the source of both nMOS transistor 238 and nMOS transistor 240 connected to a drain of an nMOS transistor 242, which has its source connected to ground and receives the bias signal, BIAS1, at its gate, from bias control circuitry 202.

[0038] The operation of QVCO 200 is now described. In general, QVCO 200 is re-configurable by the selective application of BIAS1 and BIAS2 from bias control circuitry 202. More particularly, if only BIAS2 is applied (or likewise, if only BIAS1 is applied), then QVCO 200 operates in a differential mode. In the differential mode for the instance when only BIAS2 is applied, a first antiphase signal appears between nodes 204 and 206, while a second antiphase signal, in phase with the first antiphase signal, appears between nodes 208 and 210. Thus, for a device (e.g., a receiver) that requires only an oscillating signal, the differential mode of QVCO 200 may be selected and the oscillating signal provided as between nodes 204 and 206, or as between nodes 208 and 210. In addition, however, if both BIAS2 and BIAS1 are simultaneously applied, then QVCO 200 operates in a quadrature mode, where a first set of antiphase signals occurs between nodes 204 and 210, a second set of antiphase signals occurs between nodes 206 and 208, and the first and second antiphase signal sets are 90 degrees apart, that is, they are locked in quadrature. Thus, the quadrature mode also may be selected for a device that requires such signals (e.g., QPSK transceiver). Thus, the selective assertion of BIAS1 or BIAS2, or both BIAS1 and BIAS2, provide a single/dual bias control allowing for low-frequency based IQ phase alignment and tuning. Note also therefore that such BIAS control provides on the fly reconfiguration of the oscillation using benign and non-RF invasive bias-control knobs, between the two modes of differential and quadrature. Moreover, either the single or dual application of either or both biases allows for low frequency based IQ phase alignment and tuning. Each of these modes is separately discussed below.

[0039] In the differential mode of operation of QVCO 200, recall that bias control circuitry 202 asserts BIAS2, while leaving BIAS1 unasserted. With BIAS1 unasserted, the conductive paths in third cross-coupled conduction circuit XC.sub.3 and fourth cross-coupled conduction circuit XC.sub.4 are disabled, while with BIAS2 asserted, the conductive paths in first cross-coupled conduction circuit XC.sub.1 and second cross-coupled conduction circuit XC.sub.2 are enabled. In response to the latter, therefore, an oscillatory path is enabled corresponding to each of the first cross-coupled conduction circuit XC.sub.1 and the second cross-coupled conduction circuit XC.sub.2. Specifically, in connection with the first cross-coupled conduction circuit XC.sub.1, current is drawn through nMOS transistor 224, thereby enabling in effect an oscillating circuit with respect to coil C.sub.1 and nMOS transistors 220 and 222. At the same time, in connection with the second cross-coupled conduction circuit XC.sub.2, current is drawn through nMOS transistor 230, thereby enabling in effect an oscillating circuit with respect to coil C.sub.2 and nMOS transistors 226 and 228. Given the positive coupling as between coil C.sub.1 and coil C.sub.2 (i.e., relative polarity shown by dot convention), however, each of these two oscillators oscillates in phase with the other. As a result, with respect to the first cross-coupled conduction circuit XC.sub.1, the signals at nodes 204 and 206 will oscillate in an antiphase manner with respect to one another, and with respect to the second cross-coupled conduction circuit XC.sub.2, the signals at nodes 208 and 210 will oscillate in an antiphase manner with respect to one another, but both sets of signals (i.e., one at nodes 204 and 206, the other at nodes 210 and 208) will be in phase with respect to each other.

[0040] In the quadrature mode of operation of QVCO 200, recall that bias control circuitry 202 asserts both BIAS1 and BIAS2. As a result and as now discussed, each common drain node 204, 206, 208, and 210 provides a respective quadrature signal of I+, Q+, Q, and I. Specifically, with BIAS2 asserted, the conductive paths described in the previous paragraph are again enabled. In addition, however, with BIAS1 asserted, third cross-coupled conduction circuit XC.sub.3 and fourth cross-coupled conduction circuit XC.sub.4 are also both enabled. In this regard, therefore, note that each of the oscillating circuits are now no longer solely driven by their own respective voltages, but the signals from one oscillating circuit are also injected into the other, and vice versa. For example, consider node 208, which presents the Q signal. The conductivity of the third cross-coupled conduction circuit XC.sub.3, provides an additional conductive path through nMOS transistors 232 and 234, whereby the signal at node 204 is injected into node 208; likewise with the conductive path, the signal at node 208 is injected into node 204. Similar observations may be made with respect to the fourth cross-coupled conduction circuit XC.sub.4. Particularly, as it is enabled by the asserted BIAS1 signal, it provides a conductive path between node 210 (providing I), through nMOS transistors 240 and 38, to node 206 (providing Q+).

[0041] Given the preceding, simulations confirm that in the quadrature mode the conductive paths provided by all cross-coupled conduction circuits will quadrature lock the four common drain nodesbecause the LC characteristics of each of coils C.sub.1 and C.sub.2 and the respective capacitances of the various transistors through which a conductive path is formed, then the currents flowing through those LC tanks must have equal (assuming matching components) magnitude, thereby imposing a 90 degree phase shift as between a given common drain connected node and the drain of each other transistor to which the common drain connected node is connected to that other transistor's respective gate. As a first example, assume node 210 (presenting I), at the drain of nMOS transistor 228, and at a time t.sub.0, is at a 180 degree phase shift. That same drain connected node 210 is connected to the gate of nMOS transistor 238, so node 206 (presenting Q+) at the drain of the latter nMOS transistor 238 is shifted 90 degrees relative to common drain connected node 210, and so node 206 is at 270 degrees (i.e., +90 degrees relative to node 210). Similarly, that same drain connected node 210 of nMOS transistor 228 is connected to the gate of nMOS transistor 226, so node 208 (presenting Q) at the drain of the latter nMOS transistor 226 is shifted 90 degrees relative to common drain connected node 210, and so node 208 is at 90 degrees (i.e., 90 degrees relative to node 210). As a second example, assume node 204 (presenting I+), at the drain of nMOS transistor 220, and at time t.sub.0, is at a 0 degree phase shift. That same drain connected node 204 is connected to the gate of nMOS transistor 222, so node 206 (presenting Q+) at the drain of the latter nMOS transistor 222 is shifted 90 degrees relative to common drain connected node 204, and so node 206 is at 270 degrees (i.e., 90 degrees relative to node 204). Similarly, that same drain connected node 204 of nMOS transistor 232 is connected to the gate of nMOS transistor 234, so node 234 (presenting Q) at the drain of the latter nMOS transistor 234 is shifted 90 degrees relative to common drain connected node 204, and so node 207 is at 90 degrees (i.e., +90 degrees relative to node 204). Given the preceding examples, one skilled in the art may trace the other comparable conductive paths in QVCO 200 in the quadrature mode, that is, with both BIAS1 and BIAS2 asserted, which will confirm the relative timing of the four common drain connected nodes, which timing is further illustrated by way of example in FIG. 5.

[0042] FIG. 6A illustrates a perspective exploded view, and FIG. 6B a side cross-sectional view, of a configuration in which each of inductor coils C.sub.1 and C.sub.2 may be formed in connection with well-known semiconductor and integrated circuit fabrication processes. In this preferred embodiment, each inductor coil is generally a same shape and may be formed so that a majority of the metal for the inductor is positioned in a different respective metal layer in a semiconductor process. As shown in the exploded view of FIG. 5A, therefore, in the metal layers of a semiconductor process, coils C.sub.1 and C.sub.2 may be formed from metal, one above the other; this is also shown by way of cross-section in FIG. 6B, where intermediate (e.g., insulating) layers IL are formed between the inductors and as between another layer (not shown for simplification). Given the shape and orientation in FIGS. 6A and 6B, note that in two dimensions (e.g., from a top-down view), therefore, the shape and borders of coil inductors C.sub.1 and C.sub.2 are vertically aligned, so that the area consumed by the device in those two dimensions is no greater than for a prior art single inductor device. Moreover, note further that the preferred embodiment of FIG. 4 also implements a QVCO with a considerably reduced amount of coils/inductors as compared to the prior art approaches described in the Background of the Invention section of this document. This gives rise to another preferred embodiment benefit in that typically inductors consume a considerable amount of two-dimensional area, particularly relative to the rest of the circuitry required to implement a QVCO (and related circuitry). Thus, the preferred embodiment FIG. 4 schematic may be achieved via FIGS. 6A and 6B with its two coils in a same two-dimensional space, by aligning the coils the third dimension (e.g., vertically) in line with the other inductors. Moreover, even if the two coils of the FIG. 4 preferred embodiment are implemented in a same layer, they still consume far less area than a prior art approach that required more inductors in a same layer.

[0043] From the above, the preferred embodiments are shown to provide a QVCO with improvements over the art. In a preferred embodiment, one improvement permits a two mode oscillator, with one (or a pair of) oscillating signal in a differential mode and quadrature signals in a quadrature mode. Another improvement, therefore, allows reduced power consumption and area when the QVCO is operated in the differential mode, as a single device may be integrated and used during the times when only a differential signal is needed. As still another improvement, the preferred embodiment achieves the quadrature signals with only two coils, drastically improving the amount of device size needed to implement the device. Thus, the preferred embodiments are demonstrated to have numerous benefits, and still others will be further determined by one skilled in the art. Still further, while various alternatives have been provided according to the disclosed embodiments, still others are contemplated and yet others can ascertained by one skilled in the art. Given the preceding, therefore, one skilled in the art should further appreciate that while some embodiments have been described in detail, various substitutions, modifications or alterations can be made to the descriptions set forth above without departing from the inventive scope, as is defined by the following claims.