TIME-OF-FLIGHT DETECTION PIXEL

Abstract

A time-of-flight detection pixel includes a photosensitive area including a first doped layer and a charge collection area extending in the first doped layer. At least two charge storage areas extend from the charge collection area, each including a first well more heavily doped than the charge collection area and separated from the charge collection area by a first portion of the first doped layer which is coated with a gate. Each charge storage area is laterally delimited by two insulated conductive electrodes, extending parallel to each other and facing each other. A second heavily doped layer of opposite conductivity coats the pixel except for at each portion of the first doped layer coated with the gate.

Claims

1. A time-of-flight detection pixel, comprising: a photosensitive area comprising a first doped layer of a first conductivity type; a charge collection area extending in the first doped layer and being more heavily doped of the first conductivity type than the first doped layer; at least two charge storage areas extending from the charge collection area and each comprising a first well more heavily doped of the first conductivity type than the charge collection area and separated from said charge collection area by a first portion of the first doped layer coated with a first gate, each charge storage area being laterally delimited by two parallel insulated conductive electrodes facing each other.

2. The pixel of claim 1, further comprising a second heavily-doped layer of a second conductivity type coating the photosensitive area, the charge collection area and the first well.

3. The pixel of claim 1, wherein the first doped layer is supported by a doped semiconductor substrate of the second conductivity type.

4. The pixel of claim 1, wherein the charge collection area extends in doped fingers of the first conductivity type, coated with the second heavily-doped layer, and extending in the photosensitive area, the doped fingers being more heavily doped than the first doped layer and more lightly doped than or of a same doping level as the charge collection area.

5. The pixel of claim 1, wherein the charge collection area is arranged in a central portion of the photosensitive area.

6. The pixel of claim 1, further comprising, under each first gate, a doped intermediate area of the first conductivity type interposed between the first portion and the first well, the doped intermediate area being more heavily doped than the first portion and more lightly doped than the first well.

7. The pixel of claim 1, further comprising a region more heavily doped of the first conductivity type than the charge collection area, configured to be coupled to a reference potential, and separated from the charge collection area by a second portion of the first doped layer coated with a second gate.

8. The pixel of claim 1, further comprising, for each storage area, a sense area more heavily doped of the first conductivity type than the first well, the storage area extending all the way to the sense area and being separated from the sense area by a third portion of the first doped layer coated with a third gate.

9. The pixel of claim 1, further comprising, for each storage area, at least one memory area extending from the storage area and comprising a second well more heavily doped of the first conductivity type than the first well, coated with the second heavily-doped layer, and separated from the first well by a third portion of the first layer coated with a third gate, the memory area being laterally delimited by two parallel insulated conductive electrodes facing each other.

10. The pixel of claim 9, comprising two storage areas each of which is associated with two memory areas.

11. The pixel of claim 9, further comprising, for each memory area, a sense area more heavily doped of the first conductivity type than the second well, the memory area extending all the way to the sense area and being separated from the sense area by a fourth portion of the first doped layer coated with a fourth gate.

12. The pixel of claim 1, wherein each sense area is electrically connected to a same terminal of a read circuit.

13. The pixel of claim 1, wherein said first gate is configured to receive a signal having a first potential to allow or forbid a charge transfer from the charge collection area to the storage area.

14. The pixel of claim 8, wherein said third gate is configured to receive a signal having a second potential to allow or forbid a charge transfer from the storage area to the sense area.

15. The pixel of claim 11, wherein the third gate is configured to receiving a signal having a second potential to allow or forbid a charge transfer from the storage area to the memory area, and wherein the fourth gate is configured to receive a signal having a third potential to allow or forbid a charge transfer from the memory area to the sense area.

16. The pixel of claim 1, further comprising a second heavily-doped layer of a second conductivity type coating the pixel except for each portion of the first doped layer coated with the first gate.

17. An image sensor, comprising: an array of pixels associated with a source of emission of modulated light, and a circuit configured to synchronize source and control potentials applied to gates of transistors of each pixel in the array, wherein each pixel comprises: a photosensitive area comprising a first doped layer of a first conductivity type; a charge collection area extending in the first doped layer and being more heavily doped of the first conductivity type than the first doped layer; and at least two charge storage areas extending from the charge collection area and each comprising a first well more heavily doped of the first conductivity type than the charge collection area and separated from said charge collection area by a first portion of the first doped layer coated with a first gate, each charge storage area being laterally delimited by two parallel insulated conductive electrodes facing each other.

18. The image sensor of claim 17, further comprising a second heavily-doped layer of a second conductivity type coating the pixel except for each portion of the first doped layer coated with the first gate.

19. The image sensor of claim 17, further comprising a second heavily-doped layer of a second conductivity type coating the photosensitive area, the charge collection area and the first well.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, wherein:

[0023] FIG. 1 is a top view schematically showing an example of a TOF sensor;

[0024] FIG. 2 shows an example of a TOF pixel circuit;

[0025] FIG. 3 is a timing diagram illustrating a control mode of the TOF pixel of FIG. 2;

[0026] FIGS. 4A to 4C schematically show an embodiment of a TOF pixel of the type in FIG. 2;

[0027] FIG. 5 is a simplified cross-section view of an alternative embodiment of the TOF pixel of FIGS. 4A to 4C;

[0028] FIGS. 6A and 6B schematically show another alternative embodiment of the TOF pixel of FIGS. 4A to 4C; and

[0029] FIGS. 7A to 7D schematically shows another embodiment of a TOF pixel.

DETAILED DESCRIPTION

[0030] The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed.

[0031] In the following description, terms high, low, left, right, under, over, vertical, and upper refer to the concerned elements in the corresponding drawings. Unless otherwise specified, expressions substantially, approximately, and in the order of mean to within 10%, preferably to within 5%.

[0032] FIG. 1 is a simplified top view of an example of a TOF sensor. Sensor 1 comprises an array 3 of TOF pixels, for example, an array of 1,000 rows by 1,000 columns. Array 3 is associated with a row decoder 7 and with a column decoder 9. Row decoder 7 delivers signals 11 enabling to select one or the other of the array rows. Column decoder 9 enables to read the information from the pixels of a selected row. Row decoder 7 and column decoder 9 are controlled by signals 13 delivered by a control and processing circuit 15. Control and processing circuit 15, for example, comprises a processor associated with one or a plurality of memories. Sensor 1 is associated with a light source 17 to illuminate a scene for which a three-dimensional image is desired to be obtained. Light source 17 is for example a laser having a wavelength which may be in the range from 500 to 1,000 nm. Light source 17 is connected to control and processing circuit 15 to synchronize the control signals applied to the TOF pixels of array 3 and light source 17.

[0033] In the following description, the case of a sensor 1 where light source 17 emits a sinusoidal signal L.sub.E having a frequency which may be in the range from 20 to 100 MHz, for example, 25 MHz, is considered. For each pixel, phase-shift between the emitted light signal L.sub.E and the light signal L.sub.R received by this pixel is determined. The distance separating the pixel from its conjugate point is then determined from phase shift .

[0034] FIG. 2 shows an example of a TOF pixel circuit.

[0035] The TOF pixel comprises a photosensitive element (photodiode PD) having a terminal connected to a node 21 and having its other terminal connected to a low reference potential, for example, the ground. Node 21 is coupled to sense node SN via three identical assemblies S1, S2, and S3 connected in parallel between nodes 21 and SN. Each assembly S.sub.i, with i equal to 1, 2, or 3 in this example, comprises a transfer N-channel MOS transistor, Tmem.sub.i, a charge storage area mem.sub.i, and a sense N-channel MOS transistor, Tsn.sub.i. The source of transistor Tmem.sub.i is connected to node 21, and the drain of transistor Tmem.sub.i is connected to a terminal of storage area mem.sub.i. Transistor Tmem.sub.i is controlled by a signal Vmem.sub.i applied to its gate. The source of transistor Tsn.sub.i is connected to the other terminal of storage area mem.sub.i, and the drain of transistor Tsn.sub.i is connected to sense node SN. Transistor Tsn.sub.i is controlled by a signal Vsn.sub.i applied to its gate. Examples of storage areas mem.sub.i will be given hereafter.

[0036] The TOF pixel is associated with a sense device which may be common to a plurality of pixels, for example, four pixels. The sense device comprises a precharge N-channel MOS transistor, Tres, an N-channel MOS transistor assembled as a follower source, Tsuiv, and a selection N-channel MOS transistor, Tsel, connected as shown. Sense node SN is coupled to a high reference potential, for example, power supply potential Vdd, by transistor Tres, the latter being controlled by a signal Vres applied to its gate. Sense node SN is also coupled to the gate of transistor Tsuiv having its drain coupled to the high reference potential, and having its source coupled to an output line 23 of the pixel circuit via transistor Tsel, transistor Tsel being controlled by a signal Vsel applied to its gate.

[0037] In this example, the TOF pixel further comprises an N-channel MOS transistor, Tres.sub.PD, for resetting photosensitive element PD. The source of transistor Tres.sub.PD is connected to node 21 and the drain of transistor Tres.sub.PD is connected to high potential Vdd. Transistor Tres.sub.PD is controlled by a signal Vres.sub.PD applied to its gate.

[0038] To determine the phase shift between the emitted light signal L.sub.E and the light signal L.sub.R received by the pixel, signal L.sub.R is sampled by transferring, successively and at regular intervals, charges photogenerated in the photosensitive element towards storage areas mem.sub.1, and then mem.sub.2, and finally mem.sub.3. The total duration to carry out these three successive transfers is equal to a period of signals L.sub.E and L.sub.R. Further, these three successive transfers are repeated a large number of times, for example, at least 100,000 times. The charges stored in the storage areas are then read by transferring, to node SN, the charges from area mem.sub.1, and then from area mem.sub.2, and finally from area mem.sub.3.

[0039] An embodiment of the TOF pixel of FIG. 2 will now be described in further detail in relation with FIG. 3.

[0040] FIG. 3 is a timing diagram of light signal L.sub.E emitted by light source 17 associated with sensor 1, of light signal L.sub.R received by the TOF pixel, and of digital signals Vres.sub.PD, Vres, Vmem.sub.i, Vsn.sub.i, and Vsel. By default, signals Vres.sub.PD, Vmem.sub.i, Vsn.sub.i, and Vsel are at a low level and signal Vres is at a high level.

[0041] A resetting of photosensitive element PD is first performed by setting transistor Tres.sub.PD to the on state (signal Vres.sub.PD in the high state) between times t.sub.0 and t.sub.1. An integration cycle of the pixel then starts and is synchronized on signal L.sub.E.

[0042] During the integration cycle, the charges photogenerated in photosensitive area PD are transferred to storage areas mem.sub.i. To achieve this, transfer transistors Tmem.sub.i are each set to the on state in turn. More particularly, transistor Tmem.sub.1 is set to the on state (Vmem.sub.1 high) between times t.sub.2 and t.sub.3, transistor Tmem.sub.2 is set to the on state (Vmem.sub.2 high) between times t.sub.4 and t.sub.5, and transistor Tmem.sub.3 is set to the on state (Vmem.sub.3 high) between times t.sub.6 and t.sub.7. As previously indicated, these three transfers are then repeated a large number of times. All along the integration cycle, signal Vres is in the high state, transistor Tres is on, and the voltage of sense node SN is substantially equal to the high reference potential.

[0043] At the end of the integration cycle, from a time t10, the charges stored in each of storage areas mem.sub.i are read. To achieve this, sense transistors Tsn.sub.i are each in turn set to the on state, and the voltage level on node SN is measured and stored after each reading of the charges stored in a storage area mem.sub.i. More particularly, transistor Tsel is set to the on state (Vsel high) at time t.sub.10 and precharge transistor Tres is set to the off state (Vres low) at a time t.sub.11. Transistor Tsn1 is then set to the on state (Vsn1 high) between successive times t.sub.12 and t.sub.13, after which the sequence on Tres and Tsn is repeated by the application of a new precharge pulse on transistor Tres before the reading of the second sample, followed by a switching to the on state of transistor Tsn.sub.2 (Vsn.sub.2 high) between successive times t.sub.14 and t.sub.15, and, finally, this sequence is repeated a third time before the application of a pulse on Tres and the reading of the third sample when transistor Tsn.sub.3 is set to the on state (Vsn.sub.3 high) between successive times t.sub.16 and t.sub.17. First, second, and third voltage levels of node SN are measured and stored, respectively between times t.sub.13 and t.sub.14, between times t.sub.15 and t.sub.16, and between times t.sub.17 and a time t.sub.18. At time t.sub.18, signal Vsel is set to the low state and signal Vres is set back to the high state. A new integration cycle may then start.

[0044] In this embodiment, the first, second, and third measured voltage levels are representative of the charges stored, respectively, in storage area mem.sub.1, in storage area mem.sub.2, and in storage area mem.sub.3. In a preferred alternative embodiment, a resetting of sense node SN is provided after each reading of the charges stored in a storage area mem.sub.i. In this case, the first, second, and third voltage levels are representative of the charges stored in a single storage area, respectively mem.sub.1, mem.sub.2, and mem.sub.3.

[0045] These three voltage levels enable to determine phase shift between light signals L.sub.E and L.sub.R, and thus to deduce therefrom the distance separating the pixel from the point in the scene conjugate with the pixel.

[0046] Although an embodiment and a control mode of a TOF pixel circuit comprising three identical assemblies S.sub.i, phase shift between signals L.sub.E and L.sub.R may also be determined by using a TOF pixel comprising more than three assemblies S.sub.i, for example, four assemblies S.sub.i.

[0047] As an example, the duration of a transfer towards a storage area mem.sub.i is in the range from 5 to 30 ns. The duration separating two transfers to a same storage area mem.sub.i is for example 40 ns when the frequency of these signals is 25 MHz. In this case, the duration of an integration cycle may be approximately 10 ms when the charge transfers to each of storage areas mem.sub.i are performed 250,000 times each. The duration of a charge transfer from a storage area mem.sub.i to sense node SN is for example in the range from 1 to 10 s.

[0048] In a pixel, within a few nanoseconds, few charges are photogenerated in photosensitive element PD, for example, from 0 to 10 charges. Such charges should be integrally transferred to a storage area mem.sub.i. In particular, no charge should remain blocked in photosensitive element PD or in the channel of the corresponding transistor Tmem.sub.i.

[0049] An embodiment of a TOF pixel allowing a complete transfer of the charges photogenerated in photosensitive area PD towards storage areas mem.sub.i will now be described in relation with FIGS. 4A to 4C.

[0050] FIGS. 4A to 4C schematically show an embodiment of a TOF pixel, FIG. 4A being a top view of this pixel and FIGS. 4B and 4C being cross-section views respectively along planes BB and CC of FIG. 4A. In this embodiment, a TOF pixel 40 comprises four assemblies S.sub.i, with i equal to 1, 2, 3, or 4. Each assembly S.sub.i comprises a transfer transistor Tmem.sub.i, a storage area mem.sub.i, and a sense transistor Tsn.sub.i.

[0051] TOF pixel 40 comprises a photosensitive area PD comprising, on a P-type doped semiconductor substrate 41, an N-type doped layer 43, of doping level N.sub.1. Layer 43 is coated with a heavily-doped P-type layer 45 (P.sup.+).

[0052] TOF pixel 40 also comprises, in layer 43, an N-type doped charge collection area 47, of doping level N.sub.2 higher than N.sub.1, collection area 47 being coated with layer 45. Charge collection area 47 extends in fingers 49 coated with layer 45 and extending in layer 43. Fingers 49 are N-type doped, of same doping level N.sub.2 as collection area 47.

[0053] Each of storage areas mem.sub.i of the pixel comprises an N-type doped well 51, having a doping level N.sub.3 higher than N.sub.2. Each well 51 is coated with P.sup.+ layer 45, extends through all or part of the thickness of layer 43, and may penetrate into substrate 41. Each storage area mem.sub.i is laterally delimited by two insulated vertical electrodes 53 which extend from the upper surface of the pixel and penetrate into substrate 41 down to a depth at least equal to that of well 51. Electrodes 53 comprise a conductive material 55, for example, doped polysilicon, bordered with a layer of an insulating material 57, for example, silicon oxide. Each storage area mem.sub.i extends between charge collection area 47 and a heavily-doped N-type sense area SN.sub.i (N.sup.+). Sense areas SN.sub.i are preferably electrically connected to one another and correspond to sense node SN described in relation with FIG. 2. Each storage area mem.sub.i is separated from collection area 47 by a portion 59 of layer 43 at the level of which layer 43, instead of being coated with P.sup.+ layer 45, is coated with gate 61 of the corresponding transfer transistor Tmem.sub.i, gate 61 being insulated from layer 43 by a gate insulator layer 63. Each storage area mem.sub.i is separated from the corresponding sense area SN.sub.i by a portion 65 of layer 43 at the level of which layer 43, instead of being coated with P.sup.+ layer 45, is coated with gate 67 of sense transistor Tsn.sub.i, gate 67 being insulated from layer 43 by a gate insulator layer 69.

[0054] In this embodiment, four storage areas mem.sub.i and four fingers 49 are regularly arranged around charge collection area 47, the latter being arranged in a substantially central portion of photosensitive area PD. As can be seen in FIG. 4A, storage areas mem.sub.i may be elongated, for example, of rectangular shape, each area mem.sub.i then extending widthwise between two parallel vertical insulated electrodes 53 facing each other. Although this has not been shown herein, each of assemblies S.sub.i is coated with a screen opaque to light so that no charge can be photogenerated in storage areas mem.sub.i. Further, photosensitive area PD is delimited by insulating structures, not shown, for example, by insulated vertical electrodes similar to electrodes 53.

[0055] In operation, substrate 41 is connected to a low reference potential, for example, the ground. Insulated electrodes 53 are connected to a potential smaller than or equal to 0 V, for example, 2 V, whereby holes accumulate along their walls. Such a hole accumulation enables to decrease dark currents and, further, to electrically connect substrate 41 to P.sup.+ layer 45 which then is at the low reference potential. Photosensitive area PD and storage areas mem.sub.i thus correspond to so-called pinned diodes. Further, doping levels N.sub.1, N.sub.2, and N.sub.3 are selected so that, in the absence of illumination, the diodes corresponding to photosensitive area PD and to storage areas mem.sub.i are fully depleted, and that the maximum electrostatic potential trough in wells 51 is higher than that in collection area 47 and fingers 49, which is itself higher than that in layer 43 of photosensitive area PD.

[0056] When the pixel receives light from a scene, electron-hole pairs are photogenerated in photosensitive area PD. The holes are drained off towards substrate 41 and the electrons are attracted into layer 43 of photosensitive area PD. Due to the fact that the electrostatic potential is higher in collection area 47 and in fingers 49 than in layer 43, electrons are attracted into fingers 49 and are drained towards charge collection area 47.

[0057] The electron transfer from charge collection area 47 to a storage area mem.sub.i is performed bulkwise rather than at the surface. In other words, the transferred electrons flow from N.sub.2 well 47 to N.sub.3 well 51 without reaching the interface between gate insulator layer 63 and layer 43, which advantageously enables to prevent such electrons from recombining with defects of this interface. Thus, the electrons stored in storage area 47 are effectively all transferred to storage area mem.sub.i.

[0058] Advantageously, the surface area of pixel 40 may be small, for example, in the order of 3 m by 3 m. This particularly results from the fact that storage areas mem.sub.i may have small dimensions, for example, a width of approximately 0.2 m and a length of approximately 1 m.

[0059] Although fingers 49 of same doping level as the charge collection area have been described, in alternative embodiments, the doping level of fingers 49 may be between doping levels N.sub.1 and N.sub.2. For each finger 49, this doping level may be constant or may increase as it is come closer to charge collection area 47. In this last case, the electrons will be more efficiently drained towards the charge collection area.

[0060] As an example, substrate 41 is made of silicon. Layer 43 may be formed by epitaxy on substrate 41 and be N-type doped in situ to a doping level N.sub.1. The thickness of layer 43 is for example in the order of 500 nm. Doping level N.sub.1 is for example in the range from 510.sup.15 to 10.sup.17 at/cm.sup.3, for example, 510.sup.16 at/cm.sup.3. Charge collection area 47 and fingers 49 may be formed by implantation of dopant atoms in layer 43. The thickness of layer 47 and of fingers 49 may be in the order of 300 nm. The collection area may have a surface area in the order of 500 nm*500 nm and fingers 49 may have a length in the order of 200 nm. Doping level N.sub.2 is for example in the range from 510.sup.16 to 510.sup.17 at/cm.sup.3, for example, 210.sup.17 at/cm.sup.3. Well 51 may be formed by implantation of dopant atoms in layer 43, and the dopant atoms may penetrate all the way into substrate 41. The thickness of well 51 is for example in the order of 0.5 m. Doping level N.sub.3 is for example in the range from 1 to 810.sup.17 at/cm.sup.3, for example, 410.sup.17 at/cm.sup.3. The length of gates 61 and/or 67 may be approximately 300 nm. P.sup.+ layer 45 is for example formed by implantation of dopant atoms and may have a thickness of approximately 100 nm. The doping level of layer 45 may be in the range from 210.sup.17 to 10.sup.19 at/cm.sup.3, for example, 510.sup.18 at/cm.sup.3. Sense areas SN.sub.i may be formed by implantation of dopant atoms in layer 43. Doping level N.sup.+ of sense areas SN.sub.i 45 may be in the range from 210.sup.20 to 10.sup.21 at/cm.sup.3, for example, 6.Math.10.sup.21 at/cm.sup.3. Signal Tmem.sub.i is for example in the range from 2 to 0 V in the low state, and from 0 to 3.6 V in the high state. Signal Vsn.sub.i is for example in the range from 2 to 0 V in the low state, and from 1 to 3.6 V in the high state.

[0061] FIG. 5, which corresponds to FIG. 4B, schematically shows an alternative embodiment of TOF pixel 40 of FIGS. 4A to 4C.

[0062] In this variation, a TOF pixel 400 thus comprises the same elements as TOF pixel 40 of FIGS. 4A to 4C, designated with the same reference numerals. Pixel 400 further comprises, under each gate 61, an intermediate N-type region 71, interposed between portion 59 and storage area mem.sub.i. Intermediate region 71 has a doping level N.sub.4 higher than N.sub.1 and lower than N.sub.3. As a result, the electrostatic potential in intermediate region 71 is higher than that in portion 59 and lower than that in well 51. This advantageously enables to avoid that, during an electron transfer from area 47 to an area mem.sub.i, electrons remain trapped under the gate of transistor Tmem.sub.i and can return into collection area 47.

[0063] FIGS. 6A and 6B schematically show another alternative embodiment of a TOF pixel of the type in FIG. 2, FIG. 6A being a top view of the pixel and FIG. 6B being a cross-section view along plane BB of FIG. 6A. In this alternative embodiment, a TOF pixel 50 comprises three assemblies S.sub.i, i being equal to 1, 2, or 3, and, further, a transistor Tres.sub.PD.

[0064] TOF pixel 50 is similar to TOF pixel 40 of FIGS. 4A to 4C, with the difference that assembly S.sub.4 of TOF pixel 40 is replaced with a transistor Tres.sub.PD for resetting photosensitive area PD. Transistor Tres.sub.PD comprises a gate 73 separated from layer 43 by a gate insulator layer 74. Gate 73 is arranged on a portion 75 of layer 43 extending between charge collection area 47 and a heavily-doped N-type region 77 (N.sup.+) forming the drain of transistor Tres.sub.PD and being intended to be connected to a high potential. In this example, N.sup.+ region 77 is laterally delimited, except on the side of the charge collection area, by an insulated vertical electrode 79 similar to insulated electrodes 53. It may be provided to replace electrode 79 with another insulating structure. Like each of assemblies S.sub.i, transistor Tres.sub.PD may be coated with a shield opaque to light. As an example, signal Vres.sub.PD applied to gate 73 of transistor Tres.sub.PD is in the range from 2 to 3.5 V in the high state.

[0065] Although an embodiment of a transistor Tres.sub.PD has been described, this transistor may have other forms. Further, transistor Tres.sub.PD may be used as an anti-blooming device by adapting the potentials applied to N.sup.+ area 77 and to the gate of transistor Tres.sub.PD.

[0066] In the previously-described pixels, the storage areas extend between the charge collection area of the photosensitive area and corresponding sense areas. In such pixels, the charges photogenerated in the photosensitive area are regularly transferred from the charge collection area to the storage areas to be accumulated therein. In another embodiment, a pixel comprising, in addition to the storage areas, memory areas similar to the storage areas, is provided. Each memory area is interposed between a storage area and a sense area, a same storage area being capable of being associated with a plurality of memory areas. Each storage area then extends between the charge collection area and the memory area(s) to which it is associated. In such a pixel, the photogenerated charges are regularly transferred from collection area 47 to the storage areas, and from the storage areas to the memory areas. Thus, while charges are being transferred to a storage area, charges previously stored in another storage area are transferred to a memory area associated with this other storage area. The provision of memory areas interposed between the storage areas and the sense areas allows an intermediate storage in the storage areas before the transfer to one of the memory areas. This particularly has the following advantages:

[0067] passage area between collection area 47 and transistor Tmem.sub.i easier to define to avoid narrowings in this area, which might degrade the charge transfer, and

[0068] possibility of reading from the collector with only two control signals, these two signals for example being sinusoids in phase opposition.

[0069] An embodiment of a TOF pixel 80 comprising memory areas interposed between the storage area and the sense areas will now be described in relation with FIGS. 7A to 7D. FIG. 7A is a top view of pixel 80, FIGS. 7B, 7C, and 7D being cross-section views respectively along planes BB, CC, and DD of FIG. 7A.

[0070] In this embodiment, TOF pixel 80 comprises two assemblies, each comprising a storage area mem.sub.i, with i equal to 1 or 2, associated with two memory areas mem.sub.i1 and mem.sub.i2, themselves associated with two sense areas SN.sub.i1 and SN.sub.i2 respectively. Each assembly comprises a first transfer transistor Tmem.sub.i allowing or blocking a charge transfer from the charge collection area to storage area mem.sub.i, two second transfer transistors Tmem.sub.i1 and Tmem.sub.i2 allowing or blocking a charge transfer from storage area mem.sub.i to memory areas mem.sub.i1 and mem.sub.i2, respectively, and two sense transistors Tsn.sub.i1 and Tsn.sub.i2 allowing or blocking a charge transfer from memory areas mem.sub.i1 and mem.sub.i2 to respective sense areas SN.sub.i1 and SN.sub.i2.

[0071] More particularly, TOF pixel 80 comprises photosensitive area PD comprising, on semiconductor substrate 41, layer 43 coated with P.sup.+ layer 45, and also comprises charge collection area 47 and fingers 49. Each of storage areas mem.sub.i comprises an N-type doped well 81 at a doping level N.sub.5 higher than N.sub.2, well 81 being coated with P.sup.+ layer 45. Each well 81 extends through all or part of the thickness of layer 43 and may penetrate into substrate 41. Each of storage areas mem.sub.i is laterally delimited by two insulated vertical electrodes 83 similar to previously-described electrodes 53. Each of memory areas mem.sub.i1 and mem.sub.i2 comprises an N-type doped well 85 at a doping level N.sub.6 higher than N.sub.5, well 85 being coated with P.sup.+ layer 45. Each well 85 extends through all or part of the thickness of layer 43 and may penetrate into substrate 41. Each of memory areas mem.sub.i1 and mem.sub.i2 is laterally delimited by two insulated vertical electrodes 87 similarly to insulated electrodes 53. In this example, each of storage areas mem.sub.i and of memory areas mem.sub.i1 and mem.sub.i2 is elongated, of rectangular shape, and extends widthwise between two corresponding parallel insulated electrodes facing each other. As shown in FIG. 7A, one of the two electrodes 87 delimiting a memory area mem.sub.i1 or mem.sub.i2 may correspond to an extension of an electrode 83 delimiting storage area mem.sub.i. Further, since, in this example memory areas mem.sub.i1 and mem.sub.i2 border the sides of photosensitive area PD (to the left and to the right in FIG. 7A), electrodes 87 delimiting memory areas mem.sub.i1 and mem.sub.i2 on the side of the photosensitive area may extend beyond the memory areas to delimit sides of photosensitive area PD (at the top and at the bottom of FIG. 7A) which are not bordered with the memory areas. Storage areas mem.sub.i and memory areas mem.sub.i1 and mem.sub.i2 are coated with a shield opaque to light, not shown. Each of sense areas SN.sub.i1 and SN.sub.i2 is heavily N-type doped (N.sup.+). Sense areas SN.sub.i1 and SN.sub.i2 are electrically connected to one another and form a sense node of pixel 80. As previously, a portion 89 of layer 43 separates each storage area mem.sub.i of charge collection area 47. Portion 89, instead of being coated with P.sup.+ layer 45, is coated with gate 91 of transfer transistor Tmem.sub.i, insulated from layer 43 by a gate insulator layer 93. Each memory area mem.sub.i1 and mem.sub.i2 is separated from the corresponding storage area mem.sub.i by a portion 95 of layer 43. Portion 95, instead of being coated with P.sup.+ layer 45, is coated with gate 97 of the corresponding transfer transistor Tmem.sub.i1 or Tmem.sub.i2, insulated from layer 43 by a gate insulator layer 99. Each sense area SN.sub.i1 and SN.sub.i2 is separated from the corresponding memory area mem.sub.i1 or mem.sub.i2 by a portion 101 of layer 43. Portion 101 of layer 43, instead of being coated with P.sup.+ layer 45, is coated with gate 103 of the corresponding sense transistor Tsn.sub.i1 or Tsn.sub.i2, insulated from layer 43 by a gate insulator layer 105. The structure of transistors Tmem.sub.i, Tmem.sub.i1, Tmem.sub.i2, Tsn.sub.i1, and Tsn.sub.i2 is similar to that of previously-described transistors Tmem.sub.i, whereby the charge transfers authorized by the transistors are performed bulkwise rather than surface-wise.

[0072] In operation, substrate 41 is connected to a low reference potential and insulated electrodes 83 and 87 are connected to a potential lower than or equal to 0 V. Doping levels N.sub.1, N.sub.2, N.sub.5, and N.sub.6 are selected so that, in the absence of illumination, photosensitive area PD and areas mem.sub.i, mem.sub.i1, and mem.sub.i2 correspond to fully-depleted pinned diodes, so that the maximum of the electrostatic well in wells 85 is higher than that in wells 81, and so that the maximum electrostatic potential trough in wells 81 is higher than in charge collection area 47 and in fingers 49.

[0073] As an example, the dimensions of the gates of the transistors of pixel 80 and of the storage and memory areas are substantially the same as those of the gates of the transistors and of the storage areas of previously-described pixels 40, 400, and 50. Further, wells 81 and 91 of pixel 80 may have thicknesses of the same order as those of wells 51 of pixels 40, 400, and 50. Doping level N.sub.5 may be in the range from 110.sup.17 at/cm.sup.3 to 410.sup.17 at/cm.sup.3, for example, 210.sup.17 at/cm.sup.3. Doping level N.sub.6 may be in the range from 410.sup.17 at/cm.sup.3 to 810.sup.17 at/cm.sup.3, for example, 410.sup.17 at/cm.sup.3.

[0074] Although a pixel 80 comprising two assemblies of a storage area associated with two memory areas has been described, the pixel may comprise more than two assemblies of a storage area associated with at least one memory area.

[0075] Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, an array of TOF pixels of the type of those previously described may be controlled according to a global shutter control mode or according to a rolling shutter control mode.

[0076] Further, it may be provided for array 3 of sensor 1 to comprise a plurality of groups of pixels, each group comprising a TOF pixel and pixels capable of detecting red, green, and blue light to obtain a three-dimensional color image of a scene.

[0077] The described embodiments are not limited to the specific examples of layout and configuration of the vertical electrodes shown in FIGS. 4A to 4C, 5, 6A, 6B, and 7A to 7D. Other layouts of vertical electrodes and/or a number of electrodes per pixel different from what has been shown may be provided. Further, although embodiments of pixels where photogenerated charges corresponding to electrons are detected, stored, and transferred have been described, it will be within the abilities of those skilled in the art to form similar pixels where the charges are holes, by inverting all conductivity types and by adapting the voltage levels applied to the various elements of these pixels.

[0078] Various embodiments with different variations have been described hereabove. It will be within the abilities of those skilled in the art to combine various elements of these various embodiments and variations without showing any inventive step. For example, an intermediate region 71 arranged under the gate of a transistor Tmem.sub.i has been described. An intermediate region may also be provided under the gates of transistors Tsn.sub.i, Tmem.sub.i, Tmem.sub.i1, Tmem.sub.i2, Tsn.sub.i1 and/or Tsn.sub.i2. This intermediate region will be arranged to border the N-type area or region towards which the charge transfer is performed, and will have a doping level higher than that of a layer 43 and lower than that of the area or region towards which this transfer is performed.

[0079] It may also be provided for a transistor for resetting photosensitive PD to be provided in a pixel of the type of that in FIGS. 7A to 7C. Further, in a pixel comprising no transistor for resetting the photosensitive element, such a resetting may be performed by controlling the pixel transistors to create a conductive path between the photosensitive element and a high potential, for example, potential Vdd.

[0080] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.