TIME-OF-FLIGHT DETECTION PIXEL

Abstract

A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

Claims

1. A time-of-flight detection pixel comprising a semiconductor substrate including: a photosensitive area comprising a first doped layer of a first conductivity type and a charge collection area of the first conductivity type more heavily doped than the first doped layer and extending through at least part of the first layer; at least two charge storage areas each comprising a well of the first conductivity type more heavily doped than the charge collection area and separated from said charge collection area at least by a first portion of the first layer, the first portion being covered by a first gate, each charge storage area being laterally delimited by two insulated conductive electrodes, parallel to and facing each other; and a second doped layer of a second conductivity type covering the charge collection area and the charge storage areas.

2. The pixel of claim 1, wherein each first portion of the first layer comprises a first intermediate area adjacent to the corresponding charge storage area, the first intermediate area being of the first conductivity type, more heavily doped than said first portion and less heavily doped than the well of said charge storage area.

3. The pixel of claim 1, wherein each charge storage area comprises a second intermediate area, interposed between the well of the charge storage area and the photosensitive area, the second intermediate area being of the first conductivity type, more heavily doped than the first portion and less heavily doped than the well.

4. The pixel of claim 1, wherein the photosensitive area is square-shaped in top view, and each charge storage area extends along an edge of the photosensitive area.

5. The pixel of claim 1, wherein the photosensitive area is substantially square-shaped in top view, and each charge storage area extends from an edge of the photosensitive area, orthogonally to said edge.

6. The pixel of claim 1, wherein the first layer is positioned on a portion of the semiconductor substrate of the second conductivity type and having a doping level which decreases as the distance to the first layer decreases.

7. The pixel of claim 1, further comprising a reset area of the first conductivity type more heavily-doped than the charge collection area, and separated from the charge collection area by a second portion of the first layer covered by a second gate arranged on the photosensitive area.

8. The pixel of claim 1, wherein the first gates are arranged on the photosensitive area and the charge collection area comprises a central portion arranged substantially at a center of the photosensitive area, and arms extending from said central portion between the gates arranged on the photosensitive area.

9. The pixel of claim 1, further comprising, for each charge storage area, a sense area of the first conductivity type more heavily doped than the well, separated from the well by a third portion of the first layer covered by a third gate, the third portion being arranged beyond the photosensitive area.

10. The pixel of claim 1, wherein the gates arranged on the photosensitive area are made of materials transparent to wavelengths of a received periodic signal.

11. The pixel of claim 1, further comprising a screen opaque to light covers the pixel except for the photosensitive area.

12. The pixel of claim 1, wherein each first gate is configured to receive a signal configured to allow or forbid a charge transfer from the photosensitive area to the corresponding storage area.

13. The pixel of claim 1, wherein the semiconductor substrate is a semiconductor layer of semiconductor-on-insulator type.

14. An image sensor comprising the pixel array of claim 1, associated with a source emitting a periodic light signal, and a circuit configured for synchronizing said source and control potentials applied to the gates of transistors of each pixel.

15. A method of manufacturing a time-of-flight detection pixel comprising the successive steps of: forming pairs of insulated vertical electrodes parallel to and facing each other, each electrode pair laterally delimiting a storage area extending longitudinally from a photosensitive area; forming by implantation, in the photosensitive area, a first doped layer of a first conductivity type; on the photosensitive area, forming first gates on first portions of the first layer having the storage areas extending therefrom; in the photosensitive area, between the first gates, forming by implantation a charge collection area of the first type more heavily-doped than the first layer, the collection area having edges aligned with the first gates; in each storage area, forming by implantation a well of the first type more heavily-doped than the charge collection area; and on the storage areas and on the charge collection area, forming by implantation a second doped layer of the second type.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, wherein:

[0022] FIG. 1 is a top view schematically showing an example of a TOF sensor;

[0023] FIG. 2 shows an example of a TOF pixel circuit;

[0024] FIG. 3 is a timing diagram illustrating a control mode for the TOF pixel of FIG. 2;

[0025] FIGS. 4A to 4D schematically show an embodiment of a TOF pixel of the type in FIG. 2;

[0026] FIGS. 5A to 5D schematically illustrate the variation of the electrostatic potentials in various regions of the pixel of FIGS. 4A to 4D during charge transfer steps;

[0027] FIG. 6 schematically shows an alternative embodiment of the pixel of FIGS. 4A to 4D; and

[0028] FIG. 7 schematically shows another alternative embodiment of the pixel of FIGS. 4A to 4D.

DETAILED DESCRIPTION

[0029] The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and detailed.

[0030] In the following description, terms high, low, under, over, vertical, and upper refer to the concerned elements in the corresponding drawings. Unless otherwise specified, expressions substantially, approximately, and in the order of mean to within 10%, preferably to within 5%.

[0031] FIG. 1 is a simplified top view of an example of a TOF sensor. Sensor 1 comprises an array 3 of TOF pixels, for example, an array of 1,000 rows by 1,000 columns. Array 3 is associated with a row decoder (RD) 7 and with a column decoder (CD) 9. Row decoder 7 delivers signals 11 enabling to select one or the other of the array rows. Column decoder 9 enables to read the information from the pixels of a selected row. Row decoder 7 and column decoder 9 are controlled by signals 13 delivered by a control and processing circuit (CPC) 15.

[0032] Control and processing circuit 15 for example comprises a processor associated with one or a plurality of memories. Sensor 1 is associated with a light source (LS) 17 for illuminating a scene for which a three-dimensional image is desired to be obtained. Light source 17 is, for example, a laser having a wavelength which may be in the range from 500 to 1,000 nm. Light source 17 is connected to control and processing circuit 15 to synchronize the control signals applied to the TOF pixels of array 3 and light source 17.

[0033] In the following description, the case of a sensor 1 where light source 17 emits a sinusoidal signal L.sub.E having a frequency which may be in the range from 20 to 100 MHz, for example, 25 MHz, is considered. For each pixel, phase-shift between the emitted light signal L.sub.E and the light signal L.sub.R received by this pixel is determined. The distance separating the pixel from its conjugated point is then determined from phase shift .

[0034] FIG. 2 shows an example of a TOF pixel circuit.

[0035] The TOF pixel comprises a photosensitive element (photo-diode) PD having a terminal connected to a node 21 and having its other terminal connected to a low reference potential, for example, the ground. Node 21 is coupled to sense node SN via three identical sets S.sub.1, S.sub.2, and S.sub.3 connected in parallel between nodes 21 and SN. Each set S.sub.i, with i equal to 1, 2, and 3 in this example, comprises a transfer N-channel MOS transistor, Tmem.sub.i, a charge storage area mem.sub.i, and a sense N-channel MOS transistor, Tsn.sub.i. The source of transistor Tmem.sub.i is connected to node 21, and the drain of transistor Tmem.sub.i is connected to a terminal of storage area mem.sub.i. Transistor Tmem.sub.i is controlled by a signal Vmem.sub.i applied to its gate. The source of transistor Tsn.sub.i is connected to the other terminal of storage area mem.sub.i, and the drain of transistor Tsn.sub.i is connected to sense node SN. Transistor Tsn.sub.i is controlled by a signal Vsn.sub.i applied to its gate. Examples of storage areas mem.sub.i will be given hereafter.

[0036] The TOF pixel is associated with a sense device which may be common to a plurality of pixels, for example, four pixels. The sense device comprises a precharge N-channel MOS transistor, Tres, an N-channel MOS transistor assembled as a source follower, Tsuiv, and a selection N-channel MOS transistor, Tsel, connected as shown. Sense node SN is coupled by transistor Tres to a power supply rail set to a high reference potential, for example, power supply potential Vdd. Transistor Tres is controlled by a signal Vres applied to its gate. Sense node SN is also coupled to the gate of transistor Tsuiv having its drain coupled to the power supply rail, and having its source coupled to an output rail 23 of the pixel circuit via transistor Tsel, transistor Tsel being controlled by a signal Vsel applied to its gate.

[0037] In this example, the TOF pixel further comprises an N-channel MOS transistor, Tres.sub.PD, for resetting photosensitive element PD. The source of transistor Tres.sub.PD is connected to node 21 and the drain of transistor Tres.sub.PD is connected to power supply rail Vdd. Transistor Tres.sub.PD is controlled by a signal Vres.sub.PD applied to its gate.

[0038] To determine the phase shift between the emitted light signal L.sub.E and the light signal L.sub.R received by the pixel, signal L.sub.R is sampled by transferring, successively and at regular intervals, charges photogenerated in the photosensitive element towards storage areas mem.sub.1, and then mem.sub.2, and finally mem.sub.3. The total time necessary to carry out these three successive transfers is equal to a period of signals L.sub.E and L.sub.R. Further, these three successive transfers are repeated a large number of times, for example, at least 100,000 times. The charges stored in the storage areas are then read by transferring, to node SN, the charges from area mem.sub.1, and then from area mem.sub.2, and finally from area mem.sub.3.

[0039] An embodiment of the TOF pixel of FIG. 2 will now be described in further detail in relation with FIG. 3.

[0040] FIG. 3 is a timing diagram of light signal L.sub.E emitted by light source 17 associated with sensor 1, of light signal L.sub.R received by the TOF pixel, and of digital signals Vres.sub.PD, Vres, Vmem.sub.i, Vsn.sub.i, and Vsel. By default, signals Vres.sub.PD, Vmem.sub.i, Vsn.sub.i, and Vsel are at a low level and signal Vres is at a high level.

[0041] A resetting of photosensitive element PD is first performed by setting transistor Tres.sub.PD to the on state (signal Vres.sub.PD in the high state) between times t.sub.0 and t.sub.1. An integration cycle of the pixel then starts and is synchronized on signal L.sub.E.

[0042] During the integration cycle, the charges photogenerated in photosensitive area PD are transferred to storage areas mem.sub.i. To achieve this, transfer transistors Tmem.sub.i are each set to the on state in turn. More particularly, transistor Tmem.sub.1 is set to the on state (Vmem.sub.1 high) between times t.sub.2 and t.sub.3, transistor Tmem.sub.2 is set to the on state (Vmem.sub.2 high) between times t.sub.4 and t.sub.5, and transistor Tmem.sub.3 is set to the on state (Vmem.sub.3 high) between times t.sub.6 and t.sub.7. As previously indicated, these three transfers are then repeated a large number of times. All along the integration cycle, signal Vres is in the high state, transistor Tres is on, and the voltage of sense node SN is substantially equal to the high reference potential.

[0043] At the end of the integration cycle, from a time t.sub.10, the charges stored in each of storage areas mem.sub.i are read. To achieve this, sense transistors Tsn.sub.i are each in turn set to the on state, and the voltage level on node SN is measured and stored after each reading of the charges stored in a storage area mem.sub.i. More particularly, transistor Tsel is set to the on state (Vsel high) at time t.sub.10 and precharge transistor Tres is set to the off state (Vres low) at a time t.sub.11. Transistor Tsn.sub.1 is then set to the on state (Vsn.sub.1 high) between successive times t.sub.12 and t.sub.13, followed by the setting to the on state of transistor Tsn.sub.2 (Vsn.sub.2 high) between successive times t.sub.14 and t.sub.15, followed by the setting to the on state of transistor Tsn.sub.3 (Vsn.sub.3 high) between successive times t.sub.16 and t.sub.17. First, second, and third voltage levels of node SN are measured and stored, respectively between times t.sub.13 and t.sub.14, between times t.sub.15 and t.sub.16, and between times t.sub.17 and a time t.sub.18. At time t.sub.18, signal Vsel is set to the low state and signal Vres is set back to the high state. A new integration cycle may then start.

[0044] In this embodiment, the first, second, and third measured voltage levels are representative of the charges stored, respectively, in storage area mem.sub.1, in storage areas mem.sub.1 and mem.sub.2, and in storage areas mem.sub.1, mem.sub.2, and mem.sub.3. In an alternative embodiment, a resetting of sense node SN is provided, by the application of a high-potential pulse on transistor Tres, after each reading of the charges stored in a storage area mem.sub.i. In this case, the first, second, and third voltage levels are representative of the charges stored in a single storage area, respectively mem.sub.1, mem.sub.2, and mem.sub.3.

[0045] These three voltage levels enable to determine phase shift between light signals L.sub.E and L.sub.R, and thus to deduce therefrom the distance separating the pixel from the point in the scene associated with the pixel.

[0046] Although an embodiment and a control mode of a TOF pixel circuit comprising three identical sets S.sub.i has been described, phase shift P between signals L.sub.E and L.sub.R may also be determined by using a TOF pixel comprising more than three sets S.sub.i, for example, four sets S.sub.i.

[0047] As an example, the time taken by a transfer towards a storage area mem.sub.i is in the range from 5 to 30 ns. The time separating two transfers to a same storage area mem.sub.i is for example 40 ns when the frequency of these signals is 25 MHz. In this case, the time taken by an integration cycle may be approximately 10 ms when the charge transfers to each of storage areas mem.sub.i are performed 250,000 times each. The time taken by a charge transfer from a storage area mem.sub.i to sense node SN is for example in the range from 1 to 10 s.

[0048] In a pixel, within a few nanoseconds, few charges are photogenerated in photosensitive element PD, for example, from 0 to 10 charges. Such charges should be integrally transferred to a storage area mem.sub.i. In particular, no charge should remain blocked in photosensitive element PD or in the channel of the corresponding transistor Tmem.sub.i.

[0049] An embodiment of a TOF pixel allowing a complete transfer of the charges photogenerated in photosensitive area PD towards storage areas mem.sub.i will now be described in relation with FIGS. 4A, 4B, 4C, and 4D.

[0050] FIGS. 4A to 4D schematically show an embodiment of a TOF pixel 40, FIG. 4A being a top view of the pixel and FIGS. 4B, 4C, and 4D being cross-section views respectively along planes BB, CC, and DD of FIG. 4A. In this embodiment, the pixel comprises three sets S.sub.i, with i equal to 1, 2, and 3, and one reset transistor Tres.sub.PD. Each set S.sub.i comprises a transfer transistor Tmem.sub.i, a storage area mem.sub.i, and a sense transistor Tsn.sub.i. Each set S.sub.i is associated with a sense area SN.sub.i.

[0051] TOF pixel 40 comprises a photosensitive area PD, for example, of square shape in top view. As illustrated in FIG. 4C, photosensitive area PD comprises an N-type doped layer 41, of doping level N.sub.1. N.sub.1 layer 41 is formed at the upper surface of a P-type doped semiconductor substrate 43 having a doping level which may decrease as the distance to N.sub.1 layer 41 decreases.

[0052] As illustrated in FIG. 4C, TOF pixel 40 also comprises, in photosensitive area PD, an N-type doped charge collection area 45, having a doping level N.sub.2 greater than N.sub.1. N.sub.2 layer 45 is covered by a heavily-doped P-type layer 47 (P.sup.+). N.sub.2 layer 45 extends through all or part of the thickness of N.sub.1 layer 41. In this example, N.sub.2 charge collection area 45 penetrates into P substrate 43 deeper than N.sub.1 layer 41.

[0053] As illustrated in FIG. 4C, each sense area SN.sub.i is heavily N-type doped (N.sup.+) and is formed in N.sub.1 layer 41, beyond photosensitive area PD. Sense areas SN.sub.i correspond to sense node SN described in relation with FIG. 2 and may be electrically connected to one another.

[0054] As illustrated in FIGS. 4A and 4D, each storage area mem.sub.i extends widthwise between two insulated vertical electrodes 49, parallel to and facing each other, and lengthwise from photosensitive area PD to a corresponding sense area SN.sub.i. Electrodes 49 delimiting each storage area mem.sub.i may comprise an extension 50 entirely delimiting the corresponding N.sup.+ area SN.sub.i, except for the edge on the side of area mem.sub.i. As illustrated in FIG. 4C, insulated vertical electrodes 49, 50 extend from the upper surface of pixel 40, cross N.sub.1 layer 41, and penetrate into P substrate 43. Insulated vertical electrodes 49 comprise a conductive material 51, for example, doped polysilicon, bordered with an insulating layer 53, for example, made of silicon oxide.

[0055] In this embodiment, as illustrated in FIG. 4A, each storage area mem.sub.i extends lengthwise from an opening 54 in an edge of photosensitive area PD, orthogonally to this edge. Further, each storage area mem.sub.i has a large side aligned with an edge of photosensitive area PD, so that each storage area mem.sub.i extends from a corner of photosensitive area PD. Advantageously, the insulated vertical electrodes 49 delimiting storage areas mem.sub.i may comprise extensions 55, which delimit photosensitive area PD.

[0056] Each storage area mem.sub.i comprises, as illustrated in FIGS. 4C and 4D, an N-type doped well 57, having a doping level N.sub.5 greater than N.sub.1, covered by P.sup.+ layer 47 and laterally delimited by corresponding vertical insulating electrodes 49. Each N.sub.5 well 57 penetrates into substrate 43 down to a depth greater than or equal to that of N.sub.1 layer 41 and smaller than that of insulated electrodes 49, 50, 55. Each storage area mem.sub.i is separated from N.sub.2 charge collection area 45 by a portion 41A of N.sub.1 layer 41. Each N.sub.1 portion 41A of photosensitive area PD is entirely covered by gate 59 of the corresponding transfer transistor Tmem.sub.i, gate 59 being separated from N.sub.1 portion 41A by a gate insulator layer 61. Each of storage areas mem.sub.i is separated from the corresponding area SN.sub.i by a portion 41B of N.sub.1 layer 41. N.sub.1 portion 41B is arranged outside of the photosensitive area and is entirely coated with gate 63 of the corresponding sense transistor Tsn.sub.i, gate 63 being separated from N.sub.1 portion 41B by a gate insulator layer 65.

[0057] In this embodiment, as illustrated in FIG. 4C, each area mem.sub.i comprises an N-type doped area 67, having a doping level N.sub.4 greater than N.sub.1 and smaller than N.sub.5, covered by P.sup.+ layer 47, and adjacent to photosensitive area PD. Each N.sub.4 area 67 penetrates into P substrate 43, for example down to a depth greater than or equal to that of N.sub.1 layer 41 and smaller than or equal to that of N.sub.5 wells 57. Further, each N.sub.1 portion 41A comprises an N-type doped 69, having a doping level N.sub.3 greater than N.sub.1 and smaller than N.sub.4, N.sub.5 and N.sub.2, covered by gate 59 of the corresponding transistor Tmem.sub.i, and adjacent to a corresponding storage area mem.sub.i. The N.sub.3 areas 69 penetrate into P substrate 43, for example, down to a depth substantially equal to that of N.sub.1 layer 41. Thus, from N.sub.2 charge collection area 45 and all the way to a sense area SN.sub.i, one can successively find, in contact two by two, N.sub.2 charge collection area 45, an N.sub.1 portion 41A, an N.sub.3 area 69, an N.sub.4 area 67, an N.sub.5 well 57, an N.sub.1 portion 41B, and sense area SN.sub.i.

[0058] Reset transistor Tres.sub.PD comprises a heavily N-type doped drain area 71 (N.sup.+) formed outside of photosensitive area PD, for example, in N.sub.1 layer 41. N.sup.+ area 71 extends widthwise between two insulated vertical electrodes 49, parallel to and facing each other, and lengthwise from photosensitive area PD. N.sup.+ area 71 is separated from N.sub.2 charge collection area 45 by a portion 41C of N.sub.1 layer 41 as illustrated in FIG. 4B. N.sub.1 portion 41C of photosensitive area PD is covered by gate 73 of transistor Tres.sub.PD, gate 73 being separated from this N.sub.1 portion 41C of photosensitive area PD by a gate insulator layer 75.

[0059] In this embodiment, as illustrated in FIG. 4A, and similarly to storage areas mem.sub.i, N.sup.+ area 71 of transistor Tres.sub.PD extends lengthwise from an opening 54 in an edge of photosensitive area PD, orthogonally to this edge, and has a large side aligned with another edge of photosensitive area PD, so that N.sup.+ area 71 extends from a corner of photosensitive area PD. Advantageously, insulated vertical electrodes 49 delimiting N.sup.+ area 71 may comprise extensions 55 which delimit photosensitive area PD, and an extension 50 delimiting the small side of N.sup.+ area 71 opposite to photosensitive area PD.

[0060] In this embodiment, as shown in FIG. 4A, charge collection area 45 has the shape of a cross comprising a central portion arranged at the center of the photosensitive area, and arms extending from this central portion, between gates 59, 73 resting on photosensitive area. The thicknesses and the materials of the gates of transistors Tmem.sub.i and Tres.sub.PD may then be selected so that these gates are transparent to the radiations of the light signal L.sub.R received by the pixel. Thereby, signal L.sub.R may reach photosensitive area PD after having crossed the gates of transistors Tmem.sub.i and Tres.sub.PD. For example, polysilicon gates 59 and 73 having a thickness in the range from 150 nm to 600 nm, and silicon oxide gate insulators 61, 75 having a thickness in the range from 3 to 12 nm are transparent to a near-infrared signal L.sub.R having a wavelength in the range from 800 to 1,000 nm. Further, such thicknesses and materials may advantageously not be transparent to parasitic luminous radiations having wavelengths distant from those of signal L.sub.R. This enables to filter at least part of the parasitic radiations. For example, the gates and the gate insulators indicated hereabove as an example absorb at least a portion of parasitic luminous radiations in the visible spectrum having wavelengths in the range from 400 to 700 nm.

[0061] A shield opaque to light (not shown), for example, made of a metal such as tungsten, aluminum, or copper, is provided above areas mem.sub.i, areas SN.sub.i, and possibly the gates of transistors Tsn.sub.i so that the radiations of luminous signal L.sub.R only reach photosensitive area PD of the pixel. This advantageously enables to avoid the photogeneration of parasitic charges in the storage areas. The opaque shield arranged on each area mem.sub.i may further extend over all or part of gate 59 of the corresponding transistor Tmem.sub.i. In particular, the shield may further extend over a portion of gate 59 of transistor Tmem.sub.i totally covering N.sub.3 portion 69 and over a portion, adjacent to N.sub.3 portion 69, of N.sub.1 portion 41A to avoid for charges to be photogenerated therein and then transferred to the adjacent storage area mem.sub.i while they should be transferred to another storage area mem.sub.i.

[0062] To manufacture the TOF pixel of FIGS. 4A to 4C, according to an embodiment and referring to FIG. 4C, it is started from a substrate 43 corresponding to a doped P-type silicon wafer or of a substrate obtained by epitaxy of P-type in-situ doped silicon, the dopant atom concentration may vary during the epitaxy to obtain a doping gradient such as previously described. Insulated vertical electrodes 59 and their extensions 50, 55 are simultaneously formed from a same trench with insulated walls (insulator 53) filled with conductive material 51. N.sub.1 layer 41 and N.sub.3 area 69 are then formed during steps of masking and dopant atom implantation, for example, with doses of dopant atoms in the range from 5*10.sup.11 to 5*10.sup.13 at.Math.cm.sup.2. Although in the embodiment described herein, areas 41B and 41C have a doping level N.sub.1, it may be provided for these areas to have a doping level N.sub.3 by adapting the layout of the masks used during the forming of N.sub.3 area 69. The gates of transistors Tsn.sub.i, Tres.sub.PD, and Tmem.sub.i are then formed on the substrate, after which N.sub.4 area 67, N.sub.2 area 45, N.sup.+ area SN.sub.i, and N.sup.+ area 71, and N.sub.5 wells 57 are formed during steps of masking and dopant atom implantation, for example, with doses of dopant atoms in the range from 5*10.sup.11 to 5*10.sup.13 at.Math.cm.sup.2. P.sup.+ layer 47 is finally formed by implantation.

[0063] Due to the fact that N.sub.4 area 67, N.sub.2 area 45, N.sup.+ area SN.sub.i, and N.sup.+ area 71, and N.sub.5 wells 57 are formed after the gates of transistors Tmem.sub.i, Tsn.sub.i and Tres.sub.PD, these areas and wells advantageously have edges aligned with these gates. In particular, N.sub.2 area 45 occupies the entire surface of photosensitive area PD which is not covered by gates 59 and 73. Storage areas mem.sub.i each have a small side aligned with an edge of a gate 59, this small side corresponding to a portion of an edge of photosensitive area PD, more particularly to opening 54 in this edge. N.sup.+ area 71 of transistor Tres.sub.PD has a small side aligned with an edge of gate 73, this small side corresponding to a portion of an edge of photosensitive area PD, more particularly to opening 54 in this edge.

[0064] Further, due to the fact that P.sup.+ layer 47 is formed after the gates of transistors Tsn.sub.i, Tmem.sub.i, and Tres.sub.PD, the P.sup.+ layer is not formed under the gates of these transistors, but only around these gates, over the entire charge collection area 51 and storage areas mem.sub.i. Charge transfers under these gates 59, 73 are then advantageously performed bulkwise. As a result, the transferred charges do not reach gate insulators 61, 65, or 75 where they could have remained trapped, and all the charges of photosensitive area PD are effectively transferred to areas mem.sub.i.

[0065] To suppress possible parasitic charge exchanges between two neighboring pixels, substrate 43 may correspond to a semiconductor layer resting on an insulating layer (substrate of semiconductor-on-insulator type), and electrodes 49, 50, 55 may then be formed through the entire thickness of N.sub.1 layer 41 and of P substrate 43 to electrically insulate the photosensitive areas from one another.

[0066] In operation, insulated electrodes 49 and their extensions 50, 55 are connected to a negative or zero potential so that holes are stored along their walls. This enables to decrease dark currents, and to set P.sup.+ layer 47 and P substrate 43 to a same low reference potential, for example, the ground, applied to substrate 43 or to layer 47. Photosensitive PD and storage areas mem.sub.i then correspond to so-called pinned diodes. The doping levels of photosensitive area PD and of storage areas mem.sub.i are selected so that, in the absence of illumination, the pinned diodes are fully depleted. Further, as described in relation with FIG. 2, a positive potential such as power supply potential Vdd is applied to drain area 71 of transistor Tres.sub.PD.

[0067] FIGS. 5A to 5D schematically show, according to the control potentials applied to transistors Tmem.sub.i and Tsn.sub.i, the variation in plane CC of FIG. 4A of the levels of the electrostatic potentials in photosensitive area PD, under the gates of transistors Tmem.sub.i and Tsn.sub.i, and in storage areas mem.sub.i. More particularly, FIGS. 5A to 5C illustrate a step of charge transfer from photosensitive area PD to a storage area mem.sub.i, and FIG. 5D illustrates a step of charge transfer from area mem.sub.i to the corresponding sense area SN.sub.i. In these drawings, the electrostatic potentials are increasing from top to bottom.

[0068] At the step of FIG. 5A, transistors Tmem.sub.i and Tsn.sub.i are maintained in the off state by applying negative or zero potentials to their gates, for example, the ground potential. Due to the fact that doping levels N.sub.1, N.sub.3, N.sub.4, N.sub.5, N.sup.+ are increasing, electrostatic potentials V1A and V1B, V3, V4, V5 and V.sup.+, respectively in portions 41A and 41B, N.sub.3 area 69, N.sub.4 area 67, N.sub.5 well 57, and area SN.sub.i, are increasing. Further, doping level N.sub.2 being greater than levels N.sub.1 and N.sub.3, electrostatic potential V2 in the charge collection area is greater than electrostatic potentials V1A and V3.

[0069] When the pixel receives light, electron-hole pairs are photogenerated in photosensitive area PD. The holes are drained off towards the low reference potential and the electrons (represented by crosses in the drawings) are stored in photosensitive area PD. Due to the fact that potential V2 is greater than potential V1A, the photogenerated electrons are drained towards N.sub.2 charge collection area 45 where they accumulate. N.sub.2 area 45 is selected to be sufficiently thick to allow the storage of electrons in the volume of this N.sub.2 area 45 before their transfer to a storage area mem.sub.i. Such a draining of electrons to N.sub.2 area 45 is more efficient when substrate 43 has a doping level gradient such as previously described and/or when N.sub.2 charge collection area 45 penetrates into the substrate more deeply than N.sub.1 layer 41.

[0070] At the step of FIG. 5B, transistor Tmem.sub.i is set to the on state by application of a positive potential on its gate 59 so that potential V1A and potential V3 become greater than potentials V2 and V4. The gate entirely covering N.sub.1 portion 41A and N.sub.3 area 69, potential V1A remains lower than potential V3. The electrons stored in N.sub.2 charge collection area 45 are thus all transferred to N.sub.3 area 69, where they are temporarily stored due to their being blocked between potential barriers V1A and V4. Further, due to the fact that potential V4 is smaller than potential V5, the electrons which have already been transferred into storage area mem.sub.i remain confined in N.sub.5 well 57 although, in this example, potential V3 is greater than potential V5.

[0071] Advantageously, due to the fact that the gate of transistor Tmem.sub.i covers a portion of photosensitive area PD, it contributes to attracting the photogenerated electrons present in photosensitive area PD to the upper surface of the pixel, before their transfers to N.sub.3 area 69. As a result, no photogenerated electron remains in photosensitive area PD.

[0072] At the step of FIG. 5C, transistor Tmem.sub.i is set back to the off state, whereby potentials V1A and V3 become smaller than potentials V4 and V5 again. Further, potential V1A remains greater than V3. As a result, the electrons which were in N.sub.3 area 69 are all transferred to the corresponding N.sub.5 well 57, through N.sub.4 area 67. Advantageously, potential V1A forms a potential barrier preventing the returning of electrons from N.sub.3 area 69 to N.sub.2 charge collection area 45. The electron storage capacity in N.sub.5 well 57 depends on the depth of the potential well, and particularly on the difference between potential V5 and potentials V1B and V4, which form potential barriers around N.sub.5 well 57. Such a storage capacity may advantageously be adapted by modifying potential levels V1B and V4 with respect to potential level V5. For example, a decrease in doping levels N.sub.1 of portion 41B and N.sub.4 of portion 69 causes a greater difference between potential V5 and potentials V1B and V4, and thus an increase in the electron storage capacity in N.sub.5 well 57. This storage capacity may also be increased by increasing doping level N.sub.5 of well 57, by decreasing the bias potential applied to electrodes 49, and/or by modifying the well dimensions. In particular, the electrons being stored in the volume of N.sub.5 wells 57, these wells are selected to have a sufficiently large thickness to be able to store a given amount of electrons. Further, the thickness of the wells is selected to be smaller than or equal to that of insulated electrodes 49, 50, and 55 which control the electrostatic confinement of electrons in these wells.

[0073] At the step of FIG. 5D, transistor Tsn.sub.i is set to the on state by application of a positive potential on its gate 63 so that potential V1B becomes greater than potentials V5 and remains smaller than potential V.sup.+. The electrons are then transferred from area mem.sub.i to sense area SN.sub.i. Transistor Tsn.sub.i is then set to the off state, and the quantity of photogenerated electrons transferred into area SN.sub.i may be read by the read circuit connected to area SN.sub.i. As concerns transistor Tres.sub.PD, when it is maintained in the off state by application of a negative or zero potential on its gate 73, for example, the ground potential, the photogenerated electrons remain in the N.sub.2 charge collection area 45 of photosensitive area PD. Indeed, due to the fact that doping level N.sub.1 is smaller than doping level N.sub.2, electrostatic potential V1C in N.sub.1 portion 41C covered by gate 73 of transistor Tres.sub.PD is smaller than potential V2 in N.sub.2 charge collection area 45. When transistor Tres.sub.PD is set to the on state by application of a positive potential on its gate 73, this potential is selected so that potential level V1C in N.sub.1 portion 41C becomes greater than potential V2 and remains smaller than the potential applied to drain area 71 of transistor Tres.sub.PD. As a result, the photogenerated electrons present in photosensitive area PD are all drained off from the pixel to potential Vdd.

[0074] In an alternative embodiment, the potential applied to the gate of transistor Tres.sub.PD in the off state may be selected to be greater than that applied to the gates of transistors Tmem.sub.i in the off state so that, when these transistors are in the off state, potential V1C is greater than potential V1A. Thereby, an excess of photogenerated electrons in photosensitive area PD will be drained off to N.sup.+ region 71 rather than to a storage area mem.sub.i. Transistor Tres.sub.PD may thus advantageously be used as an anti-dazzle transistor in addition to being used as a transistor for resetting photosensitive area PD.

[0075] It should be understood from the above-described operation that N.sub.1 layer 41 mainly is a charge transfer layer close to the surface, from N.sub.2 charge collection area 45 to storage areas mem.sub.i, and, in this example, from areas mem.sub.i to N.sup.+ areas SN.sub.i and 71. The thickness of N.sub.1 layer 41 may thus be selected to be lower than those of N.sub.5 wells 57 and of N.sub.2 area 47. Similarly, N.sub.3 areas 69 each have as a main function to enable the charge transfer from the photosensitive area to the corresponding memory area mem.sub.i. The thickness of N.sub.3 area 69 can then be selected to be substantially equal to that of N.sub.1 layer 41. It should further be understood that N.sub.4 areas 67 have as a main function to allow the charge transfer from N.sub.1 area 41A and N.sub.3 area 69 to an N.sub.5 well 57 when the corresponding transistor Tmem.sub.i is in the on state, and to prevent the flowing of charges from an N.sub.5 well 57 to N.sub.3 area 69 and N.sub.1 area 41A when the corresponding transistor Tmem.sub.i is in the off state. The thickness of N.sub.4 area 67 may then be selected to be greater than the thickness of N.sub.1 area 41A and N.sub.3 area 69 and smaller than or equal to that of N.sub.5 wells 47. As an example, transistor Tmem.sub.i switches at high frequency between the on state and the off state, for example, at a 25-MHz frequency.

[0076] FIG. 6 is a simplified top view of an alternative embodiment of the TOF pixel of FIGS. 4A to 4C.

[0077] TOF pixel 80 of FIG. 6 comprises the same elements as TOF pixel 40 of FIGS. 4A to 4C, except that the N.sup.+ drain 71 of transistor Tres.sub.PD and the assemblies of two associated areas mem.sub.i and SN.sub.i are not arranged in the same way relative to photosensitive area PD. In this alternative embodiment, N.sup.+ drain 71 and assemblies mem.sub.i, SN.sub.i each extend along an edge of a square central portion of photosensitive area PD, rather than orthogonally to this edge as described in relation with FIGS. 4A to 4C.

[0078] For each transistor Tmem.sub.i, gate 59 and the portion of the photosensitive area PD that it coats extend through opening 54 in the side of photosensitive area PD bordered with the corresponding area mem.sub.i, so that gate 59 has an edge adjacent to a small side of area mem.sub.i. Similarly, gate 73 of transistor Tres.sub.PD and the portion of photosensitive area PD that it coats extend through opening 54 in the side of photosensitive area PD bordered with N.sup.+ drain area 71 of transistor Tres.sub.PD, so that gate 73 has an edge adjacent to a small side of this N.sup.+ area 71.

[0079] Thus, the cross-section view along broken line BB of FIG. 6, running through N.sup.+ area 71, gate 73, and collection area 45, and the cross-section view along broken line CC, running through an area Sn.sub.i, a gate 63, an area mem.sub.i, a gate 59, and area 45, are identical to the cross-section views, respectively along planes BB and CC of FIG. 4A, illustrated in FIGS. 4B and 4C.

[0080] In this variation, each electrode 49, 50 delimiting, on the side of photosensitive area PD, a large side of an assembly mem.sub.i, Sn.sub.i or a large side of N.sup.+ area 71, also partially delimits an edge of the photosensitive area. Further, each electrode 49, 50 delimiting, on the side opposite to photosensitive area PD, the other large side of an assembly mem.sub.i, SN.sub.i or the other large side of N.sup.+ area 71, comprises a rectilinear extension 55 all the way to a neighboring assembly mem.sub.i, SN.sub.i or to N.sup.+ area 71. More particularly, each extension 55 is aligned with an end of a neighboring assembly SN.sub.i, mem.sub.i or with an end of N.sup.+ area 71. Thus, pixel 80 is square-shaped, which simplifies the forming of an array comprising a plurality of pixels 80 organized in rows and in columns.

[0081] The operation of pixel 80, similar to that of pixel 40, will not be detailed.

[0082] FIG. 7 is a simplified top view of another variation of pixel 40 of FIGS. 4A to 4C.

[0083] Pixel 90 of FIG. 7 comprises same elements as pixel 80 of FIG. 6, arranged relative one another in the same way as in pixel 80, with the difference that, in pixel 90, the N.sup.+ drain 71 of transistor Tres.sub.PD and the assemblies of two associated areas mem.sub.i and SN.sub.i are longer. Thus, N.sup.+ area 71 and assemblies mem.sub.i, SN.sub.i, each have one end arranged beyond the large side, opposite to photosensitive area PD, of a neighboring assembly mem.sub.i, SN.sub.i or of N.sup.+ area 71. Thus, as shown in FIG. 7, it is possible for gates Tsn.sub.i not to be adjacent to the gates of transistors Tres.sub.PD or Tmem.sub.i, which eases the forming of the gates of transistors Tsn.sub.i, Tres.sub.PD, and Tmem.sub.i.

[0084] TOF pixels 40, 80, and 90 where the gates of transistors Tmem.sub.i and Tres.sub.PD are arranged on the photosensitive area of these pixels have been described. These gates contribute to attracting the charges photogenerated in photosensitive area PD towards the surface of these pixels during a charge transfer from photosensitive area PD. In practice, such a charge transfer should be performed within a very short time, for example, shorter than 30 ns, whereby the charges photogenerated in photosensitive area PD should be attracted under the corresponding gate of a transistor Tmem.sub.i or Tres.sub.PD within a still shorter time. It is thus desirable for the photosensitive area to have a small surface area, for example, smaller than 5 m*5 m, or even smaller than 3 m*3 m, to limit the path of charges in photosensitive area PD.

[0085] Advantageously, due to the fact that in a TOF pixel 40, 80, or 90, photosensitive area PD may have a small surface area, and due to the fact that the storage areas may have small dimensions, for example, an approximate 0.2-m width and an approximate 1-m length, such a pixel may occupy a smaller surface area than that occupied by a SPAD-type TOF pixel. For example, TOF pixel 80 of FIG. 6 may occupy a surface area in the order of 3 m*3 m.

[0086] Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, a first heavily-doped P-type layer (P.sup.+) may cover storage areas mem.sub.i while a second heavily-doped P-type layer (P.sup.+) having a doping level and/or a thickness different from those of the first layer may cover N.sub.2 charge collection area 45.

[0087] Similarly to what has been described for N.sub.1 portions 41A, N.sub.1 portion 41C of transistor Tres.sub.PD may comprise an N.sub.3 area 69 adjacent to N.sup.+ area 71 to improve the charge transfer controlled by transistor Tres.sub.PD.

[0088] Each N.sub.1 area 41B may comprise an area adjacent to the corresponding N.sup.+ area SN.sub.i, N-type doped with a doping level greater than N.sub.1 and smaller than N.sup.+, to avoid for charges to flow back from sense area SN.sub.i to storage area mem.sub.i.

[0089] N.sup.+ areas SN.sub.i and/or 71 may be formed in an N-type doped layer with a doping level different from that of layer N.sub.1, for example, in a layer of doping level N.sub.3. N.sup.+ areas SN.sub.i and/or 71 may also be directly formed in substrate 43.

[0090] Substrate 43 may be N-type doped, with a doping level smaller than N.sub.1, and it may then have a doping level which increases as the distance to N.sub.1 layer 41 decreases.

[0091] The order and the number of steps of the previously-described manufacturing method may be modified. For example, in the case of a pixel which does not comprise areas 67 and/or 69, the implantation steps corresponding to the forming of these areas will be suppressed. In particular, in the case of a pixel which does not comprise N.sub.4 area 67, it is provided for N.sub.5 well 57 to occupy the entire storage area mem.sub.i and to have a small side aligned with a gate 59. Further, although a method of manufacturing a pixel where N.sub.5 wells 57 will be formed after the transistor gates has been described, these wells may be formed before the gates, or even before N.sub.1 layer 41.

[0092] In the case where a plurality of TOF pixels 40, 80, or 90 are formed next to one another, for example, in an array of pixels of an image sensor, two adjacent pixels may share elements such as portions of electrodes 49 and/or of their extensions 50, 55, sense areas SN.sub.i, drain area 71 of transistor Tres.sub.PD, and/or transistors of a read circuit coupled to sense areas SN.sub.i.

[0093] Transistor Tres.sub.PD may be omitted in the previously-described pixels. Indeed, the charges photogenerated in photosensitive area PD being all transferred to sense areas SN.sub.i, the photodiode resetting step may be suppressed.

[0094] The number of sets S.sub.i and of associated areas SN.sub.i may be selected to be greater than 3, possibly by providing for the photosensitive area to have the shape of a polygon, for example, a regular polygon, other than a square. For example, in a pixel comprising 6 sets S.sub.i and comprising no reset transistor Tres.sub.PD, the photosensitive area for example has a substantially hexagonal shape.

[0095] More generally, the shape, the number, and the layout of the various elements forming previously-described pixels 40, 80, and 90 may be modified. For example, it may be provided for storage areas mem.sub.i, the gates of transistors Tmem.sub.i, photosensitive area PD, and more particularly charge collection area 45 of photosensitive area PD to be arranged relative to one another as described in patent application FR no 15/63457 filed on Dec. 30, 2015, which is incorporated herein by reference.

[0096] Although conductivity types have been described for the various areas, layers, and wells of a pixel in the case where the accumulated, collected, transferred, stored, and read charges are electrons, these conductivity types may all be inverted so that the charges are holes. It will be within the abilities of those skilled in the art to adapt the control potentials applied to the various transistors of the pixel.

[0097] Various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step.

[0098] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.