Abstract
A nitride semiconductor transistor device is disclosed to provide a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting charge stored in the charge storage layer.
Claims
1. A nitride semiconductor transistor device, comprising: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer, wherein a band gap of the second nitride semiconductor layer is wider than a band gap of the first nitride semiconductor layer; a first insulating film formed over the second nitride semiconductor layer; a charge storage layer comprising a low resistivity layer made of metal or semiconductor, wherein at least a portion of the charge storage layer is formed over the first insulating film over the second nitride semiconductor layer; a source electrode and a drain electrode formed over the second nitride semiconductor and horizontally sandwiching the charge storage layer; and a first control electrode electrostatic-capacitively coupled with the charge storage layer via a first capacitor, wherein an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface between the first and second nitride semiconductor layers is adjustable by adjusting a potential of the charge storage layer, wherein the potential is controlled by a voltage applied to the first control electrode, and a threshold voltage at which the electric current is shut off by the voltage applied to the first control electrode is adjustable with a quantity of charge stored in the charge storage layer.
2. The nitride semiconductor transistor device according to claim 1, wherein the charge stored in the charge storage layer is negative and the threshold voltage is made positive by controlling the amount of the charge stored in the charge storage layer.
3. The nitride semiconductor transistor device according to claim 1, further comprising a second insulating film formed over at least a portion of the charge storage layer, and the first control electrode is formed over the second insulating film, wherein the second insulating film serves as an interlayer film between the charge storage layer and the first control electrode to form the first capacitor.
4. The nitride semiconductor transistor device according to claim 3, wherein an electrically inactive cell isolation region is formed on the substrate, the charge storage layer is extended to overlap with the cell isolation region, at least a portion of the second insulating film is formed over a portion of the charge storage layer overlapping with the cell isolation region, at least a portion of the first control electrode is formed over the second insulating film over the portion of the charge storage layer overlapping with the cell isolation region.
5. The nitride semiconductor transistor device according to claim 3, wherein a capacitance of the first capacitor is larger than a capacitance of a second capacitor formed between the charge storage layer and the second nitride semiconductor layer.
6. The nitride semiconductor transistor device according to claim 4, wherein a third insulating film is formed on at least a portion of the cell isolation region, and at least a part of the portion of the charge storage layer overlapping with the cell isolation region is formed on the third insulating film.
7. The nitride semiconductor transistor device according to claim 6, wherein a thickness of the third insulating film is larger than a thickness of the first insulating film, and a capacitance of the third insulating film per unit area is smaller than the capacitance of the first insulating film per unit area, wherein the capacitances of the first and third insulating films per unit area is defined by the thicknesses and dielectric constants of the first and third insulating films.
8. The nitride semiconductor transistor device according to claim 2, wherein a second control electrode is formed over the second nitride semiconductor layer between the charge storage layer and the drain electrode, wherein the electric current flowing between the source and drain electrodes through the conductive channel induced between the first and second nitride semiconductor layers thereunder is adjustable with a voltage applied to the second control electrode, wherein the threshold voltage for the voltage applied to the second control electrode to shut off the electric current is negative.
9. The nitride semiconductor transistor device according to claim 1, wherein the first nitride semiconductor layer comprises GaN, and the second nitride semiconductor layer comprises Al.sub.xGa.sub.1-xN, wherein 0<x1.
10. The nitride semiconductor transistor device according to claim 1, wherein at least a bottom layer of the first insulating film comprises aluminum oxide.
11. A nitride semiconductor transistor device, comprising: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed over the first nitride semiconductor layer, wherein a band gap of the second nitride semiconductor layer is wider than a band gap of the first nitride semiconductor layer; a first insulating film formed over the second nitride semiconductor layer; a charge storage insulating film formed over the first insulating film; a second insulating film formed over the charge storage insulating film; a first control electrode formed over the second insulating film; and a source electrode and a drain electrode formed over the second nitride semiconductor layer and horizontally sandwiching the first control electrode, wherein the charge storage insulating film is able to store negative charge, wherein an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface between the first and second nitride semiconductor layers is adjustable by adjusting a voltage applied to the first control electrode, wherein a threshold voltage at which the voltage applied to the first control electrode shuts off the electric current is made positive by negative charge stored in the charge storage insulating film.
12. The nitride semiconductor transistor device according to claim 11, wherein the charge storage insulating film comprises silicon nitride.
13. The nitride semiconductor transistor device according to claim 11, wherein a second control electrode is formed above the second nitride semiconductor layer between the first control electrode and the drain electrode, wherein the electric current flowing between the source and drain electrodes through the conductive channel induced between the first and second nitride semiconductor layers thereunder is adjustable with a voltage applied to the second control electrode, wherein the threshold voltage for the voltage applied to the second control gate to shut off the electric current is negative.
14. The nitride semiconductor transistor device according to claim 11, wherein the first nitride semiconductor layer comprises GaN, and the second nitride semiconductor layer comprises Al.sub.xGa.sub.1-xN, wherein 0<x1.
15. The nitride semiconductor transistor device according to claim 11, wherein at least a bottom layer of the first insulating film comprises aluminum oxide.
16. The nitride semiconductor transistor device according to claim 11, wherein the charge storage insulating film comprises charge traps with energy levels inside both band gaps of the first and second insulating films, wherein the charge traps trap and store at least a portion of the negative charge.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The present disclosure will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present disclosure, and wherein:
[0036] FIG. 1(a) is a cross-sectional view of a FET in the first embodiment of the present disclosure.
[0037] FIG. 1(b) is a diagrammatic view of an equivalent circuit of capacitors among nodes of the FET in the first embodiment.
[0038] FIG. 1(c) is a diagrammatic view of the relation between threshold voltage and stored charge of the FET in the first embodiment.
[0039] FIG. 2(a) is a band diagram of the FET in the first embodiment.
[0040] FIG. 2(b) is a band diagram of the FET in the first embodiment.
[0041] FIG. 3 shows a horizontal projection and a cross-sectional view of an example of the FET in the first embodiment.
[0042] FIG. 4(a) shows a horizontal projection and a cross-sectional view of a FET in the second embodiment.
[0043] FIG. 4(b) shows a horizontal projection and a cross-sectional view of a FET in the third embodiment.
[0044] FIG. 4(c) is a horizontal projection of a FET in the fourth embodiment.
[0045] FIG. 4(d) is a horizontal projection of a FET in the fifth embodiment.
[0046] FIG. 4(e) shows a horizontal projection and a cross-sectional view of a FET in the sixth embodiment.
[0047] FIG. 4(f) shows a horizontal projection and a cross-sectional view of a FET in the seventh embodiment.
[0048] FIG. 5(a) is a cross-sectional view of a FET in the eighth embodiment.
[0049] FIG. 5(b) is a diagrammatic view of the relation between threshold voltage and stored charge of the FET in the eighth embodiment.
[0050] FIG. 5(c) is a band diagram of the FET in the eighth embodiment.
[0051] FIG. 5(d) is a band diagram of the FET in the eighth embodiment.
[0052] FIG. 5(e) is a horizontal projection of the FET in the eighth embodiment.
[0053] FIG. 5(f) is a diagrammatic view of electrical characteristics of the FET in the eighth embodiment.
[0054] FIG. 5(g) is a diagrammatic view of electrical characteristics of the FET in the eighth embodiment.
[0055] FIG. 5(h) is a cross-sectional view of a FET in the ninth embodiment.
[0056] FIG. 6(a) is a cross-sectional view of a FET in the tenth embodiment.
[0057] FIG. 6(b) is a cross-sectional view of a FET in the eleventh embodiment.
[0058] FIG. 6(c) is a cross-sectional view of a FET in the twelfth embodiment.
[0059] FIG. 6(d) shows a horizontal projection of the FETs in the tenth to twelfth embodiments.
[0060] FIG. 6(e) is a cross-sectional view of a FET in the thirteenth embodiment.
[0061] FIG. 7 is a cross-sectional view of a conventional FET.
[0062] FIG. 8 is a cross-sectional view of another conventional FET.
[0063] FIG. 9(a) is a band diagram of the conventional FET.
[0064] FIG. 9(b) is a band diagram of the conventional FET.
[0065] FIG. 9(c) is a band diagram of the conventional FET.
DETAILED DESCRIPTION OF THE INVENTION
[0066] FIG. 1(a) is a cross-sectional view of a FET in the first embodiment of the first invention of the present disclosure. A buffer layer 102, a GaN layer 103, an AlGaN layer 104 are in turn grown on a substrate 101. The substrate 101 and the buffer layer 102 may be made of the same materials as those used in the prior art shown in FIG. 7. Next, an insulating film 105 and a gate electrode 106 may be deposited on the AlGaN layer 104. Then, another insulating film 107 and a conductive layer (to be called as control gate electrode below) 108 may be deposited on the gate electrode (to be called as charge storage layer below) 106 in turn. Furthermore, a source electrode 109 and drain electrode 110 may be formed on the AlGaN layer 104. It is preferred that a thickness of AlGaN layer 104 is 10 nm or more on both sides of the gate electrode 106 between the source electrode 109 and the gate electrode 106, and between the drain electrode 110 and the gate electrode 106. A sufficient quantity of conduction electrons may be induced in a conductive channel 111 at the interface AlGaN/GaN so as to reduce the resistivity of the regions. It may be preferred to tune the alloy crystal ratio of Al-to-N in the AlGaN layer 104, that is, the value of x in the chemical formula Al.sub.xGa.sub.1-xN, in order to avoid an excessive lattice relaxation in AlGaN having different lattice constant from GaN. Usually, x may be ranging from 0.1 to 0.4. The gate electrode 106, in which the surrounding is covered by the insulating films 105 and 107, is electrically floating. Hereinafter, the gate electrode 106 and the conductive layer 108 may be called the charge storage layer 106 and the control electrode 108, respectively. Then, the source electrode 109, drain electrode 110 and control electrode 108 may be connected to external PINs when sealing it with a package. Moreover, it may be similar in other embodiments to be mentioned later that the electrodes connected to the external PINs are these three. A polycrystalline silicon doped with impurities may be adopted for the charge storage layer 106 as well as metallic layers. In this case, the impurities may be Phosphorus, Arsenide, Boron and so forth.
[0067] The capacitances among nodes of the FET in FIG. 1(a) are shown in FIG. 1(b). A capacitor 113 is formed between the charge storage layer 106 and a surface of AlGaN 112 just below the charge storage layer 106. A capacitor 114 is formed between the charge storage layer 106 and the control electrode 108. The capacitors 114 and 113 are the first and second capacitors in the first invention of the present disclosure, respectively. The charge storage layer 106 is electrostatic-capacitively coupled to the control electrode 108 via the capacitor 114. The charge storage layer 106 is further electrostatic-capacitively coupled to the AlGaN layer 104, particularly, the surface of AlGaN 112, via the capacitor 113. Thereby, a potential of the charge storage layer 106 is determined by potentials of the control electrode 108 and the surface of AlGaN 112 and a stored charge 115 in the charge storage layer 106. The potential is, generally, inhomogeneous along the horizontal direction at the surface of AlGaN layer 112. However, here, the surface of AlGaN 112 (just below the charge storage layer 106) is assumed to have a representative unique potential value. In the present structure, the terminals of the nitride semiconductor FET are the source electrode 109, the drain electrode 110 and the control electrode 108. While the potentials of the source electrode 109 and drain electrode 110 and a quantity of the stored charge 115 in the charge storage layer 106 are fixed, the potential of the charge storage layer 106 is determined by the control electrode 108, i.e. as the potential of the control electrode increases, the potential of the charge storage layer 106 also increases. Furthermore, while the potentials of the source electrode 109, drain electrode 110, and control electrode 108 are fixed, the potential of the charge storage layer 106 is determined by the quantity of the stored charge 115 in the charge storage layer 106. The charge storage layer 106 becomes lower in potential if the stored charge 115 in the charge storage layer 106 becomes more negative. Accordingly, the threshold voltage of FET is determined by the quantity of the stored charge 115 in the charge storage layer 106. As shown in FIG. 1(c), the threshold voltage is increased as the charge is more negatively stored. Thereby, it may be possible to make threshold voltage higher than 3V once the negative charge is stored more than a predetermined quantity in the charge storage layer 106 to obtain a normally-off condition.
[0068] In order to make the on-resistance and on-current more sensitive to the voltage applied to the control electrode 108, the capacitor 114 between the charge storage layer 106 and the control electrode 108 is made comparatively larger than the capacitor 113 between the charge storage layer 106 and the surface of AlGaN 112, thereby strengthening the electrostatic capacitive-coupling between the charge storage layer 106 and the control electrode 108. For this sake, it is preferred that the permittivity of the insulating film 107 on the charge storage layer 106 is higher than that of the insulating film 105 on the AlGaN layer 104. For example, the insulating film 105 on the AlGaN layer 104 may be silicon oxide and the insulating film 107 on the charge storage layer 106 may be a high permittivity dielectric (e.g., aluminum oxide). If the charge storage layer 106 and the control electrode 108 are the same in area, the capacitance ratio of the capacitors 114 and 113 is expressed as .sub.Al2O3t.sub.SiO2/.sub.SiO2/t.sub.Al2O3, where .sub.Al2O3 and .sub.SiO2 are the permittivity of aluminum oxide (Al.sub.2O.sub.3) and silicon oxide (SiO.sub.2), respectively, and t.sub.SiO2 and t.sub.Al2O3 are the thicknesses of silicon oxide and aluminum oxide, respectively. Thus, the capacitor 114 is larger in capacitance than the capacitor 113, as long as t.sub.Al2O3/t.sub.SiO2 is smaller than .sub.Al2O3/.sub.SiO2. Furthermore, it may also be preferred that the insulating film 105 on the AlGaN layer 104 is a multilayer of a plurality of different types of insulating films. For example, it may be a multilayer consisting of aluminum oxide and silicon oxide, or that of silicon nitride and silicon oxide. This configuration of the insulating film 105 may be similar in other embodiments to be mentioned below.
[0069] In order to inject charge into the charge storage layer 106 to obtain the stored charge 115, a high voltage is applied to the control electrode 108 while the potentials of the source and drain electrodes 109 and 110 are 0 V. Thus, the potential of the charge storage layer 106 also becomes high due to the capacitive-coupling between the control electrode 108 and the charge storage layer 106. The electrons in the AlGaN layer 104 may pass through the insulating film 105 on the AlGaN layer by tunneling effect and be injected into the charge storage layer 106. Since the charge storage layer 106 is surrounded by the insulating films 105 and 107, the electrons once having been injected thereto may hardly leak and thus may remain there. As shown in FIG. 1(c), the threshold voltage may be positive if the quantity of the stored charge 115 in the charge storage layer 106 exceeds a predetermined value. Then, a normally-off VET is obtained.
[0070] Another method to inject charge into the charge storage layer 106 to obtain the stored charge 115 is that the FET is turned on by applying a certain positive potential to the control electrode 108 while a certain large voltage is applied between the source and drain electrodes 109 and 110. Thus, some of electrons transporting through the conductive channel 111 may attain high energy at an edge portion of the control electrode 108 facing the source electrode 109 or drain electrode 110, where the horizontal electric field becomes high enough. A portion of the high energy electrons may change their direction of transport due to scattering with GaN inside the conductive channel 111 and be injected to the charge storage layer 106 through the surface of AlGaN 112 and the insulating film 105. If the quantity of electrons having been injected to the charge storage layer 106 exceeds a predetermined value, the threshold voltage becomes positive and the FET becomes normally-off.
[0071] A band diagram of normally-off FET is shown in FIG. 2(a), where no voltage is applied to the control electrode 108. The electron potential energy of the charge storage layer 106 is raised as the negative stored charge 115 is stored in the charge storage layer 106. Accordingly, as long as the quantity of the negative stored charge 115 is sufficient, a conduction band edge 121 of the GaN layer 103 is higher than a Fermi level (E.sub.F) 123 in such a way that the conduction electrons are not induced at the interface between the AlGaN layer 104 and the GaN layer 103, even though the polarization (P) 122 induced inside the AlGaN layer 104 causes a large potential drop across the AlGaN layer 104. Accordingly, it results in the state where threshold voltage is positive, as shown in FIG. 1(c).
[0072] FIG. 2(b) shows a band diagram where a positive gate voltage 125 (labeled as V in the figure) is applied to the control electrode 108. The conduction band edge 121 is lower than the Fermi level 123 at the interface between the AlGaN layer 104 and the GaN layer 103, and conduction electrons are induced there to cause an electric current to flow through the conductive channel 111. In the present embodiment, without the AlGaN layer 104 being thin in the portion forming the control electrode 108, the transistor can be made normally-off by storing the negative charge in the charge storage layer 106. Thereby, it may be unnecessary to care about the dispersion of cell characteristics such as threshold voltage, etc. due to thickness dispersion of the AlGaN layer 104 after etching like in the conventional practice. Furthermore, as shown in FIG. 2(b), the AlGaN layer 104 beneath the control electrode 108 is thick enough to make trap levels 124 higher in energy than the Fermi level 123 at the interface between the insulating film 105 and the AlGaN layer 104. Accordingly, conduction electrons may not be hindered from being induced in the conductive channel 111 when the voltage is applied to the control electrode 108.
[0073] A case is not described in which the AlGaN layer 104 is etched beneath the control electrode 108 in the present embodiment. Nevertheless, it may also be preferred that the AlGaN layer 104 is etched to become thinner to some extent. For example, similar to FIG. 7 which shows a conventional FET, the insulating film 105, the charge storage layer 106 and so forth may be buried into the recess etching portion formed in the AlGaN layer 104. Even in this case, the residual thickness of the AlGaN layer 104 may be sufficient to suppress the dispersion of cell characteristics such as threshold voltage, etc. The influence of trap levels may also be avoided.
[0074] FIG. 3 is the horizontal projection and the cross-sectional views along A-A and B-B of the FET, which is an example of the first embodiment. FIG. 1 corresponds to the A-A cross-section from the source electrode 109 to the drain electrode 110 in FIG. 3. In the horizontal projection, the area of the AlGaN layer 104 is the cell area of the FET, where the rest is the cell isolation region 116. As shown in FIG. 3, the AlGaN layer 104 is removed for forming the cell isolation, but the GaN layer 103 and/or buffer layer 102 may also be removed simultaneously. Furthermore, it may also be preferred to electrically inactivate the GaN layer 103 and/or buffer layer 102 by ion implantation. Alternatively, it may also be preferred to electrically inactivate the AlGaN layer 104 as well as the GaN layer 103 and/or buffer layer 102 by the ion implantation without removing the AlGaN layer 104. The cell isolation method of other embodiments to be mentioned below may be similar to the above. In order to suppress leakage between the source and drain electrodes 109 and 110 of the FET, the ends of the charge storage layer 106 extends to the cell isolation region 116, as shown in the B-B cross-sectional view. However, the area that the charge storage layer 106 overlaps with the cell isolation region 116 may be sufficiently smaller than that of the charge storage layer 106 above the cell region (AlGaN layer 104). Accordingly, the capacitance between the cell isolation region 116 and the charge storage layer 106 is small enough to be ignorable compared with the capacitor 113 between the charge storage layer 106 and the AlGaN layer 104 in the cell region.
[0075] The nitride semiconductor FET in the present embodiment may be promising not only for power switching devices to be used in a power supply circuit, etc., but also for high frequency transistors. In this embodiment, the control electrode 108 may be identical to the electrode usually called gate electrode in the high frequency transistors. Since FET is normally-off, that is, executes the enhancement type operation, both voltages to be applied to the gate electrode and the drain electrode can be positive. Thereby, the transistor may be able to be operated with a positive single power supply, thus simplifying the electric supply source. Furthermore, the AlGaN layer 104 beneath the control electrode 108 serving as the gate electrode can be made thick to suppress the dispersion of threshold voltage due to the thickness variation. In addition, since the transistor is less affected by the trap levels existing at the interface of the insulating film 105 and the AlGaN layer 104, the high frequency transistor which is excellent in the properties such as the trans-conductance, the maximum drain current and so forth, may be obtained.
[0076] FIG. 4(a) shows the horizontal projection and the cross-sectional views along A-A and B-B of FET, which is an example of the second embodiment. The present embodiment also belongs to the first invention of the present disclosure. In the horizontal projection, similar to the first embodiment, the area of the AlGaN layer 104 is the cell area of FET and the rest is the cell isolation region 116. The majority of the charge storage layer 106 inside the cell isolation region 116 may exist above an insulating film 201 on the GaN layer 103. The insulating film 201 on the GaN layer 103 may be thicker than the insulating film 105. Thus, the capacitance of the insulating film 201 per unit area is smaller than that of the insulating film 105, where the capacitance of the insulating film per unit area is defined by the dielectric constant and the thickness of the insulating film. Thereby, the parasitic capacitance between the charge storage layer 106 and the GaN layer 103 in the cell isolation region may become sufficiently smaller than the capacitor 113 formed between the charge storage layer 106 and the AlGaN layer 104 in the cell region. In addition, the insulating film 107 and the control electrode 108 may be in turn stacked above the charge storage layer 106 in the cell isolation region 116. Accordingly, the capacitor 114 may be formed between the charge storage layer 106 and the control electrode 108. Similar to the first embodiment, the capacitor 114 is larger in capacitance than in the capacitor 113. Thus, the on-resistance and on-current may be more easily controlled by the control electrode 108.
[0077] The capacitance of the capacitor 114 is in proportion to the overlapping area of the charge storage layer 106 and the control electrode 108. Thus, the electrostatic capacitive-coupling is able to be strengthened between the charge storage layer 106 and the control electrode 108, if the overlapping area is widened to enlarge the capacitance of the capacitor 114. Accordingly, the insulating film 107 may not be necessarily a high permittivity material, which is different from the case of the first embodiment. For example, silicon oxide or a multilayer of three films of silicon oxide/silicon nitride/silicon oxide may be possibly used. Moreover, the physical thickness of the insulating film 107 may be larger than that of the insulating film 105. The configuration of the insulating 107 may be similar in other embodiment.
[0078] Furthermore, for the charge storage layer 106, polycrystalline silicon doped with impurities may be used as well as metallic layers. In that case, the impurities may be phosphorus, arsenide, boron and so forth.
[0079] In the second embodiment mentioned above, the bottom electrode of the capacitor 114 configured in the cell isolation region is made of the charge storage layer 106 extending from the cell region. However, a bottom electrode may be made of a low resistive layer which is different from the charge storage layer 106. In this case, the low resistive layer may be electrically connected to the charge storage layer 106 directly or connected indirectly via another low resistive layer.
[0080] The method of injecting electrons to the charge storage layer 106 may be similar to that of the first embodiment.
[0081] FIG. 4(b) is a drawing illustrating the horizontal projection and the cross-sectional views along A-A and B-B in the third embodiment. Different from the second embodiment, since the insulating film 107 and the control electrode 108 are stacked above the entire surface of the charge storage layer 106. Similarly to in the second embodiment, a main part of the charge storage layer 106 in the cell isolation region 116 is formed over the insulating film 201 except for the closest vicinity of the cell region. Thus, the parasitic capacitance between the charge storage layer 106 in the cell isolation region 116 and the GaN layer 103 becomes sufficiently smaller than the capacitance of the capacitor 113 between the charge storage layer 106 in the cell region and the AlGaN layer 104. In addition, the overlapping area of the charge storage layer 106 and the control electrode 108 is sufficiently larger than the overlapping area of the charge storage layer 106 in the cell region and the AlGaN layer 104. Therefore, even though the insulating film 107 is thicker than the insulating film 105, the capacitance of the capacitor 114 is able to be larger than that of the capacitor 113. The other features may be similar to those in the second embodiment.
[0082] FIG. 4(c) is a drawing illustrating the horizontal project of the fourth embodiment. The basic structure of the cell in the present embodiment is the same as that of the second embodiment shown in FIG. 4(a). However, the source and drain electrodes 109 and 110 are configured by a plurality of fingers in the present embodiment. The charge storage layer 106 is meanderingly laid between the fingers of the source and drain electrodes 109 and 110. This layout design enables the large current switching. The capacitor 114 comprising the charge storage layer 106 and the control electrode 108 is configured over the cell isolation region 116 similar to the second embodiment. Furthermore, the configuration related to the area of the capacitor 114, the thickness and material of the insulating film 107, etc., are also similar to those described for the second embodiment.
[0083] In the fourth embodiment shown in FIG. 4(c), the capacitor 114 configured in the cell isolation region is formed of the charge storage layer 106 extending from the cell region, which serves as the bottom electrode of the capacitor. However, it may also be preferred that the bottom electrode is made of a low resistive layer different from the charge storage layer 106. In this case, the low resistive layer may be electrically connected to the charge storage layer 106 directly, or connected indirectly via another low resistive layer.
[0084] The capacitor 114 may also be three-dimensionally stacked above the cell region. In that case, a portion of the cell isolation region to be occupied by the capacitor 114 is saved. Therefore, the total size of the cell can be miniaturized. In addition, the capacitor 114 may also be replaced with an externally equipped capacitor outside the substrate 101 on which the cell is fabricated. In this case, the area of cell to be fabricated on the substrate 101 may also be reduced.
[0085] FIG. 4(d) is a drawing illustrating the horizontal projection of the fifth embodiment of the present disclosure. The basic structure of the cell in the present embodiment is the same as that of the third embodiment shown in FIG. 4(b). However, the source and drain electrodes 109 and 110 are configured by a plurality of fingers in the present embodiment. The charge storage layer 106 and the control electrode 108 are meanderingly laid between the fingers of the source and drain electrodes 109 and 110. This layout design enables the large current switching. The insulating film 107 and the control electrode 108 are stacked on the entire surface of the charge storage layer 106 similar to the third embodiment. Furthermore, even if the insulating film 107 is thicker than the insulating film 105, the capacitance of the capacitor 114 is able to be larger than that of the capacitor 113. This is also similar to the third embodiment.
[0086] FIG. 4(e) is a drawing illustrating the sixth embodiment of the present disclosure. This embodiment is obtained by adding a field plate 130 to the second embodiment shown in FIG. 4(a). The other part is the same as the second embodiment. The field plate 130 is almost same in potential as the source electrode 109, and suppresses concentration of the electric field on the drain side edge of the charge storage layer 106 even when a high voltage is applied to the drain electrode 110 during the stand-by with the voltage applied to the control electrode 108 being 0 V. Consequently, it may be able to restrain the potential difference from being locally enhanced between the charge storage layer 106 and the AlGaN layer 104. Then, the stored charge 115 may hardly leak from the charge storage layer 106. Thus, the aging change of threshold voltage may be suppressed.
[0087] FIG. 4(f) is a drawing illustrating the seventh embodiment. In the present embodiment, a field plate 130 is added to the third embodiment shown in FIG. 4(b). The rests are the same as the third embodiment. The field plate 130 is almost the same in potential as the source electrode 109. This suppresses concentration of the electric field on the drain side edge of the charge storage layer 106 even when a high voltage is applied to the drain electrode 110 during the stand-by with the voltage to be applied to the control electrode 108 being 0V. Consequently, it may be able to restrain the potential difference from being locally enhanced between the charge storage layer 106 and the AlGaN layer 104. Then, the stored charge 115 may hardly leak from the charge storage layer 106. Thus, the aging change of threshold voltage may be suppressed.
[0088] FIG. 5(a) is a drawing illustrating the eighth embodiment. This embodiment is that of the second invention of the present disclosure. The buffer layer 102, the GaN layer 103, the AlGaN layer 104 are in turn grown on the substrate 101. The substrate 101 and the buffer layer 102 may be made of the same materials as those in the prior art shown in FIG. 7. Next, the insulating film 117, the charge storage insulating film 118, and the insulating film 119 may be in turn deposited on the AlGaN layer 104, and then the control electrode 108 is formed over them. Furthermore, the source and drain electrode 109 and 110 are formed on the AlGaN layer 104. It is preferred that the thickness of the AlGaN layer 104 is 10 nm or more on both sides of the control electrode 108 between the source electrode 109 and the control electrode 108, and between the drain electrode 110 and the control electrode 108. A sufficient quantity of conduction electrons may be induced in a conductive channel 111 at the interface AlGaN/GaN to reduce the resistivity of those regions. It may be preferred to tune the alloy composition in the AlGaN layer 104, that is, the value of x in the chemical formula Al.sub.xGa.sub.1-xN, in order to avoid an excessive relaxation of lattice in AlGaN having the lattice constant different from GaN. Usually, x may be ranging from 0.1 to 0.4. The charge storage insulating film 118 may be made of a material having a band gap smaller than that of the insulating films 117 and 119 that sandwich the charge storage insulating film 118 and/or having plenty of traps whose energy levels are inside the band gap of the insulating films 117 and 119. Accordingly, it may be able to store sufficient quantity of charge in the charge storage insulating film 118, and the charge once having been stored in the charge storage insulating film 118 may hardly leak.
[0089] As shown in FIG. 5(b), the threshold voltage of FETs is determined by the stored charge in the charge storage insulating film 118. The threshold voltage becomes higher as more negative charge is stored. Accordingly, the threshold voltage may be able to be more than 3V if a certain quantity of negative charge is stored in the charge storage insulating film 118. Thus, an FET with a sufficient normally-off state is obtained.
[0090] FIG. 5(c) is a drawing illustrating the band diagram of insulating films and semiconductor layers beneath the control electrode 108. In this band diagram, no voltage is applied to the control electrode 108. In the case that a sufficient quantity of negative charge is stored in the charge storage insulating film 118, the potential energy of the charge storage insulating film 118 is elevated and the conduction band edge 121 of the GaN layer 103 becomes higher in energy than the Fermi level (E.sub.F) 123 at the interface between the AlGaN layer 104 and the GaN layer 103. Accordingly, the conduction electrons are restrained from being induced there. That is, the threshold voltage may be positive as shown in FIG. 5(b).
[0091] FIG. 5(d) is a drawing illustrating the band diagram where a positive gate voltage 125 (labeled V in the figure) is applied to the control electrode 108. The conduction band edge 121 is below the Fermi level 123 at the interface between the AlGaN layer 104 and the GaN layer 103. Conduction electrons may be induced there the electric current may flow through the conductive channel 111.
[0092] In the present embodiment, the transistor may be made normally-off by storing negative charge in the charge storage insulating film 118 without thinning a portion of the AlGaN layer 104 to form the control electrode 108. Therefore, it is free from a problem of the dispersion of cell characteristics such as threshold variation etc., like those in the prior art due to the residual thickness dispersion after etching the AlGaN layer 104. Furthermore, as shown in FIG. 5(d), the trap levels 124 are above the Fermi level 123 at the interface between the insulating film 117 and the AlGaN layer 104 because the AlGaN layer 104 is sufficiently thick in the portion under the control electrode 108. This may prevent the hindrance of inducing conduction electrons in the conductive channel 111 by applying a voltage to the control electrode 108 from happening.
[0093] In the present embodiment, the AlGaN layer 104 is not etched under the control electrode 108. However, it may also be preferred that the AlGaN layer 104 is etched to become thinner to some extent. For example, analogically to FIG. 7, which is a prior art, the insulating film 117, the charge storage insulating film 118, the insulating film 119, the control electrode 108 and so forth may be buried in the recessed etching portion formed in the AlGaN layer 104. Even in this case, the residual thickness of the AlGaN layer 104 may be sufficient to suppress the dispersion of cell characteristics such as threshold voltage etc. The influence of trap levels may also be avoided.
[0094] A method of injecting negative charge into the charge storage insulating film 118 is that a positive or negative voltage is applied to the control electrode 108 while the potentials of the source and drain electrodes 109 and 110 are 0V. Thus, high potential differences are given between the control electrode 108 and the source and drain electrodes 109 and 110. If the control electrode 108 is highly positive in potential, electrons in the AlGaN layer 104 may be able to tunnel through the insulating film 117 above the AlGaN layer and be injected into the charge storage insulating film 118. Alternatively, if the control electrode 108 is sufficiently negative in potential, electrons may be able to tunnel from the control electrode 108 to the charge storage insulating film 118 on the contrary. The charge storage insulating film 118 is covered by the insulating films 117 and 119, and electrons stored therein may also be trapped by charge traps whose energy levels are inside band gap of both insulating films 117 and 119. Thus, those electrons having been once trapped may not leak and thus be stored therein. As shown in FIG. 5(b), the threshold voltage may be positive if the quantify of the stored charge in the charge storage insulating film 118 exceeds a certain value. Thus, a normally-off FET is obtained.
[0095] Another method of injecting negative charge into the charge storage insulating film 118 is that the FET is turned on by giving a certain positive potential to the control electrode 108 while the source electrode is given 0 V and a certain positive potential is given to the drain electrode 110. Thus, some of the electrons transporting through the conductive channel 111 may attain high energy at the edge portion of the control electrode 108 on the drain electrode 110 side, where the horizontal electric field becomes high enough. A portion of those high energy electrons may change their direction of transport due to scattering with GaN inside the conductive channel 111 and be injected to the charge storage insulating film 118 through the surface of AlGaN 112 and the insulating film 117. This process may be repeated in the opposite direction, i.e. the drain electrode 110 is given 0 V and the source electrode 109 is given a certain positive voltage, while the control electrode 108 is positive in potential. Thus, the FET is turned on. In a similar manner, high energy electrons may be injected to the charge storage insulating film 118 at the edge of the control electrode 108 on the source electrode 109 side. If the quantity of injected electrons in the charge storage insulating film 118 exceeds a certain value, the threshold voltage becomes positive and then a normally-off FET may be obtained. The above mentioned electron injection scheme may be performed either on the source side, the drain side, or both sides.
[0096] The charge storage insulating film 118 may be, for example, silicon nitride. The insulating films 117 and 118 may be, for example, silicon oxide. The silicon nitride has plenty of charge traps and the energy levels of those traps are inside the band gap of the silicon oxides sandwiching the silicon nitride. The insulating film 117 may also be preferred to be a multilayer of a plurality of different types of insulating films. For example, it may be a multilayer of aluminum oxide and silicon oxide, or a multilayer of silicon nitride and silicon oxide.
[0097] Another method of injecting charge to the charge storage insulating film 118 is that the surface of FET is irradiated by a light. The light may penetrate through the control electrode 108, the insulating film 119, the charge storage insulating film 118, and the insulating film 117, and reach the interface between the AlGaN layer 104 and the GaN layer 103. In the case that a positive high voltage is given to the control electrode 108, electrons in the GaN layer 103 may absorb the light energy that increases the injection rate from the GaN layer 103 to the charge storage insulating film 118. Similarly, in the case that a negative potential is given to the control electrode 108, the control electrode 108 is irradiated with the light which is absorbed by electrons in the control electrode 108. Thus, the rate for those electrons to be injected from the control electrode 108 to the charge storage insulating film 118 may increase. In the case that the electron injection is executed after package sealing, a portion of the package may be formed of a transparent component, through which the light is irradiated.
[0098] The nitride semiconductor FET of the present embodiment is promising as a power switching device to be used in the power supply circuits etc., and is also preferably used as a high frequency transistor. In this embodiment, the control electrode 108 is identical to the electrode usually called gate electrode in high frequency transistors. The FET is normally-off, that is, executes the enhancement type operation. Then, voltages applied to the gate and drain electrodes are both positive. Thus, the transistors may be able to operate with a positive single power supply, and the power supply is simplified. Furthermore, since the AlGaN layer 104 under the control electrode 108 (serving as the gate electrode) is thick, the dispersion of threshold voltage is small. In addition, the trap levels 124 at the interface between the insulating film 117 and the AlGaN layer 104 become less influential. Consequently, a high frequency transistor which is excellent in trans-conductance, maximum drain current, etc., may be obtained.
[0099] FIG. 5(e) is a drawing illustrating the horizontal projection of FET which is an example of the eighth embodiment shown in FIG. 5(a). The source and drain electrodes 109 and 110 are configured by a plurality of fingers. The control electrode 108 is laid meanderingly between those fingers of the source and drain electrodes 109 and 110. This configuration enables the large current switching operation. The control electrode 108 is connected to a control voltage supplying pad 301 located in the cell isolation region 116.
[0100] FIG. 5(f) is the 2-dimensional device simulation result that shows the gate voltage (Vgs) dependence of the drain current (Id) in the FET according to the eighth embodiment shown in FIG. 5(a). The drain voltage Vds is 10V. The gate length of the control electrode 108 is 1 m. The distance between the source and control electrodes 109 and 108 is 1 m. The distance between the control and drain electrodes 108 and 110 is 10 m. This asymmetric configuration is for improving the breakdown voltage of the cell in the case that a high voltage is applied to the drain electrode 110 during stand-by where the control electrode 108 is 0 V. The insulating film 117 is silicon oxide with the thickness being 10 nm. The charge storage insulating film 118 is silicon nitride with the thickness being 5 nm. The insulating film 119 is silicon oxide with the thickness being 15 nm. The negative charge stored in the charge storage insulating film 118 is assumed to be homogenously distributed inside the film. In addition, the AlGaN layer 104 is 10 nm in thickness. The alloy composition ratio, i.e., x, in the chemical formula AL.sub.xGa.sub.1-xN is assumed to be 0.3. The three curved lines shown in FIG. 5(f) are plots with negative charge density of the insulating film 118 being 010.sup.19 cm.sup.3, 110.sup.19 cm.sup.3, and 210.sup.19 cm.sup.3, respectively, from the left. In the case that the negative charge is zero in the charge storage insulating film 118, it is shown that the threshold voltage of transistor is about 5 V and the transistor shows the normally-on characteristic. However, the threshold voltage moves toward the positive direction as the negative charge density in the charge storage insulating film 118 is increased. At 210.sup.19 cm.sup.3, the threshold voltage is about 3V and sufficient normally-off characteristic is realized. FIG. 5(g) is a plot of gate voltage (Vgs) dependence of transconductance (Id/Vggm). The threshold voltage moves toward the positive direction with no reduction of gm peak as the negative charge is stored in the charge storage insulating film 118. Therefore, a normally-off transistor can be obtained with no degradation of the basic properties.
[0101] FIG. 5(h) shows the ninth embodiment. This embodiment is obtained by adding a field plate 130 to the eighth embodiment shown in FIG. 5(a). In addition, the distance between the control electrode 108 and the drain electrodes 110 may be longer than that between the control electrode 108 and the source electrode 109 to improve the breakdown voltage between the control electrode 108 and the drain electrode 110. The rest may be the same as that shown in the eighth embodiment. The field plate 130 is assumed to be almost the same in potential as the source electrode 109. Accordingly, even when a high voltage is applied to the drain electrode 110 during stand-by where the control electrode 108 is given 0 V, the field concentration at the drain edge of the charge storage insulating film 118 is suppressed. Consequently, the stored charge hardly leaks from the charge storage insulating film. Thus, the aging change of threshold voltage is significantly reduced.
[0102] FIG. 6(a) shows the tenth embodiment. FIG. 6(a) is the cross-sectional view of the cell region, where two FETs 601 and 602 are arrayed in series on a same cell region on the AlGaN layer 104. The source electrode 109 adjoins the FET 601 and the drain electrode 110 adjoins the FET 602. Those FETs 601 and 602 are made of same materials and formed in the similar manner as that of the first and third embodiments. FIG. 6(a) is a drawing illustrating the case in which FET 601 and FET 602 are formed according to the first embodiment. Here, in FET 601, the threshold voltage is made positive by sufficiently storing negative charge 115 to the charge storage layer 106. In FET 602, the threshold voltage is negative by insufficiently storing negative charge 115 to the charge storage layer 106. In addition, two gate electrodes 108 are given same or almost same potentials. By serially connecting those FETs, the potential of the AlGaN layer 104 is lowered between FET 602 and FET 601 even when a high voltage is applied to the drain electrode 110 during stand-by where the gate electrode 108 is 0V. Accordingly, there is no excessive potential difference between the charge storage layer 106 of FET 601 and the AlGaN layer 104 underneath. This makes it difficult for the stored charge 115 to leak from the charge storage layer 106 and thus suppresses the aging change of threshold voltage.
[0103] In the tenth embodiment shown in FIG. 6(a), the configuration of FET 601 and FET 602 may be made similar to that of the eighth embodiment. In this embodiment, the charge storage layer 106 of FET 601 and FET 602 are replaced with the charge storage insulating film 118. Then, in the FET 601, a sufficient quantity of negative charge is stored in the charge storage insulating film 118 to make the threshold voltage positive. Additionally, in the FET 602, an insufficient quantity of negative charge is stored in the charge storage insulating film 118 to make the threshold voltage of the FET 602 negative. In this case, by serially connecting the two FETs, stored charge hardly leaks from the charge storage insulating film 118 of the FET 601.
[0104] FIG. 6(b) illustrates the eleventh embodiment. FIG. 6(b) is the cross-sectional view in the cell region, where two FETs 601 and 602 are serially arrayed in a same cell region on the AlGaN layer 104. The source electrode 109 adjoins the FET 601 and the drain electrode 110 adjoins the FET 602. The difference from the tenth embodiment is that the insulating film 107 does not exist in the FET 602 and the charge storage layer 106 and the control electrode 108 are electrically connected therein. The others are structurally identical to those in the tenth embodiment. The charge storage layer 106 under the control electrode 108 in FET 602 may not serve as a floating gate. As a result, the voltage dependence of on-current is more easily controlled by the control electrode 108. In FIG. 6(b), the gate electrode of FET 602 is configured of a metallic layer identical to the gate electrode of FET 601, that is, the metallic layers where the charge storage layer 106 and the control electrode 108 are directly stacked. However, it may be also preferable that the gate electrode of FET 602 is configured of a single metallic layer or multi-metallic layers, which is different from the charge storage layer 106 and the control electrode 108.
[0105] In the eleventh embodiment shown in FIG. 6(b), it may also be preferred that the configuration of the FET 601 is similar to that of the eighth embodiment. In this embodiment, the charge storage layer 106 of the FET 601 is replaced by the charge storage insulating film 118. Then, a sufficient quantity of negative charge may be stored there to make the threshold voltage positive. Additionally, in the FET 602, neither the charge storage layer 106 nor the charge storage insulating film 118 is adopted. Then, the control electrode 108 may be formed directly on the insulating film 105. Moreover, the control electrode 108 of the FET 602 may be formed of a metallic layer different from the control electrode 108 of the FET 601.
[0106] FIG. 6(c) shows the twelfth embodiment. FIG. 6(c) is the cross-sectional view in the cell region, where the two FETs 601 and 602 are serially arrayed in a same cell region on the AlGaN layer 104. The source electrode 109 adjoins the FET 601 and the drain electrode 110 adjoins the FET 602. The difference from the tenth and eleventh embodiments are that neither two insulating films 105 nor 107 exists in the FET 602. Additionally, the charge storage layer 106 and the control electrode 108 are electrically connected. The rest are structurally identical to those of the tenth and eleventh embodiments. The charge storage layer 106 under the control electrode 108 of the FET 602 does not serve as a floating gate. Additionally, since the insulating film 105 does not exist, the voltage dependence of on-current may be further improved and more easily controlled by the control electrode 108. In FIG. 6(c), the gate electrode of the FET 602 is configured of a metallic layer identical to the gate electrode of the FET 601, that is, it is configured of the metallic layers where the charge storage layer 106 and the control electrode 108 are directly stacked. However, it may also be preferred that the gate electrode of the FET 602 is configured of a single metallic layer or multi-metallic layers, which are different from the charge storage layer 106 and the control electrode 108.
[0107] In the twelfth embodiment shown in FIG. 6(c), the configuration of the FET 601 may be similar to that of the eighth embodiment. In this embodiment, the charge storage layer 106 is replaced by the charge storage insulating film 118. Then, a sufficient quantity of negative charge is stored there for the threshold to be positive. Additionally, in the FET 602, neither the charge storage layer 106 nor the charge storage insulating film 118 is adopted and the control electrode 108 may be formed directly on the AlGaN layer 104. Moreover, the control electrode 108 of the FET 602 may be formed of a different metallic layer from the control electrode 108 of the FET 601.
[0108] FIG. 6(d) is a drawing illustrating the horizontal projection related to the tenth, the eleventh, and the twelfth embodiments shown in FIG. 6(a) to (c), respectively. The source electrode 109 and the drain electrode 110 are configured of a plurality of fingers. The FET 601 and the FET 602 are laid meandering between those fingers of the source electrode 109 and drain the electrode 110. Thus, a large current switching is enabled. Additionally, the control electrodes 108 of the FET 601 and the FET 602 may be preferably electrically connected with each other in the cell region or in the cell isolation region. Alternatively, they may be supplied with voltage independently from the external. FIG. 6(d) shows the case in which the control electrodes 108 of both the FET 601 and the FET 602 are connected to the control voltage supplying pad 603 located in the cell isolation region 116.
[0109] FIG. 6(e) shows the thirteenth embodiment. The present embodiment is obtained by adding a field plate 610 to the tenth embodiment on the side of the drain electrode 110 above the control electrode 108. The rest are identical to those of the tenth embodiment. The field plate 610 is almost the same in potential as the source electrode 109. Thus, the field concentration at the drain edge of the FET 602 is suppressed when a high voltage is applied to the drain electrode 110 during the stand-by that the control electrode 108 is 0 V. This may be able to improve the breakdown voltage of the FET 602. The field plate may also be able to improve the breakdown voltage of the FET 602 in the eleventh and twelfth embodiments by adding it in a similar manner.
[0110] In the above-mentioned embodiments, the nitride semiconductors are assumed to be GaN and AlGaN. The band gap of AlGaN is larger than that of GaN. Therefore, a conductive channel is formed on the side of GaN at the interface between AlGaN and GaN. This channel is used in the above-mentioned embodiments. It may also be preferred to use nitride semiconductors different from GaN and AlGaN. For example, nitride semiconductor including Indium such as InN, InGaN, InAlN and so forth, are also preferable. The materials and composition ratio are to be selected so as to form a layer having wider band gap above that having narrower band gap.
[0111] In addition, in order to protect the surface of the second nitride semiconductor, another nitride semiconductor having different composition may be inserted above. For example, in the case that the first nitride semiconductor is GaN and the second semiconductor is AlGaN, a thin GaN layer may be inserted on AlGaN.
[0112] The nitride semiconductor transistor devices according to the present disclosure may be useful to serve mainly as power switches to be used in power supply circuits, etc. In addition, they may also be useful to serve as high frequency transistors to be used in wireless communication, sensor and so forth.
