CHECKER AND CHECKING METHOD FOR PROSSOR CIRCUIT

Abstract

The present disclosure provides a checker and a checking method for a processor circuit. The checking method includes: determining whether a data cache send a data refill request under a branch prediction executing status for obtaining a first result; determining whether data requested by the data refill request is written into a register and calculated under the branch prediction executing status for obtaining a second result; and determining whether the processor circuit has a vulnerability according to the first result and the second result.

Claims

1. A checking method for use in a processor circuit, the processor circuit comprising an out-of-order execution and branch prediction unit, and the checking method comprising: determining whether a data cache sends a data refill request under a branch prediction execution status for obtaining a first determination result; determining whether a data requested by the data refill request is written into a register and calculated under the branch prediction execution status for obtaining a second determination result; and determining whether the processor circuit has vulnerability according to the first determination result and the second determination result.

2. The checking method of claim 1, wherein when the first determination result is that the data cache sends the data refill request under the branch prediction execution status, and the second determination result is that the first data is written into the register and calculated under the branch prediction execution status, determining that the processor circuit has vulnerability.

3. The checking method of claim 1, further comprising: determining a cache miss happens in the data cache under the branch prediction execution status.

4. The checking method of claim 3, wherein the step of determining whether the data cache sends the data refill request under the branch prediction execution status further comprises: determining whether a miss status holding register (MSHR) of the data cache sends the data refill request under the branch prediction execution status for obtaining the first determination result.

5. The checking method of claim 4, wherein the step of determining whether the MSHR of the data cache sends the data refill request under the branch prediction execution status further comprises: determining whether the MSHR of the data cache sends the data refill request to a next level memory under the branch prediction execution status for obtaining the first determination result.

6. The checking method of claim 5, wherein the next level memory comprises a second level cache (L2 cache) or a bus-connected memory.

7. The checking method of claim 1, wherein the step of determining whether the data requested by the data refill request is written into the register and calculated under the branch prediction execution status further comprises: determining whether the data requested by the data refill request is written into the register from the data cache under the branch prediction execution status; and determining whether the data of the register is calculated under the branch prediction execution status for obtaining the second determination result.

8. The checking method of claim 7, wherein the step of determining whether the data requested by the data refill request is written into the register from the data cache under the branch prediction execution status further comprises: determining whether a load-store unit writes the data requested by the data refill request into the register from the data cache under the branch prediction execution status.

9. The checking method of claim 8, wherein the step of determining whether the data of the register is calculated under the branch prediction execution status further comprises: determining whether a calculation unit accesses the data of the register under the branch prediction execution status for obtaining the second determination result.

10. The checking method of claim 1, wherein the branch prediction execution status is recorded in a reorder buffer.

11. A checker for use in a processor circuit, the processor circuit comprising an out-of-order execution and branch prediction unit, and the checker comprising: a first checking module, configured to determine whether a data cache of the processor circuit sends a data refill request under a branch prediction execution status for obtaining a first determination result; a second checking module, configured to determine whether a data requested by the data refill request is written into a register of the processor circuit and calculated under the branch prediction execution status for obtaining a second determination result; and a determination module, configured to determining whether the processor circuit has vulnerability according to the first determination result and the second determination result.

12. The checker of claim 11, wherein when the first determination result is that the data cache sends the data refill request under the branch prediction execution status, and the second determination result is that the first data is written into the register and calculated under the branch prediction execution status, the determination module determines that the processor circuit has vulnerability.

13. The checker of claim 11, wherein the first checking module is further configured to: Determining a cache miss happens in the data cache under the branch prediction execution status.

14. The checker of claim 13, wherein the first checking module is further configured to: determining whether a miss status holding register (MSHR) of the data cache sends the data refill request under the branch prediction execution status for obtaining the first determination result.

15. The checker of claim 14, wherein the first checking module is further configured to: determine whether the MSHR of the data cache sends the data refill request to a next level memory under the branch prediction execution status for obtaining the first determination result.

16. The checker of claim 15, wherein the next level memory comprises a second level cache (L2 cache) or a bus-connected memory.

17. The checker of claim 11, wherein the second checking module is further configured to: determine whether the data requested by the data refill request is written into the register from the data cache under the branch prediction execution status; and determine whether the data of the register is calculated under the branch prediction execution status for obtaining the second determination result.

18. The checker of claim 18, wherein the second checking module is further configured to: determine whether a load-store unit writes the data requested by the data refill request into the register from the data cache under the branch prediction execution status.

19. The checker of claim 18, wherein the second checking module is further configured to: determine whether a calculation unit accesses the data of the register under the branch prediction execution status for obtaining the second determination result.

20. The checker of claim 11, wherein the branch prediction execution status is recorded in a reorder buffer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] FIG. 1A is a block diagram illustrating a checker according to some embodiments of the present disclosure.

[0009] FIG. 1B is a block diagram illustrating a checker according to some embodiments of the present disclosure.

[0010] FIG. 2A is a block diagram illustrating a checker according to some embodiments of the present disclosure.

[0011] FIG. 2B is a block diagram illustrating a checker according to some embodiments of the present disclosure.

[0012] FIG. 3 is a flowchart of a checking method according to some embodiments of the present disclosure.

[0013] FIG. 4 is a flowchart of a checking method according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

[0014] Embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

[0015] Reference is made to FIG. 1A, which is a block diagram illustrating a checker 1 according to certain embodiments of the present disclosure. The checker 1 is configured to check whether a processor circuit 9 has a vulnerability (such as spectre attack). In certain embodiments, the processor circuit 9 includes an out-of-order execution and branch prediction unit 91, a register 93 and a data cache 95. The out-of-order execution and branch prediction unit 91 is configured to decode instructions and execute the decoded instructions out-of-order. The out-of-order execution and branch prediction unit 91 is capable of branch prediction and can record a branch prediction status, such as: branch prediction execution status (branch prediction unresolved status) and branch prediction non-execution status (branch prediction resolved status).

[0016] In certain embodiments, the checker 1 includes a first checking module 11, a second checking module 13 and a determination module 15. Specifically, the first checking module 11 is configured to determine whether the data cache 95 of the processor circuit 9 sends a data refill request under the branch prediction execution status for obtaining a first determination result. The second checking module 13 is configured to determine whether a data requested by the data refill request is written into the register 93 of the processor circuit 9 and calculated under the branch prediction execution status for obtaining a second determination result. The determination module 15 is configured to determining whether the processor circuit 9 has a vulnerability according to the first determination result and the second determination result.

[0017] Reference is made to FIG. 1B. In certain embodiments, when the first checking module 11 determines that the data cache 95 of the processor circuit 9 sends a data refill request 950 under the branch prediction execution status, then the second checking module 13 further determines whether the data requested by the data refill request 950 is written into the register 93 of the processor circuit 9 and calculated under the branch prediction execution status. When the second checking module 13 determines that a data. 952 requested by the data refill request 950 is written into the register 93 of the processor circuit 9 and calculated under the branch prediction execution status, then the determination module 15 determines that the processor circuit 9 may have vulnerability according to the above-mentioned checking results of the first checking module 11 and the second checking module 13.

[0018] In certain embodiments, when: (1) the first checking module 11 determines that the data cache 95 of the processor circuit 9 does not send any data refill request under the branch prediction execution status; (2) when the second checking module 13 determines that the data 952 requested by the data refill request 950 is not written into the register 93 of the processor circuit 9 under the branch prediction execution status; or (3) when the second checking module 13 determines that the data 952 is not calculated under the branch prediction execution status, then the determination module 15 determines that the processor circuit 9 may not have a vulnerability according to the above-mentioned checking results of the first checking module 11 and the second checking module 13.

[0019] It should be noted that, in certain embodiments, the above-mentioned processor circuit and checker can include a hardware circuit, so that data and signals are transmitted via the electrical connection between components of the processor circuit (such as the out-of-order execution and branch prediction unit, the register and the data cache) and components of the checker (the first checking module, the second checking module and the determination module). In certain embodiments, the signal and data transmission between the above-mentioned processor circuit, checker and components can be simulated using a software, such as, Electronic Design Automation (EDA).

[0020] Reference is made to FIG. 2A, which is a block diagram illustrating a checker 2 according to certain embodiments of the present disclosure. The checker 2 is configured to check whether a processor circuit 8 has a vulnerability. In certain embodiments, the processor circuit 8 includes: an out-of-order execution and branch prediction unit 81, a register 83, a data cache 85, a load-store unit 87 and a calculation unit 89. The out-of-order execution and branch prediction unit 81 is configured to decode instructions and execute the decoded instructions out-of-order. The out-of-order execution and branch prediction unit 81 is capable of branch prediction and can record the branch prediction status (such as: the branch prediction execution status and the branch prediction non-execution status) in a reorder buffer 811. The data cache 85 has a miss status holding register (MSHR) 851.

[0021] In certain embodiments, the checker 2 includes a first checking module 21, a second checking module 23 and a determination module 25. Specifically, the first checking module 21 is configured to determine whether a cache miss happens in the data cache 85 of the processor circuit 8 under the branch prediction execution status. Because of the cache miss, it is possible that a data refill request is generated. The first checking module 21 is configured to determine whether the MSHR 851 of the data cache 85 sends a data refill request to a next level memory 7 (such as: a second level cache L2 cache, a bus-connected memory, etc.) under the branch prediction execution status for obtaining a first determination result.

[0022] The second checking module 23 is configured to determine whether the load-store unit 87 writes a data requested by the data refill request into the register 83 under the branch prediction execution status and determine whether the calculation unit 89 accesses the data of the register 83 under the branch prediction execution status for obtaining a second determination result. The determination module 25 is configured to determining whether the processor circuit 8 has a vulnerability according to the first determination result and the second determination result.

[0023] Reference is made to 2B. In certain embodiments, when the first checking module 21 determines that the cache miss happens the data cache 85 of the processor circuit 8 under the branch prediction execution status, and determines that the data cache 85 of the processor circuit 8 sends a data refill request 850 under the branch prediction execution status, then the second checking module 23 further determines whether the data requested by the data refill request 850 is written into the register 83 of the processor circuit 8 and calculated under the branch prediction execution status.

[0024] More specifically, when the second checking module 23 determines that the load-store unit 87 writes a data 852 requested by the data refill request 850 from the data cache 85 into the register 83 of the processor circuit 8 under the branch prediction execution status, and determines that the calculation unit 89 accesses the data 852 of the register 83 under the branch prediction execution status, then the determination module 25 determines that the processor circuit 8 may have a vulnerability according to the above-mentioned checking results of the first checking module 21 and the second checking module 23.

[0025] In certain embodiments, when: (1) the first checking module 21 determines that the data cache 85 of the processor circuit 8 does not send any data refill request under the branch prediction execution status; (2) when the second checking module 23 determines that the load-store unit 87 does not write the data 852 requested by the data refill request 850 into the register 83 of the processor circuit 8 under the branch prediction execution status; or (3) when the second checking module 23 determines that calculated unit 89 does not access the data 852 under the branch prediction execution status, then the determination module 25 determines that the processor circuit 8 may not have a vulnerability according to the above-mentioned checking results of the first checking module 21 and the second checking module 23.

[0026] In certain embodiments, in addition to the reorder buffer 811, the out-of-order execution and branch prediction unit 81 of the processor circuit 8 may further include: an instruction fetch/branch prediction unit, an instruction decode unit and a register renaming/dispatch/retire unit.

[0027] It should be noted that, whether the various aforementioned operations are performed in the branch prediction execution status can be determined according to the data of the reorder buffer 851 at the time when the operations are performed. In addition, in certain embodiments, the above-mentioned processor circuit, checker and next level memory can include hardware circuit, so that data and signals are transmitted via the electrical connection between components of the processor circuit (such as the out-of-order execution and branch prediction unit, the register, the data cache, the load-store unit, the calculation unit), components of the checker (the first checking module, the second checking module and the determination module) and the next level memory. In certain embodiments, the signal and data transmission between the above-mentioned processor circuit, checker and components can be simulated using a software, such as, EDA.

[0028] Certain embodiments of the present disclosure include a checking method for use in a processor circuit, and a flowchart thereof is shown in FIG. 3. The processor circuit includes an out-of-order execution and branch prediction unit. The checking method according to these embodiments is implemented by a checker (such as the checker described in the fore-going embodiments), and detailed operations of the method are discussed below. First, the step S301 is executed to determine whether a data cache of the processor circuit sends a data refill request under a branch prediction execution status for obtaining a first determination result. If the first determination result is negative, then step S304 is executed to determine that the processor circuit does not have a vulnerability. If the first determination result is positive, then step S302 is executed to determine whether a data requested by the data refill request is written into a register and calculated under the branch prediction execution status for obtaining a second determination result. If the second determination result is negative, then the method proceeds to the step S304. If the second determination result is positive, then step S303 is executed to determine that the processor circuit has a vulnerability.

[0029] Certain embodiments of the present disclosure include a checking method for use in a processor circuit, and a flowchart thereof is shown in FIG. 4. The processor circuit includes an out-of-order execution and branch prediction unit. The checking method according to these embodiments is implemented by a checker (such as the checker described in the fore-going embodiments), and detailed operations of the method are discussed below. First, the step S401 is executed to determine whether a cache miss happens in a data cache of the processor circuit under a branch prediction execution status. If not, then the step S401 is repeated.

[0030] If the result in the step S401 is positive, then step S402 is executed to determine whether an MSHR of the data cache sends a data refill request under the branch prediction execution status to a next level memory for obtaining a first determination result. If the first determination result is negative, then step S406 is executed to determine that the processor circuit does not have a vulnerability. If the first determination result is positive, then in step S403 is executed to determine whether a load-store unit of the processor circuit writes the data requested by the data refill request from the data cache into the register under the branch prediction execution status. If not, then the step S406 is executed to determine that the processor circuit does not have a vulnerability.

[0031] If the result in the step S403 is positive, then step S404 is executed to determine whether a calculation unit of the processor circuit accesses the data of the register under the branch prediction execution status for obtaining a second determination result. If the second determination result is negative, then the step S406 is executed to determine that the processor circuit does not have a vulnerability. If the second determination result is positive, then step S405 is executed to determine that the processor circuit has a vulnerability.

[0032] In view of the foregoing, the checkers and checking methods for use in to processor circuits according to embodiments of the present disclosure can use the checking steps to determine whether a specific attack mode of operation (e.g., a spectre attack mode) may exist, so that the processor circuit can be subsequently modified

[0033] While this invention has been described with specific embodiments thereof, it is evident that many alternatives, modifications, and variations may be apparent to those skilled in the art. For example, various components of the embodiments may be interchanged, added, or substituted in the other embodiments. Also, all of the elements of each figure are not necessary for operation of the disclosed embodiments. For example, one of ordinary skill in the art of the disclosed embodiments would be enabled to make and use the teachings of the invention by simply employing the elements of the independent claims. Accordingly, embodiments of the invention as set forth herein are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention.