Method for Determining Material Parameters of a Multilayer Test Sample

Abstract

The multilayer test sample includes a stack with a bottom layer, a top layer, and a tunnel layer sandwiched between the bottom and top layers. The multilayer test sample has terminals below the stack for measuring on the stack. The terminals have unknown positions or distance between them. A model and a measurement strategy is defined so that material parameters of the stack may be determined.

Claims

1. A method for determining material parameters of a multilayer test sample, said method comprising: providing a multilayer test sample, said multilayer test sample comprising: a stack including a bottom layer, a top layer, and a tunnel layer sandwiched between said bottom layer and said top layer, a plurality of test sample terminals for connection with a measurement circuit, said measurement circuit having a plurality of electrodes, and a plurality of stack terminals below or above said stack, such that each of said stack terminals is electrically connected to said bottom layer or said top layer, providing a resistance model representative of said multilayer test sample, said resistance model outputting a resistance value as a function of a set of stack terminal parameters and a set of stack material parameters, providing a plurality of electrically conductive paths, each of said conductive paths electrically interconnecting one of said test sample terminals and one of said stack terminals, contacting said test sample terminals with said electrodes, determining at least six different measured resistance values using six measurements, each of said measured resistance values being determined in one of said measurements by: selecting four different test sample terminals of said plurality of test sample terminals, and dividing said four different test sample terminals into a first pair of test sample terminals and a second pair of test sample terminals, and injecting a current into said multilayer test sample using said first pair of test sample terminals, measuring a voltage induced between said second pair of test sample terminals, and determining each of said measured resistance values as a function of said voltage and said current, for each of said measured resistance values defining a partial error function, said partial error function defining an error between said resistance model and one of said measured resistance values, defining an error function comprising each partial error and defining a total error, and varying each of said set of stack terminal parameters and said set of stack material parameters in each of said resistance models in said error function such that said total error is minimized.

2. The method according to claim 1, further comprising solving said set of equations for said set of stack terminal parameters.

3. The method according to claim 1, where each of said stack terminals has a fixed position.

4. The method according to claim 1, wherein one of said electrodes has a varying position on one of said test sample terminals from one measurement to the next.

5. The method according to claim 1, wherein said resistance model assumes said measured resistance values are independent from positions of said plurality of electrodes on said test sample terminals.

6. The method according to claim 1, comprising landing said plurality of electrodes on said test sample terminals.

7. The method according to claim 1, wherein each of said test sample terminals has a larger area than one of said stack terminals.

8. The method according to claim 1, wherein said error function comprises a term for each of said partial error functions.

9. The method according to claim 1, wherein said error is defined by each of said partial error functions as a difference between said resistance model and one of said measured resistance values.

10. The method according to claim 1, wherein said test sample comprises at least five test stack terminals.

11. The method according to claim 1, said set of stack terminal parameters comprising a distance between stack terminals.

12. The method according to claim 1, wherein said set of stack terminal parameters comprise a position of a stack terminal or a position of each of said stack terminals.

13. The method according to claim 1, wherein said set of stack material parameters comprises a resistance value of said bottom layer and optionally of said top layer and/or said tunnel layer.

14. The method according to claim 1, wherein said multilayer test sample includes an electrically insulating layer.

15. The method according to claim 14, wherein said plurality of electrically conductive paths are embedded in said electrically insulating layer.

16. A method for determining material parameters of a multilayer test sample, said method comprising: providing said multilayer test sample, said multilayer test sample comprising: a stack including a bottom layer, a top layer, and a tunnel layer sandwiched between said bottom layer and said top layer, a plurality of test sample terminals for connection with a measurement circuit, said measurement circuit having a plurality of electrodes, and a plurality of stack terminals below or above said stack, such that each of said stack terminals electrically connected to said bottom layer or said top layer, providing a resistance model representative of said multilayer test sample, said resistance model outputting a resistance value as a function of a set of stack terminal parameters and a set of stack material parameters, providing a plurality of electrically conductive paths, each of said electrically conductive paths electrically interconnecting one of said test sample terminals and one of said stack terminals, contacting said test sample terminals with said electrodes, determining at least six different measured resistance values using six measurements, each of said measured resistance values being determined in a respective measurement by: selecting four different test sample terminals of said plurality of test sample terminals, and dividing said four different test sample terminals into a first pair of test sample terminals and a second pair of test sample terminals, and injecting a current into said test sample using said first pair of test sample terminals, measuring a voltage induced between said second pair of test sample terminals, and determining each of said measured resistance values as a function of said voltage and said current, for each measured resistance value defining a partial error function, said partial error function defining an error between said resistance model and one of said measured resistance values, defining a set of equations, each of said set of equations defining an equality between one of said measured resistance values and said resistance model, and solving said set of equations for said set of stack material parameters.

17. A computer-based system for determining material parameters of a multilayer test sample, said multilayer test sample that includes a stack including a bottom layer, a top layer, and a tunnel layer sandwiched between said bottom layer and said top layer; a plurality of test sample terminals for connection with a measurement circuit; a plurality of stack terminals below or above said stack, such that each of said stack terminals electrically connected to said bottom layer or said top layer; and a plurality of electrically conductive paths, each of said conductive paths electrically interconnecting one of said test sample terminals and one of said stack terminals, said computer-based system comprising: a measurement system arranged for determining at least six different measured resistance values using six measurements, each of said measured resistance values being determined in a respective measurement by: selecting four different test sample terminals of said plurality of test sample terminals, and dividing said four different test sample terminals into a first pair of test sample terminals and a second pair of test sample terminals, and injecting a current into said multilayer test sample using said first pair of test sample terminals, measuring a voltage induced between said second pair of test sample terminals, and determining each of said measured resistance values as a function of said voltage and said current, and a processing unit and a memory, said memory including: a resistance model representative of said multilayer test sample, said resistance model outputting a resistance value as a function of a set of stack terminal parameters and a set of stack material parameters, for each of said measured resistance values said processing unit configured to: define a partial error function, said partial error function defining an error between said resistance model and one of said measured resistance values, define an error function comprising each of said partial errors and defining a total error, and vary each of said set of stack terminal parameters and said material parameters in said resistance model such that said total error is minimized.

18. The method according to claim 16, further comprising solving said set of equations for said set of stack terminal parameters.

19. The method according to claim 16, where each of said stack terminals has a fixed position.

20. The method according to claim 16, wherein one of said electrodes has a varying position on one of said test sample terminals from one measurement to the next.

21. The method according to claim 16, wherein said resistance model assumes said measured resistance values are independent from positions of said plurality of electrodes on said test sample terminals.

22. The method according to claim 16, comprising landing said plurality of electrodes on said test sample terminals.

23. The method according to claim 16, wherein each of said test sample terminals has a larger area than one of said stack terminals.

24. The method according to claim 16, wherein said error function comprises a term for each of said partial error functions.

25. The method according to claim 16, wherein said error is defined by each of said partial error functions as a difference between said resistance model and one of said measured resistance values.

26. The method according to claim 16, wherein said test sample comprises at least five test stack terminals.

27. The method according to claim 16, said set of stack terminal parameters comprising a distance between stack terminals.

28. The method according to claim 16, wherein said set of stack terminal parameters comprise a position of a stack terminal or a position of each of said stack terminals.

29. The method according to claim 16, wherein said set of stack material parameters comprises a resistance value of said bottom layer and optionally of said top layer and/or said tunnel layer.

30. The method according to claim 16, wherein said multilayer test sample includes an electrically insulating layer.

31. The method according to claim 30, wherein said plurality of electrically conductive paths are embedded in said electrically insulating layer.

Description

DESCRIPTION OF THE DRAWINGS

[0049] FIG. 1 shows an exploded view of a test sample.

[0050] FIG. 2 shows a test sample connected to electrodes.

[0051] FIG. 3 shows a schematic perspective view of a computer-based system for measuring a multilayer test sample.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0052] Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined only by reference to the appended claims.

[0053] FIG. 1 shows an exploded view of a test sample.

[0054] The test sample 10 has five layers wherein the top three layers constitute a magnetic tunnel junction (MTJ), i.e. a MTJ stack.

[0055] The test sample may constitute a semiconductor wafer comprising at least two electrically conductive layers and a tunnelling electrically insulating layer sandwiched in the middle, for example an MTJ.

[0056] The top layer 12 of the MTJ stack may or may not contain a ferromagnetic material, but it is electrically conductive.

[0057] The direction of the magnetization of the top layer may be changed.

[0058] A middle layer 14 is sandwiched between the top layer and a bottom layer 16 of the MTJ stack.

[0059] The middle layer is a thin electrically insulator—the thickness of which is not so large that electrons may not tunnel through it, i.e. the middle layer is a tunnelling barrier layer.

[0060] The bottom layer 16 may also or may not contain ferromagnetic materials, but it is electrically conductive.

[0061] Alternatively, the top layer may have a permanent magnetization, and the bottom layer may have a variable direction of the magnetic moments. Both layers may also have a variable direction of the magnetic moments.

[0062] The resistance of the stack when a voltage potential is applied across the stack could depend on if the magnetization of the top and bottom layer are parallel or antiparallel, i.e. if they are parallel, the tunnelling barrier is lower than if the magnetizations are antiparallel.

[0063] The top layer is illustrated with a planar top surface, and the layers are in general illustrated as being parallel to each other.

[0064] The stack may also have more than two conductive layers and one barrier with several electrical properties, which are to be measured.

[0065] Alternatively, the layers of the test sample may have another function than as for a MRAM cell. For example, a stack having only two layers, the purpose of which being a sensor.

[0066] The three layers of the stack are shown as eight islands in FIG. 1, i.e. seven smaller islands next to each other on a row and one larger island by itself (such as a test island constituting an MTJ stack 28 for MRAM or a sensor purpose). This is a result of etchings in the stack layers such that these islands become electrically insulated from each other, i.e. the islands are not electrically connected with each other.

[0067] The removed parts of the layers could also be constituted by oxide material or another material constituting an electrical insulator, i.e. such that the space between the islands themselves, and the space between an island and the MTJ stack is filled with an electrical insulator material.

[0068] The seven smaller islands constitute seven test sample terminals, which may have the purpose of landing pads such as a first landing pad 26 having a first landing area on top of the landing pad (i.e. the exposed surface 30), which is not covered by another layer on top of it—except for possibly a thin oxide layer.

[0069] A test sample terminal may have any in-plane shape. FIG. 1 shows rectangular shapes/areas but the shape may be round, oval, elliptic, polygonal or a random shape.

[0070] Each landing area of each landing pad is for landing a probe tip/electrode, i.e. contacting a probe tip with the landing area such that an electric signal may be injected into the landing pad during a measurement routine, or alternatively, an electric measurement signal may be picked up. In this way, terminals are provided on the test sample for a probe, and for doing a probe measurement with a measurement circuit.

[0071] Instead of using a probe, the test sample may be inserted into a measuring device wherein the measuring terminals have fixed positions aligned with the position of the test sample terminals when the test sample is placed correctly in the measuring device.

[0072] Below the MTJ stack is a fourth layer constituting a first electrically insulating layer 18, i.e. no current is intended to flow freely in that layer without control of the current path.

[0073] Below the fourth electrically insulating layer is the fifth layer constituting a second electrically insulating layer 20.

[0074] The first electrically insulating layer, and the second electrically insulating layer may be made as one electrically insulating layer.

[0075] The first electrically insulating layer has vias such as a first via 22 extending vertically throughout the thickness of the layer.

[0076] Seven vias are located shown under the larger island, which all go into contact with the bottom surface of the bottom layer of the MTJ stack, and constitute terminals for contacting the MTJ stack.

[0077] As an alternative, the stack terminals may contact the top layer from above. It is contemplated that a number of layers may be above the top layer of the stack and that the stack terminals goes through these layers.

[0078] The sample terminals may be in a layer higher than the layer that the stack terminals are in, whether the stack terminals connect to the bottom layer of the stack or the top layer of the stack.

[0079] In the second electrically insulating layer are seven copper lanes, i.e. copper deposited during one of the fabrication steps (another electrically conductive material than copper may be used).

[0080] The copper lanes constitute electrically conductive paths such as a first electrically conductive path 24.

[0081] The electrically conductive paths extend parallel with the layers and each electrically conductive path interconnects a via for one landing pad with one of the vias contacting the MTJ stack.

[0082] One of the electrically insulating layers may also be used for electrically connections leading to for example control electronics such as a switch. The switch itself may be placed in a sixth layer, which may be lower than the electrically insulating layer.

[0083] A landing pad may not necessarily be constituted by three MTJ layers. Alternatively, the landing pad may be a semiconductor material deposited or otherwise created on the first electrically insulating layer as an island which may conduct an electric signal from a probe tip to the via, which contacts the respective landing pad from below.

[0084] Five of the test sample terminals have been designated the letters A to E.

[0085] In FIG. 2, a probe has been placed above the test sample.

[0086] The test sample is shown in a non-exploded view. The vias and electrically conductive paths are illustrated as dotted lines below the top three layers.

[0087] The probe has seven cantilever arms extending parallel to each other. Each cantilever arm ending in a probe tip/electrode such as a first probe tip 32.

[0088] Each respective probe tip has been brought into contact with the landing areas of each respective landing pad, i.e. the first probe tip 32 contacts the first landing pad 26 with the first via 22 contacting the first landing pad from below.

[0089] The probe tip may penetrate a possible oxide layer on top of the landing pad such that an electric contact may be established between the landing pad and the probe tip.

[0090] A probe tip may penetrate the landing pad a small distance so that it not only rests on the surface constituting the landing area.

[0091] The vias and electrically conductive paths enable a circuit path to be completed from one probe tip to another such that a current may be injected into the circuit path and go into the MTJ stack and further to a second probe tip.

[0092] FIG. 3 shows a schematic perspective view of a computer-based system for measuring a multilayer test sample.

[0093] The computer-based system comprises a measurement circuit 42 including a multi-probe measurement setup connected to a stationary computer 44 and/or a laptop for controlling the measurements. The stationary computer 44 and/or a laptop and the sub-systems therein can include any suitable processor (or processing unit) known in the art, such as a parallel processor. In addition, the sub-system(s) or system(s) may include a platform with high speed processing and software, either as a standalone or a networked tool. Program instructions implementing methods such as those described herein may be transmitted over or stored on carrier medium. The carrier medium may include a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid state memory, a magnetic tape, and the like. A carrier medium may include a transmission medium such as a wire, cable, or wireless transmission link. Moreover, different sub-systems of the stationary computer 44 and/or a laptop may include one or more computing or logic systems. Therefore, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration.

[0094] The multi point probe includes the five electrodes designated A-E in FIG. 1, and they are in contact with the multilayer test sample as shown in FIG. 2.

[0095] The multilayer test sample measurement may then begin. As a first step, a model for the resistance of the stack may be defined as:

[00001]$R^i=\frac{R_T{R}_B}{2\pi \left(R_T+R_B\right)}\left\{\frac{R_T}{R_B}\left(K_0\left(\frac{w^i}{\lambda }\right)+K_0\left(\frac{z^i}{\lambda }\right)-K_0\left(\frac{y^i}{\lambda }\right)-K_0\left(\frac{x^i}{\lambda }\right)\right)+\ln \left(\frac{x^i{y}^i}{z^i{w}^i}\right)\right\}$$\lambda =\sqrt{\frac{\mathrm{RA}}{R_T+R_B}}$

[0096] where the index i refers to the different resistance measurements (1-6) and x.sup.i, y.sup.i, z.sup.i and w.sup.i are distances between the five stack terminals below the stack, which are connected to the test sample terminals A-E, in the i configuration for the specific R.sup.i measurement.

[0097] The only electrode interdistance assumed to be known may be the distance between the two outermost stack terminals (connected to test sample terminals A and E respectively). Instead, all the other distances between the stack terminals are to be determined, i.e.

[0098] x.sup.i are unknown and may define the distance between the two stack terminals connected to test sample terminals A and B respectively or other inter electrode distances.

[0099] y.sup.i are unknown and may define the distance between the two stack terminals connected to test sample terminals B and C respectively or other inter electrode distances.

[0100] z.sup.i is unknown and may define the distance between the two stack terminals connected to test sample terminals C and D respectively or other inter electrode distances.

[0101] w.sup.i is unknown and may define the distance between the two stack terminals connected to test sample terminals D and E respectively or other inter electrode distances.

[0102] The unknown material parameters are the top layer sheet resistance RT, the bottom layer sheet resistance RB, and the tunnelling resistance area product RA.

[0103] K.sub.0 is the modified Bessel function of the second kind, O'th order.

[0104] The method assumes that, unlike the prior art, the measured resistance is independent of the landing position of the movable electrodes of the measurement circuit. Thus, the variables/parameters relating to the geometric relation between the electrodes and the test sample terminals do not enter into the resistance model. Instead, the parameters defining the distances between the fixed stack terminals is used to define a relationship between resistance of the test sample R.sup.i and the test sample parameters (R.sub.T, R.sub.B, R.sub.A), and enters the resistance model as (x.sup.i,y.sup.i,z.sup.i,w.sup.i).

[0105] However, depending on the size of the test sample terminals this assumption behind the model in the present disclosure may lead to an error if the test sample terminals become smaller, and necessitating that for example the distances between the test sample terminals (χ, γ, σ, ω) enters the equation (resistance model) as well where χ is known within an error margin and may define the distance between the two electrodes in contact with test sample terminals A and B respectively. γ is known within an error margin and may define the distance between the two electrodes in contact with test sample terminals B and C respectively. σ is known within an error margin and may define the distance between the two electrodes in contact with test sample terminals C and D respectively. ω defines the distance between the electrodes connected to the two outermost test sample terminals (A and E respectively) and is estimated (set as a constant).

[0106] The test sample terminals used in each of the six measurements may be defined as follows:

TABLE-US-00001 Measurement # Voltage pairs Current pairs 1 A, C B, E 2 A, C B, D 3 A, E B, C 4 A, E B, D 5 B, D C, E 6 B, C A, D

[0107] At least one of the pins are to be changed from one measurement to the other.

[0108] Thus, for the first measurement, in a first step, a current is injected into the test sample by the electrodes contacting test sample terminals B and E on FIG. 1 respectively.

[0109] A voltage is measured in a second step by the electrodes contacting test sample terminals A and C on FIG. 1 respectively.

[0110] The resistance may then be determined in a third step by means of Ohm's law from the injected current and measured voltage.

[0111] The above three steps are then repeated with the voltage and current pairs defined in the above table until six measured resistance values have been determined.

[0112] The resistance model has been chosen to approximate or model the measured resistance. The difference or error between a measured resistance and the model may be:

f({circumflex over (p)}, {circumflex over (d)})=R.sub.m−R({circumflex over (p)}, {circumflex over (d)}) [0113] where the vector p are the material parameters R.sub.T, R.sub.B, R.sub.A and the vector d are the distances between the stack terminals used in the measurement. Since these are fixed, but unknown (except one stack interterminal distance which is assumed to be known), there are a total of six unknown parameters in the function f (i.e. three from the sample, three from the fixed stack terminals distances). However, with six measurements six equations may be established and solved for the six unknown parameters.

[0114] Alternatively, for each measured resistance value a (partial) error function may be defined, which defines an error or difference between the (output of the) resistance model and a respective measured resistance value.

[0115] All of the six partial error functions may enter into a (total) error function and each set of stack terminal parameters and the set of stack material parameters in each resistance model in the total error function may be varied such that the total error is minimized.

[0116] The error function defining a total error may be defined as:

∈=|R.sub.m.sup.1−R.sup.1({circumflex over (p)}, {circumflex over (d)}.sup.1)|+|R.sub.m.sup.2−R.sup.2({circumflex over (p)}, {circumflex over (d)}.sup.2)|30 |R.sup.3.sub.m−R.sup.3({circumflex over (p)}, {circumflex over (d)}.sup.3)|+|R.sub.m.sup.3−R.sup.3({circumflex over (p)}, {circumflex over (d)}.sup.3)|+|R.sub.m.sup.4−R.sup.4({circumflex over (p)}, {circumflex over (d)}.sup.4)|+|R.sub.m.sup.5−R.sup.5({circumflex over (p)}, {circumflex over (d)}.sup.5)|+|R.sub.m.sup.6−R.sup.6({circumflex over (p)}, {circumflex over (d)}.sup.6)|

[0117] The variation of parameters may proceed until a change in error is less than a threshold, for example when varying a parameter up to 5% or 10% and the error does not decrease with more than for example 1%. In this case the material parameters are said to be determined and having a value for which the error no longer changes substantially.

[0118] Although the present disclosure has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure. Hence, the present disclosure is deemed limited only by the appended claims and the reasonable interpretation thereof.